TWI555125B - Method for manufacturing package of power module - Google Patents
Method for manufacturing package of power module Download PDFInfo
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- TWI555125B TWI555125B TW103131503A TW103131503A TWI555125B TW I555125 B TWI555125 B TW I555125B TW 103131503 A TW103131503 A TW 103131503A TW 103131503 A TW103131503 A TW 103131503A TW I555125 B TWI555125 B TW I555125B
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Description
本發明是關於半導體封裝體的製造方法，特別是關於功率模組封裝體的製造方法。 The present invention relates to a method of fabricating a semiconductor package, and more particularly to a method of fabricating a power module package.
電動車馬達控制單元中的變頻器(inverter)是由電能轉換成動能最重要關鍵組件，其中影響電能轉換效率最重要部份即是功率電子模組，車用馬達功率模組元件之電壓/電流規格達600V/450A，遠高於一般功率模組及消費性電子IC，且需通過車規AEC-Q101之各項可靠度試驗，因此其封裝技術及材料的門檻極高。功率模組封裝包括將一表面金屬化之陶瓷基板與一金屬散熱底板接合，再將一功率IC晶片固定在陶瓷基板上，然後進行晶片上銲墊與基板上銲墊的連線(interconnection)，最常使用的連線技術是200μm以上粗線徑鋁線的打線接合，陶瓷基板一般使用氧化鋁，其表面金屬化採用銅板，亦即習知的直接接合銅基板(direct bonding copper；DBC)，功率IC晶片、陶瓷基板與金屬散熱底板的接合一般採用錫基合金，由於功率IC晶片、陶瓷基板與金屬散熱底板的面積極大，如果採用一般大氣迴銲方法，在接合過程，熔融錫基合金內部常會殘留大量氣孔，此氣孔在後續功率模組運作時， 會造成接合界面破裂及導熱不佳，因此業界改用真空迴銲方法進行接合，利用真空負壓將錫基合金內部殘留氣體排除。 The inverter in the electric vehicle motor control unit is the most important key component for converting electric energy into kinetic energy. The most important part affecting the electric energy conversion efficiency is the power electronic module, the voltage/current of the vehicle motor power module component. The specification is 600V/450A, which is much higher than the general power module and consumer electronic IC, and needs to pass the reliability test of the car gauge AEC-Q101, so the threshold of its packaging technology and materials is extremely high. The power module package includes bonding a surface-metallized ceramic substrate to a metal heat-dissipating substrate, and then fixing a power IC chip on the ceramic substrate, and then performing an interconnection between the pad on the wafer and the pad on the substrate. The most commonly used wiring technology is wire bonding of thick wire diameter of 200 μm or more. The ceramic substrate is generally made of alumina, and the surface metallization is made of copper plate, which is a conventional direct bonding copper (DBC). The joint of the power IC chip, the ceramic substrate and the metal heat sink is generally made of a tin-based alloy. Since the area of the power IC chip, the ceramic substrate and the metal heat sink is extremely large, if a general atmospheric reflow method is employed, the inside of the molten tin-based alloy is bonded during the bonding process. Often there will be a large number of pores that will remain in the subsequent power module operation. The joint interface is broken and the heat conduction is not good. Therefore, the industry uses the vacuum reflow method to join, and the residual gas inside the tin-based alloy is removed by vacuum negative pressure.
然而此習知的功率模組製作技術有許多缺點，首先錫基合金的熔點在250℃以下，因而限制了功率模組的使用溫度，其次，錫基合金與直接接合銅基板反應極快，將形成很厚的Cu6Sn5介金屬化合物，不僅會導致界面脆裂，更會降低模組的導熱性。 However, this conventional power module fabrication technique has many disadvantages. First, the melting point of the tin-based alloy is below 250 ° C, thereby limiting the use temperature of the power module. Secondly, the tin-based alloy reacts extremely rapidly with the directly bonded copper substrate. The formation of a very thick Cu 6 Sn 5 intermetallic compound not only causes the interface to be brittle, but also reduces the thermal conductivity of the module.
此外，利用真空迴銲方法進行接合仍會留下相當多氣孔，而且如果使用熔點較高的鋅基合金，在真空環境會造成大量鋅蒸發。 In addition, the use of the vacuum reflow method still leaves a considerable amount of pores, and if a zinc-based alloy having a higher melting point is used, a large amount of zinc is evaporated in a vacuum environment.
有鑑於此，本發明的一實施例是提供一種功率模組封裝體，其包含一陶瓷基板、一第一含鈦金屬層、一基板銲墊以及一積體電路晶片。上述陶瓷基板具有一上表面與一下表面；上述第一含鈦金屬層是位於上述陶瓷基板的上表面上，並具有一第一接合區與一第二接合區；上述基板銲墊是連接於上述第一含鈦金屬層的第二接合區；上述積體電路晶片是連接於上述第一含鈦金屬層的第一接合區，並具有一晶片銲墊，上述晶片銲墊是電性連接於上述基板銲墊。 In view of this, an embodiment of the present invention provides a power module package including a ceramic substrate, a first titanium-containing metal layer, a substrate pad, and an integrated circuit chip. The ceramic substrate has an upper surface and a lower surface; the first titanium-containing metal layer is located on the upper surface of the ceramic substrate, and has a first bonding region and a second bonding region; the substrate pad is connected to the above a second bonding region of the first titanium-containing metal layer; the integrated circuit wafer is connected to the first bonding region of the first titanium-containing metal layer, and has a wafer pad, the wafer pad is electrically connected to the above Substrate pad.
在上述之功率模組封裝體中，較好為：上述晶片銲墊是藉由一金屬連線而電性連接於上述基板銲墊，上述金屬連線是選自以下所組成之族群：鋁線、鋁帶、銅線、銅帶、鍍鋁銅線、鍍鋁銅帶、銀合金線及銀合金帶。 Preferably, in the power module package, the wafer pad is electrically connected to the substrate pad by a metal wire, and the metal wire is selected from the group consisting of: aluminum wire , aluminum strip, copper wire, copper strip, aluminized copper wire, aluminized copper strip, silver alloy wire and silver alloy strip.
在上述之功率模組封裝體中，較好為更包含：一 散熱底板；一第二含鈦金屬層，覆蓋上述陶瓷基板的上述下表面；以及一第三含鈦金屬層，覆蓋上述散熱底板的上表面，並接合於上述第二含鈦金屬層而連接上述散熱底板與上述陶瓷基板。 In the above power module package, it is preferable to further include: a heat dissipation substrate; a second titanium-containing metal layer covering the lower surface of the ceramic substrate; and a third titanium-containing metal layer covering the upper surface of the heat dissipation substrate and bonding to the second titanium-containing metal layer to connect the above A heat sink base plate and the above ceramic substrate.
在上述之功率模組封裝體中，較好為更包含：一第一鋅基合金層，在上述積體電路晶片與上述第一含鈦金屬層的上述第一接合區之間，藉以接合上述積體電路晶片與上述第一含鈦金屬層。 Preferably, the power module package further includes: a first zinc-based alloy layer between the integrated circuit wafer and the first bonding region of the first titanium-containing metal layer; The integrated circuit wafer and the first titanium-containing metal layer described above.
在上述之功率模組封裝體中，較好為更包含：一第一鋅基合金層，在上述積體電路晶片與上述第一含鈦金屬層的上述第一接合區之間，藉以接合上述積體電路晶片與上述第一含鈦金屬層。 Preferably, the power module package further includes: a first zinc-based alloy layer between the integrated circuit wafer and the first bonding region of the first titanium-containing metal layer; The integrated circuit wafer and the first titanium-containing metal layer described above.
在上述之功率模組封裝體中，較好為更包含：一第二鋅基合金層，在上述第二含鈦金屬層與上述第三含鈦金屬層之間，藉以接合上述第二含鈦金屬層與上述第三含鈦金屬層。 Preferably, the power module package further includes: a second zinc-based alloy layer between the second titanium-containing metal layer and the third titanium-containing metal layer to bond the second titanium-containing layer The metal layer and the third titanium-containing metal layer described above.
本發明的另一實施例是提供一種功率模組封裝體的製造方法，包含：提供一陶瓷基板，具有一上表面與一下表面，在上述陶瓷基板的上述上表面上，具有一第一含鈦金屬層，上述第一含鈦金屬層具有一第一接合區與一第二接合區；進行第一接合步驟，在第一氣壓下、且為第一保護氣體的氣氛下，以一第一鋅基合金層接合於一積體電路晶片與上述第一含鈦金屬層的上述第一接合區之間，藉以接合上述積體電路晶片與上述第一含鈦金屬層，其中在上述第一接合步驟的接合溫度 是在上述第一鋅基合金層的熔點以上；以及將上述積體電路晶片的一晶片銲墊電性連接一基板銲墊，上述基板銲墊是連接於上述第一含鈦金屬層的上述第二接合區。 Another embodiment of the present invention provides a method of fabricating a power module package, comprising: providing a ceramic substrate having an upper surface and a lower surface, and having a first titanium on the upper surface of the ceramic substrate a metal layer, the first titanium-containing metal layer has a first bonding region and a second bonding region; performing a first bonding step, under a first gas pressure and under a first shielding gas atmosphere, with a first zinc a base alloy layer bonded between the integrated circuit wafer and the first bonding region of the first titanium-containing metal layer, thereby bonding the integrated circuit wafer and the first titanium-containing metal layer, wherein in the first bonding step Bonding temperature And above the melting point of the first zinc-based alloy layer; and electrically connecting a wafer pad of the integrated circuit wafer to a substrate pad, wherein the substrate pad is connected to the first titanium-containing metal layer Two junction areas.
在上述之功率模組封裝體的製造方法中，較好為更包含：進行第二接合步驟，在接合上述積體電路晶片與上述第一含鈦金屬層之前，先在第二氣壓下、且為第二保護氣體的氣氛下，以一第二鋅基合金層接合於覆蓋上述陶瓷基板的上述下表面的一第二含鈦金屬層與覆蓋上述散熱底板的上表面的一第三含鈦金屬層之間，藉以接合上述陶瓷基板與上述散熱底板，其中在上述第二接合步驟的接合溫度是在上述第二鋅基合金層的熔點以上。 In the method of manufacturing the power module package described above, preferably, the method further includes: performing a second bonding step of, prior to bonding the integrated circuit wafer and the first titanium-containing metal layer, at a second air pressure a second zinc-based alloy layer bonded to a second titanium-containing metal layer covering the lower surface of the ceramic substrate and a third titanium-containing metal covering the upper surface of the heat dissipation substrate, in a second protective gas atmosphere The ceramic substrate and the heat dissipation substrate are joined between the layers, wherein the bonding temperature in the second bonding step is equal to or higher than the melting point of the second zinc-based alloy layer.
在上述之功率模組封裝體的製造方法中，較好為：上述鈦合金中的鈦含量為50wt%以上，鈦合金的鈦以外的合金成分包含Cu、Ni、Al、V、Mo的一種或二種以上的組合。 In the method of manufacturing the power module package described above, it is preferable that the titanium content in the titanium alloy is 50% by weight or more, and the alloy component other than titanium of the titanium alloy contains one of Cu, Ni, Al, V, and Mo or Two or more combinations.
在上述之功率模組封裝體的製造方法中，較好為：上述鋅基合金層的鋅含量為80wt%以上，鋅基合金層的鋅以外的合金成分包含Sn、Al、Ag、Ti、Ce的一種或二種以上的組合。 In the above method for manufacturing a power module package, it is preferable that the zinc-based alloy layer has a zinc content of 80% by weight or more, and the alloy component other than zinc of the zinc-based alloy layer contains Sn, Al, Ag, Ti, and Ce. One or a combination of two or more.
在上述之功率模組封裝體的製造方法中，較好為：在上述第一接合步驟的接合溫度為250℃~450℃，在上述第一接合步驟的接合溫度作接合的時間為5分鐘~30分鐘。 In the above method for manufacturing a power module package, it is preferable that a bonding temperature in the first bonding step is 250 to 450 ° C, and a bonding time in the first bonding step is 5 minutes. 30 minutes.
在上述之功率模組封裝體的製造方法中，上述第一氣壓較好為1Kg/cm2~20Kg/cm2。 In the above method of manufacturing a power module package, the first gas pressure is preferably from 1 Kg/cm 2 to 20 kg/cm 2 .
在上述之功率模組封裝體的製造方法中，上述第 一保護氣體較好為氬或氮。 In the above method of manufacturing a power module package, the above A shielding gas is preferably argon or nitrogen.
在上述之功率模組封裝體的製造方法中，較好為：在上述第二接合步驟的接合溫度為250℃~400℃，在上述第二接合步驟的接合溫度作接合的時間為5分鐘~30分鐘。 In the above method for manufacturing a power module package, it is preferable that a bonding temperature in the second bonding step is 250 to 400 ° C, and a bonding time in the second bonding step is 5 minutes. 30 minutes.
在上述之功率模組封裝體的製造方法中，上述第二氣壓較好為1Kg/cm2~20Kg/cm2。 In the method of manufacturing the power module of the package, the second pressure is preferably 1Kg / cm 2 ~ 20Kg / cm 2.
在上述之功率模組封裝體的製造方法中，上述第二保護氣體較好為氬或氮。 In the above method of manufacturing a power module package, the second shielding gas is preferably argon or nitrogen.
在上述之功率模組封裝體的製造方法中，較好為：上述晶片銲墊是藉由一金屬連線而電性連接於上述基板銲墊，上述金屬連線是選自以下所組成之族群：鋁線、鋁帶、銅線、銅帶、鍍鋁銅線、鍍鋁銅帶、銀合金線及銀合金帶。 In the above method for manufacturing a power module package, it is preferable that the wafer pad is electrically connected to the substrate pad by a metal wire, and the metal wire is a group selected from the group consisting of : Aluminum wire, aluminum tape, copper wire, copper tape, aluminum-plated copper wire, aluminum-plated copper tape, silver alloy wire and silver alloy tape.
10‧‧‧積體電路晶片 10‧‧‧Integrated circuit chip
12‧‧‧陶瓷基板 12‧‧‧Ceramic substrate
12a‧‧‧上表面 12a‧‧‧Upper surface
12b‧‧‧下表面 12b‧‧‧ lower surface
14‧‧‧散熱底板 14‧‧‧ Thermal floor
14a‧‧‧上表面 14a‧‧‧Upper surface
15‧‧‧第一含鈦金屬層 15‧‧‧First titanium-containing metal layer
15a‧‧‧第一接合區 15a‧‧‧First junction area
15b‧‧‧第二接合區 15b‧‧‧Second junction
16‧‧‧第一鋅基合金層 16‧‧‧First zinc-based alloy layer
17‧‧‧晶片銲墊 17‧‧‧ wafer pads
18‧‧‧金屬連線 18‧‧‧Metal connection
19‧‧‧基板銲墊 19‧‧‧Substrate pads
25‧‧‧第二含鈦金屬層 25‧‧‧Second titanium-containing metal layer
26‧‧‧第二鋅基合金層 26‧‧‧Second zinc-based alloy layer
35‧‧‧第三含鈦金屬層 35‧‧‧ Third titanium-containing metal layer
50、55‧‧‧腔體 50, 55‧‧‧ cavity
第1圖是一側視圖，顯示本發明一實施例之功率模組封裝體。 1 is a side view showing a power module package according to an embodiment of the present invention.
第2圖是一側視圖，顯示本發明一實施例之功率模組封裝體的製造方法的一中間階段。 Fig. 2 is a side elevational view showing an intermediate stage of a method of fabricating a power module package in accordance with an embodiment of the present invention.
第3圖是一側視圖，顯示本發明一實施例之功率模組封裝體的製造方法的一中間階段。 Figure 3 is a side elevational view showing an intermediate stage of a method of fabricating a power module package in accordance with an embodiment of the present invention.
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下： 要瞭解的是本說明書以下的揭露內容提供許多不同的實施例或範例，以實施本發明的不同特徵。以下將配合所附圖式詳述本發明之實施例，其中同樣或類似的元件將盡可能以相同的元件符號表示。在圖式中可能誇大實施例的形狀與厚度以便清楚表面本發明之特徵。而本說明書以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化發明的說明。當然，這些特定的範例並非用以限定本發明。例如，若是本說明書以下的揭露內容敘述了將一第一特徵形成於一第一特徵之上或上方，即表示其包含了所形成的上述第一特徵與上述第二特徵是直接接觸的實施例，亦包含了尚可將附加的特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與上述第二特徵可能未直接接觸的實施例。另外，本說明書以下的揭露內容可能在各個範例中使用重複的元件符號，以使說明內容更加簡化、明確，但是重複的元件符號本身並未指示不同的實施例及/或結構之間的關係。 The above and other objects, features and advantages of the present invention will become more <RTIgt; It is to be understood that the following disclosure of the specification provides many different embodiments or examples to implement various features of the invention. Embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein the same or similar elements will be denoted by the same reference numerals. The shapes and thicknesses of the embodiments may be exaggerated in the drawings in order to clarify the features of the invention. The disclosure of the present specification is a specific example of the various components and their arrangement in order to simplify the description of the invention. Of course, these specific examples are not intended to limit the invention. For example, if the disclosure of the present specification describes forming a first feature on or above a first feature, that is, it includes an embodiment in which the formed first feature is in direct contact with the second feature. Also included is an embodiment in which additional features are formed between the first feature and the second feature described above, such that the first feature and the second feature may not be in direct contact. In addition, the disclosure of the present disclosure may be repeated in the various examples to make the description more simplified and clear, but the repeated element symbols themselves do not indicate the relationship between different embodiments and/or structures.
另外，在本案專利說明書中，在數值相關敘述後接「以上」、「以下」之詞來敘述數值範圍的情況中，除非另有加註，相關的數值範圍是包含上述「以上」、「以下」之詞前接的數值。 In addition, in the case of the numerical description, the words "above" and "below" are used to describe the numerical range. Unless otherwise noted, the relevant numerical range includes the above "above" and "below". The value preceded by the word.
關於本案專利說明書全文所述「實質上的純鈦」等實質上的純物質的敘述，係指在設計上期望為完全不含其他元素、化合物等的雜質的純鈦，但在實際冶煉、精煉、鍍膜等的過程中卻難以完全除去上述雜質而達成數學上或理論上含100%的純鈦，而當上述雜質含量的範圍落於對應的標準或規格 所訂定的允收範圍內，就視為「實質上的純鈦」。其他任何的實質上的純物質的意義亦同。本發明所屬技術領域中具有通常知識者應當瞭解依據不同的性質、條件、需求等等，上述對應的標準或規格會有所不同，故下文中並未列出特定的標準或規格。 The description of a substantially pure substance such as "substantially pure titanium" as used throughout the patent specification of the present invention means pure titanium which is designed to be completely free of impurities such as other elements and compounds, but is actually smelted and refined. In the process of coating, etc., it is difficult to completely remove the above impurities to achieve 100% pure or theoretically pure titanium, and when the above impurity content falls within the corresponding standard or specification Within the specified allowable range, it is considered to be "substantially pure titanium". The meaning of any other substantially pure substance is the same. Those having ordinary skill in the art to which the present invention pertains should understand that the above-mentioned corresponding standards or specifications may vary depending on different properties, conditions, requirements, etc., and thus specific standards or specifications are not listed below.
首先，請參考第1圖，針對本發明一實施例之功率模組封裝體來作說明。 First, please refer to FIG. 1 for a description of a power module package according to an embodiment of the present invention.
在第1圖中，本發明一實施例之功率模組封裝體是包含一陶瓷基板12、一第一含鈦金屬層15、一基板銲墊19以及一積體電路晶片10。 In the first embodiment, a power module package according to an embodiment of the present invention includes a ceramic substrate 12, a first titanium-containing metal layer 15, a substrate pad 19, and an integrated circuit wafer 10.
陶瓷基板12可以整塊都是陶瓷材料構成的基板，亦可以是內含數個堆疊的電路層結構的層積陶瓷基板。陶瓷基板12具有一上表面12a與一下表面12b。 The ceramic substrate 12 may be a substrate made of a ceramic material as a whole, or may be a laminated ceramic substrate having a plurality of stacked circuit layer structures. The ceramic substrate 12 has an upper surface 12a and a lower surface 12b.
第一含鈦金屬層15是位於陶瓷基板12的上表面12a上，並具有一第一接合區15a與一第二接合區15b。在某些實施例中，第一含鈦金屬層15是被圖形化而形成電路圖形，上述電路圖形包含第一接合區15a與第二接合區15b。在某些實施例中，第一接合區15a與第二接合區15b是相互隔離的，但為了顯示上的方面，從第1圖未顯示第一接合區15a與第二接合區15b是相互隔離的情況。此外，可具有複數個第二接合區15b，這些第二接合區15b可以是相互隔離的，亦有因設計上的需求，有數個第二接合區15b是相互連接但與其他第二接合區15b是相互隔離的情況。 The first titanium-containing metal layer 15 is on the upper surface 12a of the ceramic substrate 12 and has a first land 15a and a second land 15b. In some embodiments, the first titanium-containing metal layer 15 is patterned to form a circuit pattern, and the circuit pattern includes a first land 15a and a second land 15b. In some embodiments, the first land 15a and the second land 15b are isolated from each other, but for the sake of display, the first land 15a and the second land 15b are not isolated from FIG. Case. In addition, there may be a plurality of second joint regions 15b, which may be isolated from each other, and also have a plurality of second joint regions 15b connected to each other but with other second joint regions 15b due to design requirements. It is a situation of isolation from each other.
基板銲墊10是連接於第一含鈦金屬層15的第二接 合區15b。在前述具有複數個第二接合區15b時，亦可具有對應數量的基板銲墊19連接於對應的基板銲墊19。在一實施例中，基板銲墊19是銅銲墊，視需求其表面可鍍上鎳、金、鈀、上述之合金、上述金屬層的堆疊層或其他適合的金屬層，有助於銅銲墊的防蝕及/或與其他元件的接合等。 The substrate pad 10 is connected to the second connection of the first titanium-containing metal layer 15 Constituency 15b. When the plurality of second bonding regions 15b are provided, a corresponding number of substrate pads 19 may be connected to the corresponding substrate pads 19. In an embodiment, the substrate pad 19 is a copper pad, and the surface thereof may be plated with nickel, gold, palladium, the above alloy, a stacked layer of the above metal layer or other suitable metal layer to facilitate brazing. Corrosion of the mat and/or bonding with other components.
積體電路晶片10是連接於第一含鈦金屬層15的第一接合區15a，並具有一晶片銲墊17，上述晶片銲墊17是電性連接於基板銲墊19。晶片銲墊17、基板銲墊19的數量及電性連接的方式，是可依照實際產品的需求作設計上的變更。在某些實施例中，積體電路晶片10是一功率晶片；在其他實施例中，積體電路晶片10是其他用途的晶片。 The integrated circuit wafer 10 is connected to the first bonding region 15a of the first titanium-containing metal layer 15 and has a wafer pad 17 electrically connected to the substrate pad 19. The number of the wafer pads 17 and the substrate pads 19 and the manner of electrical connection are designed to be changed according to the requirements of the actual product. In some embodiments, integrated circuit die 10 is a power die; in other embodiments, integrated circuit die 10 is a wafer for other uses.
關於晶片銲墊17與基板銲墊19的電性連接，在一實施例中，晶片銲墊17是藉由一金屬連線18而電性連接於基板銲墊19。金屬連線18可以是鋁線、鋁帶、銅線、銅帶、鍍鋁銅線、鍍鋁銅帶、銀合金線、銀合金帶或其他適用的金屬連線材料。 Regarding the electrical connection between the die pad 17 and the substrate pad 19, in one embodiment, the die pad 17 is electrically connected to the substrate pad 19 by a metal wire 18. The metal wire 18 can be an aluminum wire, an aluminum tape, a copper wire, a copper tape, an aluminum-plated copper wire, an aluminum-plated copper tape, a silver alloy wire, a silver alloy tape, or other suitable metal wire material.
在本實施例中，關於積體電路晶片10與第一含鈦金屬層15之間的接合，是藉由在積體電路晶片10與第一含鈦金屬層15的第一接合區15a之間的一第一鋅基合金層16來達成。第一含鈦金屬層15與第一鋅基合金層16的成分及彼此之間的交互作用的細節，容後敘述。 In the present embodiment, the bonding between the integrated circuit wafer 10 and the first titanium-containing metal layer 15 is between the integrated circuit wafer 10 and the first bonding region 15a of the first titanium-containing metal layer 15. A first zinc-based alloy layer 16 is achieved. Details of the composition of the first titanium-containing metal layer 15 and the first zinc-based alloy layer 16 and the interaction between each other will be described later.
積體電路晶片10是一功率晶片時，在運作過程往往會產生龐大的熱量，若這些熱量未能即時被疏散，則可能使積體電路晶片10暫時停止運作甚至故障，亦有可能造成積體電 路晶片10與陶瓷基板12之間的接點的破壞、及/或前述其他各個元件之間的接點的破壞。 When the integrated circuit chip 10 is a power chip, a large amount of heat is generated during operation. If the heat is not immediately evacuated, the integrated circuit chip 10 may be temporarily stopped or even malfunctioned, and the integrated body may be caused. Electricity Destruction of the joint between the wafer 104 and the ceramic substrate 12, and/or destruction of the joint between the other respective elements described above.
因此，本發明之功率模組封裝體較好為連接一散熱結構，例示的散熱結構一併顯示於第1圖中，包含一散熱底板14、一第二含鈦金屬層25以及一第三含鈦金屬層35。第二含鈦金屬層25是覆蓋陶瓷基板12的下表面12b；第三含鈦金屬層35是覆蓋散熱底板14的上表面14a，並接合於第二含鈦金屬層25而連接散熱底板14與陶瓷基板12。陶瓷基板12是內含數個堆疊的電路層結構的層積陶瓷基板時，這些電路層結構可內建導熱路徑，將積體電路晶片10產生的熱量導引至陶瓷基板12的下表面12b，再傳達至散熱底板14。散熱底板14可以是任何目前已使用的散熱器結構。 Therefore, the power module package of the present invention is preferably connected to a heat dissipation structure. The illustrated heat dissipation structure is also shown in FIG. 1 and includes a heat dissipation substrate 14, a second titanium-containing metal layer 25, and a third Titanium metal layer 35. The second titanium-containing metal layer 25 covers the lower surface 12b of the ceramic substrate 12; the third titanium-containing metal layer 35 covers the upper surface 14a of the heat dissipation substrate 14, and is bonded to the second titanium-containing metal layer 25 to connect the heat dissipation substrate 14 with Ceramic substrate 12. When the ceramic substrate 12 is a laminated ceramic substrate having a plurality of stacked circuit layer structures, the circuit layer structure can have a built-in heat conduction path to guide the heat generated by the integrated circuit wafer 10 to the lower surface 12b of the ceramic substrate 12. Then communicated to the heat sink base plate 14. The heat sink base 14 can be any heat sink structure that has been used so far.
在本實施例中，關於第二含鈦金屬層25與第三含鈦金屬層35之間的接合，是藉由在第二含鈦金屬層25與第三含鈦金屬層35之間的一第二鋅基合金層26來達成。第二含鈦金屬層25、第三含鈦金屬層35與第二鋅基合金層26的成分及彼此之間的交互作用的細節，容後敘述。 In the present embodiment, the bonding between the second titanium-containing metal layer 25 and the third titanium-containing metal layer 35 is by a layer between the second titanium-containing metal layer 25 and the third titanium-containing metal layer 35. The second zinc-based alloy layer 26 is achieved. Details of the composition of the second titanium-containing metal layer 25, the third titanium-containing metal layer 35 and the second zinc-based alloy layer 26, and the interaction between each other will be described later.
第1圖所示的功率模組封裝體，可藉由已知的模封製程及材料，將積體電路晶片10、晶片銲墊17、金屬連線18、基板銲墊19、陶瓷基板12的上表面12a等予以密封，但此非本案發明的重點，在第1圖中並未加以呈現，其詳細敘述亦予以省略。 In the power module package shown in FIG. 1, the integrated circuit wafer 10, the wafer pad 17, the metal wiring 18, the substrate pad 19, and the ceramic substrate 12 can be formed by a known molding process and material. The upper surface 12a and the like are sealed, but the focus of the present invention is not shown in the first drawing, and the detailed description thereof is also omitted.
接下來，請參考第2、3圖，針對本發明一實施例之功率模組封裝體的製造方法來作說明。 Next, please refer to FIGS. 2 and 3 for a description of a method of manufacturing a power module package according to an embodiment of the present invention.
在需要連接散熱結構的實施例中，較好為先如第2圖所示，接合陶瓷基板12與散熱底板14。在不需要連接散熱結構的實施例中，則可跳過第2圖的相關敘述，參考第3圖相關敘述的陶瓷基板12與積體電路晶片10的接合。 In the embodiment in which the heat dissipation structure needs to be connected, it is preferable to bond the ceramic substrate 12 and the heat dissipation substrate 14 as shown in Fig. 2 first. In the embodiment in which the heat dissipation structure is not required, the related description of FIG. 2 can be skipped, and the bonding of the ceramic substrate 12 and the integrated circuit wafer 10 described in connection with FIG. 3 can be referred to.
如第2圖所示，提供如前述的陶瓷基板12及散熱底板14。此時，在陶瓷基板12的上表面12a上，具有第一含鈦金屬層15，第一含鈦金屬層15具有第一接合區15a與第二接合區15b(請參考第1圖所示的第一接合區15a與第二接合區15b)，而覆第二含鈦金屬層25則覆蓋陶瓷基板12的下表面12b。另外，第三含鈦金屬層35則覆蓋散熱底板14的上表面14a。 As shown in Fig. 2, the ceramic substrate 12 and the heat dissipation substrate 14 as described above are provided. At this time, on the upper surface 12a of the ceramic substrate 12, there is a first titanium-containing metal layer 15, and the first titanium-containing metal layer 15 has a first bonding region 15a and a second bonding region 15b (please refer to FIG. 1 The first bonding region 15a and the second bonding region 15b) cover the lower surface 12b of the ceramic substrate 12 with the second titanium-containing metal layer 25. In addition, the third titanium-containing metal layer 35 covers the upper surface 14a of the heat dissipation substrate 14.
在一實施例中，將含第二鋅基合金層26的預定成分與助銲劑等成分混合調製而成的膏狀物(俗稱「錫膏」)以任何已知的方法(例如模板印刷法、以刮刀塗布等)塗布於第三含鈦金屬層35及/或第二含鈦金屬層25。然後，例如在一腔體50內，在第二氣壓下、且為第二保護氣體的氣氛下，加熱至第二鋅基合金層26的熔點以上，持續一既定時間後冷卻，而接合第二含鈦金屬層25與第三含鈦金屬層35，從而接合陶瓷基板12與散熱底板14。 In one embodiment, a paste containing a predetermined component of the second zinc-based alloy layer 26 and a component such as a flux (commonly known as "solder paste") is prepared by any known method (for example, a stencil printing method, It is applied to the third titanium-containing metal layer 35 and/or the second titanium-containing metal layer 25 by doctor blade coating or the like. Then, for example, in a cavity 50, under a second gas pressure and under a second protective gas atmosphere, it is heated to above the melting point of the second zinc-based alloy layer 26, and is cooled for a predetermined period of time, and joined to the second. The titanium-containing metal layer 25 and the third titanium-containing metal layer 35 are bonded to the ceramic substrate 12 and the heat dissipation substrate 14.
在上述步驟中，上述第二保護氣體較好為氬或氮，上述第二氣壓較好為正壓。所謂「正壓」，一般指的是大於一大氣壓(1.0336Kg/cm2)的氣壓，但在實際操作的情況下，只要所用壓力大於操作當時當地實際的大氣壓力，即為「正壓」。在一實施例中，上述第二氣壓的範圍是1Kg/cm2~20Kg/cm2，第二鋅基合金層26的熔點以上的接合溫度較好為250 ℃~450℃，保持在上述接合溫度作接合的時間較好為5分鐘~30分鐘。 In the above step, the second shielding gas is preferably argon or nitrogen, and the second gas pressure is preferably a positive pressure. The term "positive pressure" generally refers to a gas pressure greater than one atmosphere (1.0336 Kg/cm 2 ). However, in actual operation, the pressure is greater than the actual atmospheric pressure at the time of operation. In one embodiment, the second gas pressure ranges from 1 Kg/cm 2 to 20 Kg/cm 2 , and the second zinc-based alloy layer 26 has a bonding temperature of preferably 250 ° C to 450 ° C above the bonding temperature. The bonding time is preferably from 5 minutes to 30 minutes.
接下來，請參考第3圖，在一實施例中，將含第一鋅基合金層16的預定成分與助銲劑等成分混合調製而成的膏狀物(俗稱「錫膏」)以任何已知的方法(例如模板印刷法、以刮刀塗布等)塗布於第一含鈦金屬層15的第一接合區15a(請參考第1圖)及/或積體電路晶片10的預定接合面。然後，例如在同一腔體50或轉移至另一腔體55內，在第一氣壓下、且為第一保護氣體的氣氛下，加熱至第一鋅基合金層16的熔點以上，持續一既定時間後冷卻，而接合第一含鈦金屬層15與積體電路晶片10，從而接合陶瓷基板12與積體電路晶片10。 Next, referring to FIG. 3, in one embodiment, a paste (commonly referred to as "solder paste") prepared by mixing a predetermined component of the first zinc-based alloy layer 16 with a flux and the like is used. A known method (for example, stencil printing, blade coating, or the like) is applied to the first bonding region 15a of the first titanium-containing metal layer 15 (refer to FIG. 1) and/or the predetermined bonding surface of the integrated circuit wafer 10. Then, for example, in the same cavity 50 or transferred to another cavity 55, under the first gas pressure and under the atmosphere of the first shielding gas, it is heated to above the melting point of the first zinc-based alloy layer 16 for a predetermined period. After the time is cooled, the first titanium-containing metal layer 15 and the integrated circuit wafer 10 are bonded, thereby bonding the ceramic substrate 12 and the integrated circuit wafer 10.
在上述步驟中，上述第一保護氣體較好為氬或氮，上述第一氣壓較好為正壓，「正壓」的定義如前所述。在一實施例中，上述第一氣壓的範圍是1Kg/cm2~20Kg/cm2，第一鋅基合金層16的熔點以上的接合溫度較好為250℃~450℃，保持在上述接合溫度作接合的時間較好為5分鐘~30分鐘。 In the above step, the first shielding gas is preferably argon or nitrogen, and the first gas pressure is preferably a positive pressure, and the "positive pressure" is as defined above. In one embodiment, the first gas pressure ranges from 1 Kg/cm 2 to 20 Kg/cm 2 , and the bonding temperature of the first zinc-based alloy layer 16 or more is preferably from 250 ° C to 450 ° C, and is maintained at the above-mentioned joining temperature. The bonding time is preferably from 5 minutes to 30 minutes.
然後，將積體電路晶片10的晶片銲墊17電性連接基板銲墊19，其中基板銲墊19是連接於第一含鈦金屬層15的第二接合區15b(請參考第1圖)。上述電性連接的方法例如為銲線接合或其他適當的方法，形成如第1圖所示的金屬連線18。金屬連線18可以是鋁線、鋁帶、銅線、銅帶、鍍鋁銅線、鍍鋁銅帶、銀合金線、銀合金帶或其他適用的金屬連線材料。 Then, the wafer pads 17 of the integrated circuit wafer 10 are electrically connected to the substrate pads 19, wherein the substrate pads 19 are connected to the second bonding regions 15b of the first titanium-containing metal layer 15 (please refer to FIG. 1). The above method of electrical connection is, for example, wire bonding or other suitable method to form the metal wiring 18 as shown in FIG. The metal wire 18 can be an aluminum wire, an aluminum tape, a copper wire, a copper tape, an aluminum-plated copper wire, an aluminum-plated copper tape, a silver alloy wire, a silver alloy tape, or other suitable metal wire material.
然後，可以使用模封或其他適當的密封方法，使積體電路晶片10、晶片銲墊17、金屬連線18、基板銲墊19、陶 瓷基板12的上表面12a等與外界隔離。 Then, the integrated circuit wafer 10, the wafer pad 17, the metal wiring 18, the substrate pad 19, and the ceramic can be used by molding or other suitable sealing method. The upper surface 12a of the porcelain substrate 12 and the like are isolated from the outside.
本發明乃經過諸位發明人長久、精心的研究，尋找出適當熔點與強度的接合填充金屬，同時配合適當的擴散障礙金屬層，在最佳正壓環境及溫度時間條件下進行功率積體電路晶片、陶瓷基板及散熱底板的接合，由於使用熔點較高的鋅基合金作為第一鋅基合金層16、第二鋅基合金層26，此模組可以耐較高溫度。第一含鈦金屬層15、第二含鈦金屬層25、第三含鈦金屬層35中的鈦金屬具有極佳的擴散障礙功能，可以防止與第一鋅基合金層16、第二鋅基合金層26的接合界面形成太厚的脆性介金屬反應層。一般錫基合金無法與鈦金屬層潤濕，但鋅基合金由於鋅元素的活性，與鈦金屬可以充分反應並接合。此外，習知技術與消除大面積接合氣孔率，均使用真空迴銲方法，但因為鋅元素的蒸氣壓極高，在真空迴銲時鋅元素將大量蒸發，因此本發明採用正壓迴銲，一方面可以更有效消除大面積接合氣孔率，同時避免鋅元素的蒸發。本發明完美設計組合，所製作完成的功率模組封裝可達到氣孔率低於1%及接合強度高於50MPa的功率模組接合界面。 The present invention has been subjected to long-term and meticulous research by the inventors to find a joint filler metal having a suitable melting point and strength, and at the same time, with a suitable diffusion barrier metal layer, to perform power integrated circuit wafers under optimal positive pressure environment and temperature time conditions. The joint of the ceramic substrate and the heat dissipation substrate can withstand higher temperatures by using a zinc-based alloy having a higher melting point as the first zinc-based alloy layer 16 and the second zinc-based alloy layer 26. The titanium metal in the first titanium-containing metal layer 15, the second titanium-containing metal layer 25, and the third titanium-containing metal layer 35 has an excellent diffusion barrier function, and can prevent the first zinc-based alloy layer 16 and the second zinc-based layer. The bonding interface of the alloy layer 26 forms a brittle intermetallic reaction layer that is too thick. Generally, tin-based alloys cannot be wetted with a titanium metal layer, but zinc-based alloys can sufficiently react and bond with titanium metal due to the activity of zinc. In addition, the conventional technique and the elimination of the large-area joint porosity have used the vacuum reflow method, but since the vapor pressure of the zinc element is extremely high, the zinc element will be largely evaporated during the vacuum reflow, so the present invention uses positive pressure reflow, On the one hand, it can effectively eliminate the large-area joint porosity and avoid the evaporation of zinc. The perfect design combination of the invention can produce a power module package with a power module joint interface with a porosity of less than 1% and a joint strength of more than 50 MPa.
在一實施例中，為了達成上述功效，第一含鈦金屬層15、第二含鈦金屬層25、第三含鈦金屬層35是由實質上的純鈦構成；在其他實施例中，第一含鈦金屬層15、第二含鈦金屬層25、第三含鈦金屬層35是由鈦與其他金屬元素組合的鈦合金構成，此鈦合金中的鈦含量較好為50wt%以上，若鈦含量低於50wt%，則有擴散障礙功能不足的問題。此外，以不妨礙擴散障礙功能及/或與鋅基合金的潤濕性為前提，上述鈦合金的 鈦以外的合金成分亦可包含Cu、Ni、Al、V、Mo等元素的一種或二種以上。 In one embodiment, in order to achieve the above effects, the first titanium-containing metal layer 15, the second titanium-containing metal layer 25, and the third titanium-containing metal layer 35 are composed of substantially pure titanium; in other embodiments, The titanium-containing metal layer 15, the second titanium-containing metal layer 25, and the third titanium-containing metal layer 35 are made of a titanium alloy in combination with titanium and other metal elements, and the titanium content in the titanium alloy is preferably 50% by weight or more. When the titanium content is less than 50% by weight, there is a problem that the function of diffusion barrier is insufficient. Further, the titanium alloy is premised on the premise of not impeding the diffusion barrier function and/or the wettability with the zinc-based alloy. The alloy component other than titanium may contain one or more of elements such as Cu, Ni, Al, V, and Mo.
在一實施例中，為了達成上述功效，第一鋅基合金層16、第二鋅基合金層26中的鋅含量較好為80wt%以上，若鋅含量低於80wt%，則有與鈦金屬層的潤濕性不足的問題。此外，以不妨礙與鈦金屬層的潤濕性為前提，第一鋅基合金層16、第二鋅基合金層26中的鋅以外的合金成分亦可包含Sn、Al、Ag、Ti、Ce等元素的一種或二種以上。 In an embodiment, in order to achieve the above effects, the zinc content in the first zinc-based alloy layer 16 and the second zinc-based alloy layer 26 is preferably 80% by weight or more, and if the zinc content is less than 80% by weight, there is a titanium metal. The problem of insufficient wettability of the layer. Further, the alloy component other than zinc in the first zinc-based alloy layer 16 and the second zinc-based alloy layer 26 may contain Sn, Al, Ag, Ti, Ce, without impeding the wettability with the titanium metal layer. One or more of the elements.
在較佳實施例，是以一Zn-20Sn合金作為第一鋅基合金層16(厚度：1mm)、第二鋅基合金層26(厚度：1mm)，藉由前述步驟，在300℃及10Kg/cm2與純鈦成分的第一含鈦金屬層15(厚度：1mm)、第二含鈦金屬層25(厚度：1mm)、第三含鈦金屬層35(厚度：1mm)接合30分鐘。經觀察，其界面完全無氣孔，且接合強度高達100MPa，接合完成界面介金屬厚度約18μm。 In a preferred embodiment, a Zn-20Sn alloy is used as the first zinc-based alloy layer 16 (thickness: 1 mm) and the second zinc-based alloy layer 26 (thickness: 1 mm) by the foregoing steps at 300 ° C and 10 Kg. /cm 2 was bonded to the first titanium-containing metal layer 15 (thickness: 1 mm) of the pure titanium component, the second titanium-containing metal layer 25 (thickness: 1 mm), and the third titanium-containing metal layer 35 (thickness: 1 mm) for 30 minutes. It was observed that the interface was completely free of pores, and the joint strength was as high as 100 MPa, and the interfacial metal thickness of the joint was about 18 μm.
在另一較佳實施例，是以一Zn-6Al-6Ag-0.2Ce合金作為第一鋅基合金層16(厚度：1mm)、第二鋅基合金層26(厚度：1mm)，藉由前述步驟，在420℃及10Kg/cm2與Ti-20Cu-10Ni成分的第一含鈦金屬層15(厚度：1mm)、第二含鈦金屬層25(厚度：1mm)、第三含鈦金屬層35(厚度：1mm)接合30分鐘。經觀察，其界面完全無氣孔，且接合強度高達124MPa。 In another preferred embodiment, a Zn-6Al-6Ag-0.2Ce alloy is used as the first zinc-based alloy layer 16 (thickness: 1 mm) and the second zinc-based alloy layer 26 (thickness: 1 mm), by the foregoing step, at 420 ℃ and 10Kg / cm 2 with Ti-20Cu-10Ni composition of the first titanium metal layer 15 (thickness: 1mm), the second titanium-containing metal layer 25 (thickness: 1mm), a third layer of titanium metal-containing 35 (thickness: 1 mm) was joined for 30 minutes. It was observed that the interface was completely free of pores and the joint strength was as high as 124 MPa.
在另一較佳實施例，是以一Zn-4Ag-4Ti-0.2Ce合金作為第一鋅基合金層16(厚度：1mm)、第二鋅基合金層26(厚度：1mm)，藉由前述步驟，在450℃及10Kg/cm2與Ti-6Al-6V-2Mo 成分的第一含鈦金屬層15(厚度：1mm)、第二含鈦金屬層25(厚度：1mm)、第三含鈦金屬層35(厚度：1mm)接合30分鐘。經觀察，其界面完全無氣孔，且接合強度高達156MPa。 In another preferred embodiment, a Zn-4Ag-4Ti-0.2Ce alloy is used as the first zinc-based alloy layer 16 (thickness: 1 mm) and the second zinc-based alloy layer 26 (thickness: 1 mm), by the foregoing Step, the first titanium-containing metal layer 15 (thickness: 1 mm), the second titanium-containing metal layer 25 (thickness: 1 mm), and the third titanium-containing layer at 450 ° C and 10 Kg/cm 2 and Ti-6Al-6V-2Mo composition The metal layer 35 (thickness: 1 mm) was joined for 30 minutes. It was observed that the interface was completely free of pores and the joint strength was as high as 156 MPa.
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above preferred embodiments, the present invention is not intended to limit the invention, and it is possible to make a few changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.
10‧‧‧積體電路晶片 10‧‧‧Integrated circuit chip
12‧‧‧陶瓷基板 12‧‧‧Ceramic substrate
12a‧‧‧上表面 12a‧‧‧Upper surface
12b‧‧‧下表面 12b‧‧‧ lower surface
14‧‧‧散熱底板 14‧‧‧ Thermal floor
14a‧‧‧上表面 14a‧‧‧Upper surface
15‧‧‧第一含鈦金屬層 15‧‧‧First titanium-containing metal layer
15a‧‧‧第一接合區 15a‧‧‧First junction area
15b‧‧‧第二接合區 15b‧‧‧Second junction
17‧‧‧晶片銲墊 17‧‧‧ wafer pads
18‧‧‧金屬連線 18‧‧‧Metal connection
19‧‧‧基板銲墊 19‧‧‧Substrate pads
25‧‧‧第二含鈦金屬層 25‧‧‧Second titanium-containing metal layer
35‧‧‧第三含鈦金屬層 35‧‧‧ Third titanium-containing metal layer
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