JP5946286B2 - Power semiconductor device and manufacturing method thereof - Google Patents

Power semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
JP5946286B2
JP5946286B2 JP2012033266A JP2012033266A JP5946286B2 JP 5946286 B2 JP5946286 B2 JP 5946286B2 JP 2012033266 A JP2012033266 A JP 2012033266A JP 2012033266 A JP2012033266 A JP 2012033266A JP 5946286 B2 JP5946286 B2 JP 5946286B2
Authority
JP
Japan
Prior art keywords
power semiconductor
semiconductor element
metal
lead frame
metal lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2012033266A
Other languages
Japanese (ja)
Other versions
JP2013171878A (en
Inventor
芳雄 藤井
芳雄 藤井
寺崎　浩則
浩則 寺崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New Japan Radio Co Ltd
Original Assignee
New Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New Japan Radio Co Ltd filed Critical New Japan Radio Co Ltd
Priority to JP2012033266A priority Critical patent/JP5946286B2/en
Publication of JP2013171878A publication Critical patent/JP2013171878A/en
Application granted granted Critical
Publication of JP5946286B2 publication Critical patent/JP5946286B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

本発明はパワー半導体装置及びその製造方法、特にパワー半導体素子を金属リードフレームへ接合させる構造を持ち、高放熱性、環境性及びオーディオ信号の伝送特性に優れた半導体装置に関する。   The present invention relates to a power semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a structure in which a power semiconductor element is bonded to a metal lead frame and having excellent heat dissipation, environmental friendliness, and audio signal transmission characteristics.

従来から、家電機器、ＯＡ機器、音響機器等の電源には、ダイオードやトランジスタ等のパワー（電力制御用）半導体装置が用いられており、このパワー半導体装置は、例えば図１１のような構造となっている。図１１のパワー半導体装置では、パワー半導体素子１の裏面電極を半田（接合材）２を用いて比較的大きな面積の金属リードフレーム３へ固着させ、この金属リードフレーム３の内部リード部４とパワー半導体素子１の表面電極を金属線５により接続し、全体を樹脂６にて封止する構成とされ、上記金属リードフレーム３には外部電極７ａ、内部リード部４には外部電極７ｂが接続される。また、上記金属リードフレーム３の端部には、金属リードフレーム３と樹脂６を共に貫通する取付け用の孔８が形成されている。近年、上記金属線５として、パワー半導体素子１の大電流化及びコストダウンの要求を受け、２００〜５００μｍ径のアルミニウム線が用いられている。   Conventionally, power (power control) semiconductor devices such as diodes and transistors have been used as power sources for home appliances, OA devices, acoustic devices, and the like. It has become. In the power semiconductor device of FIG. 11, the back electrode of the power semiconductor element 1 is fixed to a metal lead frame 3 having a relatively large area using solder (joining material) 2, and the internal lead portion 4 of the metal lead frame 3 and the power The surface electrode of the semiconductor element 1 is connected by a metal wire 5 and the whole is sealed with a resin 6. An external electrode 7 a is connected to the metal lead frame 3, and an external electrode 7 b is connected to the internal lead portion 4. The An attachment hole 8 that penetrates both the metal lead frame 3 and the resin 6 is formed at the end of the metal lead frame 3. In recent years, an aluminum wire having a diameter of 200 to 500 μm has been used as the metal wire 5 in response to a demand for a large current and cost reduction of the power semiconductor element 1.

また、従来では、更なる高放熱性の実現に向け、例えば下記特許文献１（特開２００６−６６８１３号公報）に示されるように、パワー半導体素子を導電性金属部材で挟み込む構造とし、この金属部材を放熱板として利用する方法も提案されている。   Conventionally, in order to achieve further high heat dissipation, for example, as shown in Patent Document 1 (Japanese Patent Application Laid-Open No. 2006-66813), a power semiconductor element is sandwiched between conductive metal members. A method of using a member as a heat sink has also been proposed.

一方、オーディオ及び各種通信用装置に関しては、下記特許文献２（特開平１０−１８９８５１号公報）のダイオード、或いはトランジスタ、ＦＥＴ等が用いられるが、これらにおいて、高音質特性を向上させるためには、半導体素子を配置するリードフレームに無酸素銅材が有効であることが示されている。この特許文献２では、上記半導体素子の無酸素銅材リードフレームへの接合は、導電性・熱伝導性に優れた半田を用いることが前提とされている。   On the other hand, for audio and various communication devices, the diode, transistor, FET, or the like of the following Patent Document 2 (Japanese Patent Laid-Open No. 10-189851) is used. In order to improve the high sound quality characteristics, It has been shown that an oxygen-free copper material is effective for a lead frame in which a semiconductor element is arranged. In this Patent Document 2, it is assumed that the semiconductor element is bonded to the oxygen-free copper lead frame using solder having excellent conductivity and thermal conductivity.

また、上記パワー半導体素子１自体の製造では、ウェハー（集合基板）内にパワー半導体回路を複数個形成し、この集合基板の切削ラインに沿ってブレードを高速回転させながら切削すること（ダイシング法）により、個々のパワー半導体素子１が製作される。このダイシング作業は、通常ダイシングテープと呼ばれる粘着テープに貼り付けて行うが、このパワー半導体素子１の搬送の際には、粘着テープの粘着力をＵＶ照射などによって低下させた後、突上げ針（金属針）をテープ側よりパワー半導体素子１を突き上げることによって、パワー半導体素子１がテープ側より剥がされた状態となり、その後、このパワー半導体素子１は、吸着孔を有する円柱形のコレットと呼ばれるツールによって容易に吸着保持される。   Further, in the manufacture of the power semiconductor element 1 itself, a plurality of power semiconductor circuits are formed in a wafer (aggregate substrate), and cutting is performed while rotating the blade at a high speed along the cutting line of the aggregate substrate (dicing method). Thus, the individual power semiconductor elements 1 are manufactured. This dicing operation is usually performed by adhering to an adhesive tape called a dicing tape. When the power semiconductor element 1 is transported, the adhesive force of the adhesive tape is reduced by UV irradiation or the like, and a push-up needle ( By pushing up the power semiconductor element 1 from the tape side with the metal needle), the power semiconductor element 1 is peeled off from the tape side. Thereafter, the power semiconductor element 1 is a tool called a cylindrical collet having suction holes. It is easily adsorbed and held by.

更に、パワー半導体素子１と金属リードフレーム３の接合では、金属リードフレーム３が半田２の融点温度＋３０℃〜５０℃程度に加熱され、半田２が金属リードフレーム３上で加熱溶融される。この接合作業において、半田２や金属リードフレーム３の接触界面で酸化現象が生じると、半田２の金属リードフレーム３への濡れ性が著しく阻害され、パワー半導体素子１の接合強度が低下すると共に、半田２の内部のボイド発生やこれによるパワー半導体素子１への応力集中、電気伝導度や熱伝導度の低下及び接合信頼性が著しく低下し、半田２のクラックも発生する等、様々な不具合が生じるため、この作業環境を窒素ガス（Ｎ２）雰囲気中や（窒素＋水素）ガスの還元性雰囲気中とすることにより、酸素の影響を排除することが重要となっている。 Further, in joining the power semiconductor element 1 and the metal lead frame 3, the metal lead frame 3 is heated to the melting point temperature of the solder 2 + 30 ° C. to about 50 ° C., and the solder 2 is heated and melted on the metal lead frame 3. In this joining operation, when an oxidation phenomenon occurs at the contact interface between the solder 2 and the metal lead frame 3, the wettability of the solder 2 to the metal lead frame 3 is significantly hindered, and the joining strength of the power semiconductor element 1 is reduced. There are various problems such as generation of voids in the solder 2, stress concentration on the power semiconductor element 1 due to this, reduction in electrical conductivity and thermal conductivity, joint reliability is remarkably reduced, and cracks in the solder 2 are also generated. Therefore, it is important to eliminate the influence of oxygen by setting the working environment in a nitrogen gas (N 2 ) atmosphere or a reducing atmosphere of (nitrogen + hydrogen) gas.

特開２００６−６６８１３号公報JP 2006-66813 A 特開平１０−１８９８５１号公報Japanese Patent Laid-Open No. 10-189851 特開２００７−３１１６５３号公報JP 2007-311653 A

ところで、一般に、オーディオ用のスピーカーケーブルは銅線が使用され、その中でも無酸素銅（ＯＦＣ）が良いとされ、パワー半導体装置用の高音質向けに開発された金属リードフレーム（３）においても、特許文献２のように無酸素銅を使用することが提案され、実際にも、図１１に示す構造のダイオードを作製し、オーディオアンプの電源回路に用いた結果、優れた音質向上効果があることが感性的に得られている。   By the way, in general, copper wires are used for speaker cables for audio, and among them, oxygen-free copper (OFC) is good, and in metal lead frames (3) developed for high sound quality for power semiconductor devices, It has been proposed to use oxygen-free copper as in Patent Document 2, and in fact, as a result of producing a diode having the structure shown in FIG. 11 and using it in a power circuit of an audio amplifier, there is an excellent sound quality improvement effect. Is obtained sensibly.

しかしながら、従来では、図１１のようにパワー半導体素子１とリードフレーム３を接続する接合材として半田が用いられており、オーディオ用のパワー半導体装置では音質の更なる向上が図れず、その他の用途を含めた全体のパワー半導体装置においても、無酸素銅の軟化により組立工程の自動化が妨げられたり、ボイドの発生、部材酸化、接合部厚みの不均一等により接合強度のバラツキが発生したりする等の問題があった。   However, conventionally, solder is used as a bonding material for connecting the power semiconductor element 1 and the lead frame 3 as shown in FIG. 11, and the power semiconductor device for audio cannot be further improved in sound quality. Even in the entire power semiconductor device including the above, the automation of the assembly process is hindered by the softening of oxygen-free copper, and the bonding strength varies due to the generation of voids, member oxidation, unevenness in the thickness of the joint, etc. There was a problem such as.

即ち、銅線の比抵抗値は１７．２ｎΩ・ｍ（２０℃、以下同様）と低く、銀の１６．３ｎΩ・ｍに次ぐ低さであり、金線の比抵抗値も２４．０ｎΩ・ｍと低いのに対し、半田接合材は、錫鉛系のＳｎＰｂ共晶半田で比抵抗値が約１００ｎΩ・ｍとなり、金、銀、銅等と比較すると、４〜５倍程高い数値になる。   That is, the specific resistance value of the copper wire is as low as 17.2 nΩ · m (20 ° C., the same applies hereinafter), the second lowest after 16.3 nΩ · m of silver, and the specific resistance value of the gold wire is also 24.0 nΩ · m. On the other hand, the solder bonding material is a tin-lead SnPb eutectic solder and has a specific resistance value of about 100 nΩ · m, which is about 4 to 5 times higher than that of gold, silver, copper or the like.

また、熱伝導率で比較しても、図１１のように、無酸素銅とした金属リードフレーム３にパワー半導体素子１を実装する際に、半田２を使用した場合、錫鉛系のＳｎＰｂ共晶半田の場合、５０Ｗ／（ｍ・Ｋ）程度であるが、金では熱伝導率が２９５Ｗ／（ｍ・Ｋ）となり、格段の差がある。このように、半田２は比抵抗値が高く、熱伝導率も小さいことから、オーディオ用において音質の向上を図るための接合素材としては好ましくない。   Further, even when compared with thermal conductivity, when solder 2 is used when mounting the power semiconductor element 1 on the metal lead frame 3 made of oxygen-free copper, as shown in FIG. In the case of crystal solder, it is about 50 W / (m · K), but in gold, the thermal conductivity is 295 W / (m · K), and there is a marked difference. Thus, since the solder 2 has a high specific resistance value and a low thermal conductivity, it is not preferable as a bonding material for improving sound quality for audio.

更に、パワー半導体素子１と金属リードフレーム３の接合に半田２を用いる場合、半田２を融点以上（融点温度＋３０℃〜５０℃）に加熱することや、雰囲気ガスによる酸素の遮蔽性や構成材料の保管性等の様々な問題により、半田２の金属リードフレーム３やパワー半導体素子１に対する必要な濡れ性が確保されず、ボイドの発生が生じ、このボイドの局在化や過大な発生がパワー半導体素子１に与える応力ばらつきにより、接合強度等の特性に重大な影響を与え、熱伝導性のばらつきの要因ともなるという問題があった。また、各部材の酸化等の影響により、接合強度自体にばらつきが生じることもあり、これによっても、電気抵抗や半導体素子からの熱拡散のばらつきが生じる。   Further, when the solder 2 is used for joining the power semiconductor element 1 and the metal lead frame 3, the solder 2 is heated to a melting point or higher (melting point temperature + 30 ° C. to 50 ° C.), oxygen shielding property or constituent material by atmospheric gas Due to various problems such as storability, the necessary wettability of the solder 2 to the metal lead frame 3 and the power semiconductor element 1 is not ensured, and voids are generated. This void is localized and excessively generated. The stress variation applied to the semiconductor element 1 has a problem of seriously affecting the characteristics such as the bonding strength and causing a variation in thermal conductivity. In addition, the bonding strength itself may vary due to the influence of oxidation or the like of each member, which also causes variations in electrical resistance and thermal diffusion from the semiconductor element.

一般に、パワー半導体素子１及び金属リードフレーム３の線膨張係数の違いから、金属リードフレーム３からの応力を緩和するため、半田層の厚みは１０μｍ以上確保されることが一般的であるが、半田２が溶融された状態でこの厚みを一定（均一）に制御することは極めて困難である。更に、鉛が含まれる半田２は、環境影響の配慮から禁止されるリスクがあり、様々な代替半田が検討されているものの、鉛を排除した場合は半田材に要求される特性の悪化が懸念される。   Generally, in order to relieve stress from the metal lead frame 3 due to the difference in linear expansion coefficient between the power semiconductor element 1 and the metal lead frame 3, the thickness of the solder layer is generally secured to 10 μm or more. It is extremely difficult to control the thickness to be constant (uniform) while 2 is melted. Furthermore, there is a risk that solder 2 containing lead has a risk of being banned from environmental considerations, and various alternative solders have been studied. However, if lead is excluded, there is a concern that the characteristics required of the solder material may deteriorate. Is done.

上記の半田材の不都合は、図１１のようにパワー半導体素子１の電極面を金属線５で結合するものではなく、特許文献１の挟み込み構造ように、パワー半導体素子１の表裏電極と金属部材との接合に半田を用いる場合にも同様に生じる。   The inconvenience of the above solder material is not that the electrode surfaces of the power semiconductor element 1 are coupled by the metal wire 5 as shown in FIG. 11, but the front and back electrodes and the metal member of the power semiconductor element 1 as in the sandwich structure of Patent Document 1. This also occurs when solder is used for bonding with the solder.

更に、図１１に示すパワー半導体素子１の表面電極と内部リード部４を接続する金属線５として、アルミニウム（Ａｌ）線を用いた場合、その比抵抗値が２８．２ｎΩ・ｍ（２０℃）と比較的小さな値ではあるが、銅線と比較すると１．５倍以上高い数値となる。この結果、アルミニウム線で抵抗値を下げるためには、銅線よりも線径の引き上げが必要となる。近年、パワー半導体素子１として低オン抵抗として有利な炭化珪素（ＳｉＣ）を基板とした高価な素子が提案されているが、アルミニウム線の線径に通常市販される０．５ｍｍΦを使用する場合、その接合部位は線径の３倍程度が必要となるため、パワー半導体素子１は１辺が２ｍｍ以上となる大きなサイズが必要となる。   Further, when an aluminum (Al) wire is used as the metal wire 5 connecting the surface electrode of the power semiconductor element 1 and the internal lead portion 4 shown in FIG. 11, the specific resistance value is 28.2 nΩ · m (20 ° C.). Although it is a relatively small value, it is 1.5 times higher than the copper wire. As a result, in order to lower the resistance value with the aluminum wire, it is necessary to increase the wire diameter as compared with the copper wire. In recent years, an expensive element based on silicon carbide (SiC), which is advantageous as a low on-resistance as the power semiconductor element 1, has been proposed, but when using a commercially available 0.5 mmΦ for the wire diameter of the aluminum wire, Since the joint portion needs to be about three times the wire diameter, the power semiconductor element 1 needs a large size with one side being 2 mm or more.

また、アルミニウムの線膨張係数は２３．５ｐｐｍであり、銅は１７．０ｐｐｍと小さく、炭化珪素（ＳｉＣ）は４．１ｐｐｍ程度で、シリコンについても２．８ｐｐｍ程度と小さく、アルミニウムとの差が銅と比較して大きい。このことは、−６５℃〜１５０℃の温度サイクル試験を実施した場合、アルミニウム線を使用したパワー半導体装置は、パワー半導体素子１の結合部からクラックが成長するため銅線と比較して寿命が短いという問題もある。   Also, the linear expansion coefficient of aluminum is 23.5 ppm, copper is as small as 17.0 ppm, silicon carbide (SiC) is about 4.1 ppm, and silicon is also as small as about 2.8 ppm, and the difference from aluminum is copper. Big compared to. This means that when a temperature cycle test at −65 ° C. to 150 ° C. is performed, the power semiconductor device using the aluminum wire has a life longer than that of the copper wire because cracks grow from the joint portion of the power semiconductor element 1. There is also the problem of being short.

更に、金属リードフレーム３に無酸素銅を使用する場合、この無酸素銅の軟化温度が通常２００℃程度であり、パワー半導体素子１と金属リードフレーム３の実装に半田２を使用すると、半田２の融点にプラス３０℃〜５０℃の作業温度が必要であることから、作業温度は２５０〜３００℃程度の高温となり、無酸素銅が軟化してしまう。従って、その後のプロセスの作業が困難となり、組立工程の自動化が妨げられるという問題がある。   Further, when oxygen-free copper is used for the metal lead frame 3, the softening temperature of the oxygen-free copper is usually about 200 ° C. When the solder 2 is used for mounting the power semiconductor element 1 and the metal lead frame 3, the solder 2 Since a working temperature of 30 ° C. to 50 ° C. is necessary for the melting point of the steel, the working temperature becomes a high temperature of about 250 to 300 ° C., and the oxygen-free copper is softened. Therefore, there is a problem that the subsequent process work becomes difficult and automation of the assembly process is hindered.

本発明は上記問題点に鑑みてなされたものであり、その目的は、接合材として半田を使用することなく、音響機器用では音質の向上を図り、その他の用途を含めたパワー半導体装置においては、ボイド発生、部材酸化又は接合部の厚みの不均一等による接合強度のバラツキの発生等をなくすことができ、また無酸素銅の軟化による組立工程の自動化が妨げられることのないパワー半導体装置及びその製造方法を提供することにある。   The present invention has been made in view of the above problems, and its purpose is to improve the sound quality for acoustic equipment without using solder as a bonding material, and in a power semiconductor device including other uses. A power semiconductor device capable of eliminating the occurrence of voids, member oxidation or unevenness in joining strength due to uneven thickness of the joint, and the like, and preventing the automation of the assembly process due to softening of oxygen-free copper, and It is in providing the manufacturing method.

上記目的を達成するために、請求項１に係る発明は、表裏面に電極が形成されたパワー半導体素子と、このパワー半導体素子を接合し、かつ放熱板としても機能する金属リードフレームとを設け、この金属リードフレームの一部を放熱のために露出させながら全体を樹脂封止してなるパワー半導体装置において、上記金属リードフレームに高純度（９９．９９％）の無酸素銅を用い、上記パワー半導体素子の基板に炭化珪素を用い、かつ該パワー半導体素子の表面電極としてチタン膜の上にアルミニウム膜を形成し、このパワー半導体素子の表面電極を上記金属リードフレームの内部リードに銅線にて接合する構成とし、上記パワー半導体素子の裏面電極として形成された金膜又は銀膜の上に、高純度（９９．９９％）の金又は銅からなる金属バンプを介して、上記金属リードフレームを接合してなることを特徴とする。 To achieve the above object, the invention according to claim 1 is provided with a power semiconductor element having electrodes formed on the front and back surfaces, and a metal lead frame that joins the power semiconductor element and also functions as a heat sink. In a power semiconductor device in which a part of the metal lead frame is exposed for heat dissipation and the whole is resin-sealed , high purity (99.99%) oxygen-free copper is used for the metal lead frame, Silicon carbide is used for the substrate of the power semiconductor element, and an aluminum film is formed on the titanium film as the surface electrode of the power semiconductor element. The surface electrode of the power semiconductor element is connected to the internal lead of the metal lead frame with a copper wire. And made of gold or copper of high purity (99.99%) on the gold film or silver film formed as the back electrode of the power semiconductor element. Via the bumps, characterized in that formed by joining the metal lead frame.

請求項２に係る発明は、表裏面に電極が形成されたパワー半導体素子を設け、このパワー半導体素子を金属リードフレームに接合するパワー半導体装置の製造方法において、上記パワー半導体素子の表面電極としてチタン膜の上にアルミニウム膜を形成し、このパワー半導体素子の表面電極を上記金属リードフレームの内部リードに銅線にて接合し、上記パワー半導体素子の表面電極又は裏面金属膜、又は上記金属リードフレームに、半田材でない金属バンプを形成し、上記パワー半導体素子の金属バンプを形成しない面の外周に、弾性体からなる凸部を設けると共に、上記金属リードフレームの金属バンプの形成又は圧接位置（半導体素子にバンプ形成する場合とリードフレームに形成する場合の両方）に予め窪みを設け、上記パワー半導体素子を金属バンプが配置されない面から加圧しながら、超音波振動を与えることにより、上記パワー半導体素子と上記金属リードフレームとを接合することを特徴とする。
請求項３の発明は、複数のパワー半導体素子が形成された集合基板の各パワー半導体素子に金属バンプを形成した後、この集合基板を切削することで、個々のパワー半導体素子を製作するとき、個々のパワー半導体素子の金属バンプ形成面の外周に、各パワー半導体素子間の境界を識別する隙間を残した状態で、弾性体からなる凸部を設けたことを特徴とする。 Invention, a power semiconductor element electrodes on the front and back surface is formed provided a method of manufacturing a power semiconductor device for joining the power semiconductor element on a metal lead frame, titanium as the surface electrodes of the power semiconductor device according to claim 2 An aluminum film is formed on the film, and the surface electrode of the power semiconductor element is joined to the internal lead of the metal lead frame with a copper wire , and the surface electrode or back metal film of the power semiconductor element, or the metal lead frame And forming bumps made of an elastic body on the outer periphery of the surface of the power semiconductor element where the metal bumps are not formed, and forming or pressing the metal bumps of the metal lead frame (semiconductors). previously recess both) in the case of forming the case and the lead frame forming bumps provided on the element, the power semiconductor While pressing the element from the surface metal bumps is not arranged, by applying ultrasonic vibrations, characterized by joining the said power semiconductor device and the metal lead frame.
Invention 請 Motomeko 3, after forming the metal bump on the power semiconductor element of the set substrate on which a plurality of power semiconductor elements are formed, by cutting the collective substrate, when fabricating the individual power semiconductor device A convex portion made of an elastic body is provided on the outer periphery of the metal bump forming surface of each power semiconductor element, leaving a gap for identifying the boundary between the power semiconductor elements .

請求項４の発明は、上記パワー半導体素子の上記金属バンプが配置されない面で、搬送時（剥離時）に金属針により突き上げられる部分に、弾性体を設けたことを特徴とする。 According to a fourth aspect of the present invention, an elastic body is provided on a portion of the power semiconductor element on which the metal bumps are not disposed and which is pushed up by a metal needle during transportation (peeling) .

請求項１，２のパワー半導体装置及びその製造方法によれば、パワー半導体素子の金属リードフレームへの接合材として、半田接合材を使用せず、電気的に有利な（比抵抗値が低く、熱伝導率の小さい）金、銀、銅等を使用するため、高放熱特性を有するパワー半導体装置等において応力的影響が小さくなり、接合部のクラック等をなくすことができる。即ち、線膨張係数で考えると、主に錫鉛系からなる半田の場合は２１〜２４（×１０−6／℃）程度であるのに対し、金属バンプは、銅：１７．０、金：１４．１、銀：１８．９、アルミニウム：２３、パラジウム：１１．８、チタン：８．６（×１０−6／℃）、パワー半導体素子の基板に使用される炭化珪素（ＳｉＣ）は４．１（×１０−6／℃）であるので、半田をパワー半導体素子の接合材として使用するよりも、上記の金属バンプで接合する方が応力的影響は小さくなる。そして、音響機器においては、感性的な音質の向上を図ることができ、金属バンプのレイアウト自由度も高いため、感性的に高い音質評価が得られるという利点がある。 According to the power semiconductor device and the method for manufacturing the power semiconductor device according to claim 1 , the soldering material is not used as a bonding material to the metal lead frame of the power semiconductor element, which is electrically advantageous (low specific resistance value, Since gold, silver, copper, or the like (having a low thermal conductivity) is used, the stress effect is reduced in a power semiconductor device having high heat dissipation characteristics, and cracks in the joint can be eliminated. That is, in terms of linear expansion coefficient, in the case of solder mainly made of tin-lead, it is about 21 to 24 (× 10 −6 / ° C.), whereas metal bumps are copper: 17.0, gold: 14.1, Silver: 18.9, Aluminum: 23, Palladium: 11.8, Titanium: 8.6 (× 10 −6 / ° C.), 4 silicon carbide (SiC) used for the substrate of the power semiconductor element .1 (× 10 −6 / ° C.) Therefore, the stress effect is smaller when the solder is used for joining the metal bumps than when the solder is used as a joining material for the power semiconductor element. And in an audio equipment, since it is possible to improve the sensuous sound quality and the layout flexibility of the metal bumps is high, there is an advantage that a high sound quality evaluation can be obtained sensibly.

また、半田を使用しないから、環境によく、半田濡れ性の影響による内部ボイドの発生もなく、接合強度や熱伝導性のばらつき等、ひいては電気抵抗や半導体素子からの熱拡散のばらつきを解消することができる。しかも、金属バンプの接続では、その本数、接合位置を任意に設定することで、上記ばらつき要因を良好に解消することが可能である。
更に、半田のような高温の接合プロセスを必要とせず、超音波振動を用いれば、室温から無酸素銅の軟化温度である２００℃以下の温度範囲でも接合が可能となる。 Also, since no solder is used, it is good for the environment, there are no internal voids due to the influence of solder wettability, and it eliminates variations in bonding strength, thermal conductivity, etc., as well as variations in electrical resistance and thermal diffusion from semiconductor elements. be able to. In addition, in the connection of the metal bumps, it is possible to satisfactorily eliminate the above-mentioned variation factor by arbitrarily setting the number and the joining position.
Furthermore, if ultrasonic vibration is used without requiring a high-temperature bonding process such as solder, bonding can be performed even in a temperature range from room temperature to 200 ° C., which is the softening temperature of oxygen-free copper.

また、上記金属バンプの接合、そして超音波振動の接合によれば、金属バンプの潰し込み量が比較的制御し易く、バンプ接合部の厚み（Ｚ方向）を任意かつ一定に設定することができ、接合部の応力の影響（クラック等）がなくなる。即ち、半田の厚みが厚い場合は、金属リードフレームと半導体素子の線膨張係数差で生じる応力を緩和する効果が期待されているが、半田接合法では、半田が溶けた状態で半導体素子を接合するため半田の厚みを一定に制御することが難しく、ばらつきが生じる。これに対し、本発明は、バンプ接合部を任意かつ一定の厚みにでき、接続される各部材の線膨張係数差で生じる応力を緩和することが可能となる。   Further, according to the bonding of the metal bump and the bonding of ultrasonic vibration, the crushing amount of the metal bump can be controlled relatively easily, and the thickness (Z direction) of the bump bonding portion can be set arbitrarily and constant. The effect of stress at the joint (cracks, etc.) is eliminated. In other words, when the thickness of the solder is thick, the effect of alleviating the stress caused by the difference in coefficient of linear expansion between the metal lead frame and the semiconductor element is expected. For this reason, it is difficult to control the thickness of the solder to be constant, resulting in variations. On the other hand, according to the present invention, the bump bonding portion can have an arbitrary and constant thickness, and the stress generated by the difference in linear expansion coefficient between the connected members can be reduced.

更に、金属バンプの周辺部はモールド樹脂の成型圧によって樹脂が注入され、パワー半導体素子は全体的に同一樹脂で封止されるため、局所的な応力の発生が生じない。即ち、一般的な半田は、モールド樹脂（エポキシ樹脂等）と接着することができないため、半田が濡れ広がった界面では樹脂が密着しておらず、これによる剥離が生じ、この剥離部分に水分が浸入することで、腐食や水蒸気爆発等、重大な信頼性不具合が生じていたが、本発明では、モールド樹脂が直接金属リードフレームへ接着することになり、上記のような不具合はなくなる。   Further, since the resin is injected into the peripheral portion of the metal bump by the molding resin molding pressure and the power semiconductor element is entirely sealed with the same resin, no local stress is generated. That is, since general solder cannot be bonded to a mold resin (epoxy resin, etc.), the resin does not adhere to the interface where the solder has spread, and peeling occurs due to this, and moisture is present at the peeled portion. Intrusion caused serious reliability problems such as corrosion and water vapor explosion, but in the present invention, the mold resin is directly bonded to the metal lead frame, and the above problems are eliminated.

また、パワー半導体素子の電極と金属線の接合において電極側のチタンと金属線である銅線が強固に接合されるから、接合信頼性が向上すると共に、十分な寿命が得られるという利点がある。 In addition , since the electrode side titanium and the copper wire, which is the metal wire, are firmly joined in the joining of the electrode and the metal wire of the power semiconductor element, there is an advantage that the joining reliability is improved and a sufficient life is obtained. .

また、パワー半導体素子基板に用いられる炭化珪素は、オン抵抗が低いため、省電力化、小型化が促進できるという利点がある。
更に、上記パワー半導体素子の裏面電極に金又は銀を蒸着すると共に、金属バンプに高純度の金又は銅を用い、金属リードフレームを高純度の無酸素銅とすることにより、音響機器において更に高い音質特性を得ることができる。 In addition , silicon carbide used for the power semiconductor element substrate has an advantage that power saving and miniaturization can be promoted because of low on-resistance.
Furthermore, gold or silver is vapor-deposited on the back electrode of the power semiconductor element, high-purity gold or copper is used for the metal bump, and the metal lead frame is made of high-purity oxygen-free copper. Sound quality characteristics can be obtained.

上記製造方法によれば、パワー半導体素子の例えば裏面を上にして金属バンプを形成する工程では、回路面接触回避用の弾性体凸部により、電極が形成された例えば表面と集合基板台（ウェハー台）とが直接接触することが防止され、また金属バンプによる接合を行う工程では、上記パワー半導体素子の表面とボンディングツールとが直接接触することが防止され、パワー半導体素子自体又はその電極へのダメージが回避される。また、ボンディングツールの長寿命化にも繋がる。
また、金属リードフレーム上に設けた窪みにより、金属バンプ接合においてアンカー効果が発揮され、接合性の安定化が図れるという利点がある。 According to the above manufacturing method, in the step of forming the metal bump with the power semiconductor element, for example, the back surface facing up, for example, the surface and the collective substrate stand (wafer) on which the electrodes are formed by the elastic convex portions for circuit surface contact avoidance In the process of bonding with metal bumps, the surface of the power semiconductor element and the bonding tool are prevented from coming into direct contact with each other, and the power semiconductor element itself or its electrode Damage is avoided. It also leads to longer life of the bonding tool.
Further, the depression provided on the metal lead frame has an advantage that the anchor effect is exhibited in the metal bump bonding, and the bonding property can be stabilized.

上記請求項３の発明によれば、パワー半導体素子間の弾性体凸部の境界が切削ラインとなり、他の識別手段を施すことなく、ダイシングが可能となり、また弾性体凸部が金属バンプを形成するときのアライメント（位置決め）マークとなり、正確な位置への金属バンプの形成が可能となる。 According to the third aspect of the present invention, the boundary of the elastic convex portion between the power semiconductor elements becomes a cutting line, and dicing can be performed without applying other identification means, and the elastic convex portion forms a metal bump. Alignment (positioning) marks are used, and metal bumps can be formed at accurate positions.

上記請求項４の構成によれば、個片化されたパワー半導体素子が突上げ針によりダイシングテープから剥離される際に、パワー半導体素子の突上げ面が弾性体（膜等）により保護され、パワー半導体素子自体又はその電極へダメージが与えられることがない。 According to the configuration of claim 4, when the separated power semiconductor element is peeled from the dicing tape by the thrust needle, the thrust surface of the power semiconductor element is protected by the elastic body (film or the like), The power semiconductor element itself or its electrode is not damaged .

本発明の第１実施例に係るパワー半導体装置（ダイオード）の構成を示し、図（Ａ）は樹脂を透視した状態の側面図、図（Ｂ）は樹脂を透視した状態の平面図である。BRIEF DESCRIPTION OF THE DRAWINGS The structure of the power semiconductor device (diode) based on 1st Example of this invention is shown, FIG. (A) is a side view of the state which permeate | transmitted resin, FIG. (B) is a top view of the state which permeate | transmitted resin. 第１実施例のパワー半導体素子の構成を示す断面図である。It is sectional drawing which shows the structure of the power semiconductor element of 1st Example. 実施例のパワー半導体素子における金属バンプの配置例を示す図である。It is a figure which shows the example of arrangement | positioning of the metal bump in the power semiconductor element of an Example. 本発明の第２実施例のパワー半導体装置の製造方法で製作されるパワー半導体素子の構成を示し、図（Ａ）は表面側の図、図（Ｂ）は裏面側の図である。The structure of the power semiconductor element manufactured with the manufacturing method of the power semiconductor device of 2nd Example of this invention is shown, A figure (A) is a figure on the surface side, and a figure (B) is a figure on the back side. 第２実施例において金属バンプを形成する工程の一例を示す図である。It is a figure which shows an example of the process of forming a metal bump in 2nd Example. 第２実施例において金属バンプを形成する工程の他の例を示す図である。It is a figure which shows the other example of the process of forming a metal bump in 2nd Example. 第２実施例においてウェハー上のパワー半導体素子の集合基板のダイシング工程を示す図である。It is a figure which shows the dicing process of the collective board | substrate of the power semiconductor element on a wafer in 2nd Example. 第２実施例においてダイシングテープからのパワー半導体素子の取出し（ピックアップ）を示す図である。It is a figure which shows taking out (pickup) of the power semiconductor element from a dicing tape in 2nd Example. 第２実施例でのパワー半導体素子と金属リードフレームの接合工程の一例を示す図である。It is a figure which shows an example of the joining process of the power semiconductor element and metal lead frame in 2nd Example. 第２実施例でのパワー半導体素子と金属リードフレームの接合工程の他の例を示す図である。It is a figure which shows the other example of the joining process of the power semiconductor element and metal lead frame in 2nd Example. 従来のパワー半導体装置（ダイオード）の構成を示し、図（Ａ）は樹脂を透視した状態の側面図、図（Ｂ）は樹脂を透視した状態の平面図である。The structure of the conventional power semiconductor device (diode) is shown, FIG. (A) is a side view of the state which saw through resin, and FIG. (B) is a top view of the state which saw through resin.

図１には、本発明の第１実施例に係るパワー半導体装置（ダイオード）の構成が示されている。この第１実施例は、図１１と同様に、パワー半導体素子１０の裏面電極（カソード）１２を比較的大きな面積の金属リードフレーム１３に接続する構成であり、この裏面電極１２と金属リードフレーム１３の接合に金属バンプ（スタッドバンプ）１４を用いる。また、金属リードフレーム１３の内部リード部１５とパワー半導体素子１０の表面電極（アノード）１１を金属線１６により接続し、全体を樹脂６にて封止する構成となり、上記金属リードフレーム１３には外部電極１７ａ、内部リード部１５には外部電極１７ｂが接続される。更に、金属リードフレーム１３の端部には、金属リードフレーム１３と樹脂６を共に貫通する取付け用の孔８が形成されている。実施例では、上記金属リードフレーム１３に例えば純度９９．９９％の無酸素銅を用い、上記金属線１６に銅線又はアルミニウム線を使用している。   FIG. 1 shows the configuration of a power semiconductor device (diode) according to the first embodiment of the present invention. In the first embodiment, the back electrode (cathode) 12 of the power semiconductor element 10 is connected to a metal lead frame 13 having a relatively large area, as in FIG. 11, and the back electrode 12 and the metal lead frame 13 are connected. Metal bumps (stud bumps) 14 are used for bonding. Further, the internal lead portion 15 of the metal lead frame 13 and the surface electrode (anode) 11 of the power semiconductor element 10 are connected by the metal wire 16 and the whole is sealed with the resin 6. An external electrode 17 b is connected to the external electrode 17 a and the internal lead portion 15. Further, an attachment hole 8 that penetrates both the metal lead frame 13 and the resin 6 is formed at the end of the metal lead frame 13. In the embodiment, for example, oxygen free copper having a purity of 99.99% is used for the metal lead frame 13, and a copper wire or an aluminum wire is used for the metal wire 16.

図２には、パワー半導体素子１０の断面構造が示されており、このパワー半導体素子１０の基板（基材）１９は、炭化珪素（ＳｉＣ）からなり（シリコン等でもよい）、その裏面電極（カソード面）１２には基板側から順にチタン（Ｔｉ）膜１２ａ、ニッケル（Ｎｉ）膜１２ｂ、金（Ａｕ）膜又は銀（Ａｇ）膜１２ｃが蒸着・形成され、表面電極（アノード面）１１には、基板側から順にチタン（Ｔｉ）膜１１ａ、アルミニウム（Ａｌ）膜１１ｂが蒸着・形成され、この表面電極１１の周囲には、ポリイミド等からなる弾性体凸部（保護膜）２０が形成される。また、実施例では、裏面電極１２側の金属バンプ１４の材料として、金（例えば純度９９．９９％）、銀、銅（例えば純度９９．９９％）、アルミニウム、パラジウム（Ｐｄ）又はチタンのいずれか又はこれらを組み合わせた材料、或いはＧａＮ（窒化ガリウム）、Ｇａ２Ｏ３（酸化ガリウム）等が用いられ、この金属バンプ１４によるスタッドバンプ工法による接合が行われる。これらの中では、特に、金、銀、銅が好適である。 FIG. 2 shows a cross-sectional structure of the power semiconductor element 10, and a substrate (base material) 19 of the power semiconductor element 10 is made of silicon carbide (SiC) (or silicon or the like), and its back electrode ( A titanium (Ti) film 12a, a nickel (Ni) film 12b, a gold (Au) film, or a silver (Ag) film 12c are deposited and formed on the surface electrode (anode surface) 11 in this order from the substrate side. In this case, a titanium (Ti) film 11a and an aluminum (Al) film 11b are deposited and formed in order from the substrate side, and an elastic protrusion (protective film) 20 made of polyimide or the like is formed around the surface electrode 11. The In the embodiment, the material of the metal bump 14 on the back electrode 12 side is any of gold (for example, purity 99.99%), silver, copper (for example, purity 99.99%), aluminum, palladium (Pd), or titanium. Alternatively, or a combination of these materials, GaN (gallium nitride), Ga 2 O 3 (gallium oxide), or the like is used, and the metal bumps 14 are joined by the stud bump method. Among these, gold, silver, and copper are particularly preferable.

図３（Ａ）〜（Ｄ）には、上記金属バンプ１４の配置例が示されており、図示のように、パワー半導体素子１０の裏面電極側に形成可能な金属バンプ１４は、自由度の高いレイアウトで配置することができる。即ち、この金属バンプ１４の数は、後述の熱伝導性や溶断電流等の試算により算出でき、半田接合では一般に上記裏面電極１２にボイドが発生することが多く、電流密度の偏りが音質に影響する懸念が指摘されているが、金属バンプ１４のレイアウトによって音質に関する大きな影響が感性的に認められており、金属バンプ１４の接合であれば自由度の高いレイアウトで音質を改善できる。   FIGS. 3A to 3D show examples of the arrangement of the metal bumps 14. As shown in the drawing, the metal bumps 14 that can be formed on the back electrode side of the power semiconductor element 10 are flexible. It can be arranged with a high layout. That is, the number of the metal bumps 14 can be calculated by trial calculation such as thermal conductivity and fusing current, which will be described later. Generally, in the solder joint, voids are often generated in the back electrode 12, and the current density deviation affects the sound quality. However, if the metal bumps 14 are joined, the sound quality can be improved with a highly flexible layout.

また、パワー半導体素子１０が実装される金属リードフレーム１３に無酸素銅材を適用し、この金属リードフレーム上に銀又はパラジウムめっきを施し、超音波接合を適用することで、金属リードフレーム１３への低温実装が可能になる。また、条件により上記金属リードフレーム１３はめっきなし或いは銅めっきとした場合、金属バンプ１４と金属リードフレーム１３との接合では、合金層が形成されることはない。   Further, an oxygen-free copper material is applied to the metal lead frame 13 on which the power semiconductor element 10 is mounted, silver or palladium plating is performed on the metal lead frame, and ultrasonic bonding is applied to the metal lead frame 13. Low temperature mounting becomes possible. In addition, when the metal lead frame 13 is not plated or is copper plated depending on conditions, an alloy layer is not formed when the metal bump 14 and the metal lead frame 13 are joined.

上記パワー半導体素子１０を上記金属リードフレーム１３に実装した後は、パワー半導体素子１０の表面電極１１と金属リードフレーム１３の内部電極（と同一材料で形成される）が金属線１６で接続され、この後、金型成型法によるエポキシ樹脂等の封止材を金型内へ圧力を加えながら成型することで、パワー半導体装置の成型ができ、このときの金型温度や樹脂硬化温度は１５０〜１８０℃で可能であるから、無酸素銅の軟化温度を超えることはない。   After the power semiconductor element 10 is mounted on the metal lead frame 13, the surface electrode 11 of the power semiconductor element 10 and the internal electrode (formed of the same material) of the metal lead frame 13 are connected by the metal wire 16, Thereafter, a power semiconductor device can be molded by molding a sealing material such as an epoxy resin by a mold molding method while applying pressure into the mold, and the mold temperature and the resin curing temperature at this time are 150 to Since it is possible at 180 ° C., the softening temperature of oxygen-free copper is not exceeded.

このような第１実施例の構成では、パワー半導体素子１０と金属リードフレーム１３の接合材に半田を使用せず、金又は銅等からなる金属バンプ１４を用いていることから、パワー半導体素子１０から金属リードフレーム１３への熱伝導率が向上することになる。この熱伝導性の向上を図るためには、金属バンプ１４の数をどの程度に設定するかが重要であり、次の熱抵抗簡易計算式で求めることができる。   In such a configuration of the first embodiment, the solder is not used for the bonding material between the power semiconductor element 10 and the metal lead frame 13, and the metal bumps 14 made of gold, copper, or the like are used. Therefore, the thermal conductivity from the metal to the metal lead frame 13 is improved. In order to improve the thermal conductivity, it is important how many metal bumps 14 are set, and can be obtained by the following simple calculation formula for thermal resistance.

［熱抵抗簡易計算式］
Ｒ＝ｂ／（λ・ａ）［℃／Ｗ］ … （１）
但し、Ｒ：熱抵抗値、ａ：断面積［ｍ２］、ｂ：厚み［ｍｍ］、λ：熱伝導度［Ｗ／（ｍ・℃）］である。
例えば、金のλＡｕは２９５［Ｗ／ｍ・℃］で、パワー半導体素子１０と金属リードフレーム１３に使用される半田は、一般に鉛含有率が高い高温半田が使用されるため、λＰｂＳｎを３５［Ｗ／ｍ・℃］とすると、厚みが同じであれば、断面積は半田の約１／８で同等となるから、その倍以上の断面積となる金バンプを確保すればよいことになる。また、銅の熱伝導率は３９１［Ｗ／ｍ・℃］であるから、熱伝導率では、銅は金より更に有利な設計とすることができる。 [Thermal calculation formula]
R = b / (λ · a) [° C./W] (1)
Where R: thermal resistance value, a: cross-sectional area [m 2 ], b: thickness [mm], λ: thermal conductivity [W / (m · ° C.)].
For example, λ Au of gold is 295 [W / m · ° C.], and the solder used for the power semiconductor element 10 and the metal lead frame 13 is generally a high-temperature solder having a high lead content, so that λ PbSn is If it is 35 [W / m · ° C.], if the thickness is the same, the cross-sectional area is equivalent to about 1/8 of the solder, so it is sufficient to secure a gold bump having a cross-sectional area more than twice that of the solder. Become. Moreover, since the thermal conductivity of copper is 391 [W / m · ° C.], copper can be designed to be more advantageous than gold in terms of thermal conductivity.

また、金属バンプの溶断電流値は、一般的に知られている次の（２），（３）式によって算出されるので、この溶断電流値から設計上必要となる金属バンプ数を算出することが可能である。
［溶断電流式／Ａｕ］
Ｉｆ＝ｄ０ ２×１０２×ＳＱＲＴ（２．９４１×Ｔｆ −１＋１．８８５×１０３×Ｌ０ −２）…（２）
［溶断電流式／Ｃｕ］
Ｉｆ＝ｄ０ ２×１０２×ＳＱＲＴ（６．８１６×Ｔｆ −１＋２．７７０×１０３×Ｌ０ −２）…（３）
但し、Ｉｆ：溶断電流［Ａ］、ｄ０：バンプ径［ｍｍ］、Ｔｆ：溶断時間［ｓｅｃ］、Ｌ０：バンプ高さ［ｍｍ］
例えば、上記式（２）において、バンプ径ｄ０＝０．１ｍｍ、バンプ高さＬ０＝０．０５ｍｍ、溶断時間Ｔｆ＝５秒とすると、溶断電流値は８６８Ａと算出されるため、相当な余裕があると見込まれる。また、半田の電気抵抗率が１１〜１５μΩ・ｃｍであるのに対し、金は２．３μΩ・ｃｍ、銅は１．６７μΩ・ｃｍであるから、接合部材として有利であり、また半田は融点が１８３℃〜２７０℃程度となるのに対し、金の融点が１０６３℃、銅の融点が１０８３℃であるから、金や銅は金属バンプとして圧倒的に有利であることが分かる。例えば、ベタ付けの半田に対して金バンプであれば、最低１２個、銅バンプであれば、最低９個設けさえすれば、接合部に流れる電流により発生するジュール熱に対して同等の耐性が得られる。 In addition, since the fusing current value of the metal bump is calculated by the following generally known formulas (2) and (3), the number of metal bumps required for design is calculated from the fusing current value. Is possible.
[Fusing current type / Au]
I f = d 0 2 × 10 2 × SQRT (2.941 × T f −1 + 1.85 × 10 3 × L 0 −2 ) (2)
[Fusing current type / Cu]
I f = d 0 2 × 10 2 × SQRT (6.816 × T f −1 + 2.770 × 10 3 × L 0 −2 ) (3)
However, I f: fusing current [A], d 0: bump diameter [mm], T f: fusing time [sec], L 0: bump height [mm]
For example, in the above formula (2), if the bump diameter d 0 = 0.1 mm, the bump height L 0 = 0.05 mm, and the fusing time T f = 5 seconds, the fusing current value is calculated as 868 A, It is expected that there is a margin. In addition, the electrical resistivity of solder is 11 to 15 μΩ · cm, whereas gold is 2.3 μΩ · cm and copper is 1.67 μΩ · cm, which is advantageous as a joining member, and solder has a melting point. While the melting point of gold is 1063 ° C. and the melting point of copper is 1083 ° C. while it is about 183 ° C. to 270 ° C., it can be seen that gold and copper are overwhelmingly advantageous as metal bumps. For example, at least 12 gold bumps for solid solder and at least 9 bumps for copper bumps will have equivalent resistance to Joule heat generated by the current flowing through the joint. can get.

第１実施例によれば、高放熱特性を有するパワー半導体装置において、応力的影響が小さくなり、接合部のクラック等をなくすことができ、金属バンプのレイアウト自由度も高いため、音響機器に使用される場合、感性的に高い音質が得られる。この音響機器用に使用する場合、上記金属リードフレーム１３を無酸素銅とし、パワー半導体素子１０の裏面１２との接合に、金又は銅の金属バンプ１４を使用することで、更なる音質向上を見込むことができる。また、環境によく、接合時の内部ボイドの発生もなく、接合強度や熱伝導性のばらつき、電気抵抗や熱拡散のばらつきを解消することができる。   According to the first embodiment, in a power semiconductor device having high heat dissipation characteristics, the stress effect is reduced, cracks in the joint portion can be eliminated, and the layout flexibility of the metal bumps is high. If this is done, a high sound quality can be obtained. When used for this acoustic device, the metal lead frame 13 is made of oxygen-free copper, and gold or copper metal bumps 14 are used for bonding to the back surface 12 of the power semiconductor element 10 to further improve sound quality. I can expect. Further, it is good for the environment, and there is no generation of internal voids at the time of bonding, and variations in bonding strength and thermal conductivity, variations in electrical resistance and thermal diffusion can be eliminated.

また、パワー半導体素子１０の表面電極１１を内部リード１５に接続する場合、金属線１６として、アルミニウム線又は銅線を用いるので、超音波振動により無酸素銅の軟化温度以下で作業することができる。特に、金属線１６に銅線を用いた場合は、超音波振動によって表面電極１１の上層のアルミニウムの掃き出し（スプラッシュ）が生じ、銅線の下からアルミニウム層１１ｂが消失するが、この層１１ｂの下のチタン層１１ａはアルミニウムより硬度が高く、スプラッシュが生じない。従って、チタン膜１１ａと銅線（金属線１６）が強固に接合され、これにより、接合信頼性が向上し、十分な寿命も得られるという利点がある。実際に、接合断面を確認すると、銅線はチタン層１１ａとの強固な密着層が形成され、−６５〜１５０℃の温度サイクルにおいても、３０００サイクル以上の信頼性があることが実証されている。   Further, when the surface electrode 11 of the power semiconductor element 10 is connected to the internal lead 15, since the aluminum wire or the copper wire is used as the metal wire 16, it can be operated below the softening temperature of oxygen-free copper by ultrasonic vibration. . In particular, when a copper wire is used as the metal wire 16, the aluminum layer 11b disappears from the bottom of the copper wire, and the aluminum layer 11b disappears from below the copper wire due to the ultrasonic vibration. The lower titanium layer 11a is harder than aluminum and does not cause splash. Therefore, the titanium film 11a and the copper wire (metal wire 16) are firmly bonded, thereby providing an advantage that the bonding reliability is improved and a sufficient life is obtained. Actually, when the bonding cross section is confirmed, it is proved that the copper wire forms a strong adhesion layer with the titanium layer 11a and has a reliability of 3000 cycles or more even in a temperature cycle of −65 to 150 ° C. .

更に、パワー半導体素子１０の炭化珪素からなる基板１９は、オン抵抗が低いため、省電力化、小型化の促進が可能となる。   Furthermore, since the substrate 19 made of silicon carbide of the power semiconductor element 10 has low on-resistance, it is possible to save power and promote downsizing.

図４には、第２実施例に係るパワー半導体装置の製造方法で得られるパワー半導体素子（ダイオード）の構成が示され、図（Ａ）は、パワー半導体素子２２の表面側、図（Ｂ）は裏面側の図である。このパワー半導体素子２２の表面（電極）２３には、１〜５μｍのアルミニウム膜が蒸着され、裏面（電極）２４には、第１実施例と同様に、基板側からチタン膜−ニッケル膜−金又は銀膜が形成されるが、チタン膜−アルミニウム膜を形成してもよい。第２実施例でも、この裏面２４側に高さ２５〜５０μｍ程度の金属バンプ２５が配置される。なお、上記表面２３において金属バンプによる接合を実施することも可能であり、この金属バンプとして金を用いる際は、ニッケル膜の下地を用い、金属バンプとして銅を用いる場合は、チタン膜を用いるとよい。   FIG. 4 shows the configuration of a power semiconductor element (diode) obtained by the method for manufacturing a power semiconductor device according to the second embodiment. FIG. 4 (A) shows the surface side of the power semiconductor element 22 and FIG. FIG. An aluminum film having a thickness of 1 to 5 μm is deposited on the surface (electrode) 23 of the power semiconductor element 22, and a titanium film-nickel film-gold is formed on the back surface (electrode) 24 from the substrate side as in the first embodiment. Alternatively, a silver film is formed, but a titanium film-aluminum film may be formed. Also in the second embodiment, metal bumps 25 having a height of about 25 to 50 μm are disposed on the back surface 24 side. It is also possible to carry out bonding with metal bumps on the surface 23. When gold is used as the metal bumps, a nickel film base is used, and when copper is used as the metal bumps, a titanium film is used. Good.

そして、上記パワー半導体素子２２の表面２３の外周部には、ポリイミド又はレジスト等からなる回路面接触回避用の弾性体凸部（膜）２７が厚み３〜５μｍ、幅０．０１〜０．１ｍｍで方形輪状に形成されると共に、その中央部には、突上げ針の保護用として、厚み３〜５μｍのポリイミド又はレジスト等からなる弾性体凸部（膜）２８が形成される。この弾性体凸部２８は、突き上げ針の先端径に合せ、０．１〜１．０ｍｍΦの大きさとされており、これらの弾性体凸部２７と２８は、同時に形成され、他の部分はエッチングで除去される。また、パワー半導体素子２２の裏面２４の外周部にも、同様に厚み３〜５μｍ、幅０．０１〜０．１ｍｍで方形輪状の弾性体凸部（膜）２９が形成される。   Further, on the outer peripheral portion of the surface 23 of the power semiconductor element 22, an elastic convex portion (film) 27 for avoiding contact with the circuit surface made of polyimide or resist is 3 to 5 μm in thickness and 0.01 to 0.1 mm in width. In the center portion, an elastic convex portion (film) 28 made of polyimide or resist having a thickness of 3 to 5 μm is formed at the center portion for protecting the push-up needle. The elastic convex portion 28 is 0.1 to 1.0 mmΦ in accordance with the tip diameter of the push-up needle. These elastic convex portions 27 and 28 are formed at the same time, and the other portions are etched. Is removed. Similarly, a rectangular ring-shaped elastic convex portion (film) 29 having a thickness of 3 to 5 μm and a width of 0.01 to 0.1 mm is also formed on the outer peripheral portion of the back surface 24 of the power semiconductor element 22.

上記弾性体凸部２７は、図４（Ｂ）の状態で、裏面（電極）２４に金属バンプ２５を形成する際に、パワー半導体素子２２の表面２３と集合基板（ウェハー）台面との接触を防止し、また金属バンプ接合を行う際にも、表面２３とボンディングツールとの接触を防止する役目をし、上記弾性体凸部２９は、その外側の隙間（素子２２間の隙間）が個片化ダイシング時の切断ラインの役目、金属バンプ形成時のアライメントマークの役目をする。   When the metal bumps 25 are formed on the back surface (electrode) 24 in the state shown in FIG. 4B, the elastic convex portion 27 makes contact between the surface 23 of the power semiconductor element 22 and the collective substrate (wafer) base surface. Also, when the metal bump bonding is performed, it serves to prevent the contact between the surface 23 and the bonding tool, and the elastic convex portion 29 has a gap (gap between the elements 22) on the outside. It functions as a cutting line during dicing and as an alignment mark when forming metal bumps.

図５には、金属バンプをスタッドバンプボンダーにより形成するバンプ形成工程が示されており、この工程では、図５（Ａ）に示されるように、多数のパワー半導体素子回路を形成した集合基板（ウェハー）３１がその金属バンプ形成面（裏面側）を上側にしてボンディングステージ上に設置される。このとき、集合基板３１には、パワー半導体素子毎に弾性体凸部２７，２８が形成されているため、表面とボンディングステージ面が接触することがなく、パワー半導体素子回路に傷やダメージを生じさせることがない。   FIG. 5 shows a bump forming process in which metal bumps are formed by a stud bump bonder. In this process, as shown in FIG. 5 (A), a collective substrate (in which a large number of power semiconductor element circuits are formed) (Wafer) 31 is placed on the bonding stage with its metal bump formation surface (back side) facing up. At this time, since the elastic body convex portions 27 and 28 are formed on the collective substrate 31 for each power semiconductor element, the surface and the bonding stage surface do not contact each other, and the power semiconductor element circuit is damaged or damaged. I will not let you.

このバンプ形成工程では、図５（Ａ）のように、スタッドバンプボンダーを構成するキャピラリー３２から金属バンプ２５の材料である金属細線３３が供給されるが、この金属細線３３として、１５〜２０μｍの線径を有する金，銅等が使用される。まず、この金属細線３３に対しトーチロッド３４により２０００〜３０００Ｖの高圧電荷が印加され、その放電現象によってボール３５が形成され、その後、集合基板３１の所定位置にステージ温度１００〜１５０℃で加熱・加圧し、超音波振動を発生させることにより金属バンプ２５が形成される。この金属バンプ２５が形成された後、金属細線３３は引きちぎりにより金属バンプ２５の先端から切断される。この引きちぎりを容易にするため、金属細線３３には所定間隔で潰し等が入れられている。このような動作を繰り返すことで、図５（Ｂ）のように、多数の金属バンプ２５がパワー半導体素子回路毎に形成されるが、この際には、弾性体凸部２９が金属バンプ形成のための位置決めのアライメントマークとして機能することになる。   In this bump forming step, as shown in FIG. 5A, a metal fine wire 33 which is a material of the metal bump 25 is supplied from the capillary 32 constituting the stud bump bonder. The metal fine wire 33 has a thickness of 15 to 20 μm. Gold, copper, etc. having a wire diameter are used. First, a high voltage charge of 2000 to 3000 V is applied to the thin metal wire 33 by the torch rod 34, and the ball 35 is formed by the discharge phenomenon, and then heated to a predetermined position of the collective substrate 31 at a stage temperature of 100 to 150 ° C. Metal bumps 25 are formed by applying pressure and generating ultrasonic vibration. After the metal bumps 25 are formed, the fine metal wires 33 are cut off from the tips of the metal bumps 25 by tearing. In order to facilitate this tearing, the fine metal wires 33 are crushed at predetermined intervals. By repeating such an operation, as shown in FIG. 5B, a large number of metal bumps 25 are formed for each power semiconductor element circuit. At this time, the elastic protrusions 29 are formed on the metal bumps. Therefore, it functions as an alignment mark for positioning.

図６には、金属リードフレームへ金属バンプを形成する場合のバンプ形成工程が示されており、この例では、ワイヤーボンダーを使用することで容易に金属バンプが形成できる。また、このバンプ形成工程では、金属リードフレーム１３に上記パワー半導体素子２２上に形成したような弾性体凸部２９がないため、図６（Ａ）のように、予め金属バンプ形成箇所にエッチングや金型法等により深さ３０〜５０μｍの窪み（凹部）３７を設けることが好ましい。そして、窪み３７に対し、図５の場合と同様にして金属バンプ２５が順に形成されることで、図６（Ｂ）のように、多数の金属バンプ２５がパワー半導体素子毎に形成される。また、上記の窪み３７は、金属バンプ２５のアンカー効果としても機能することになる。なお、金属バンプ２５の形成に銅ワイヤーを使用する場合、ボール形成において還元性雰囲気を追加した装置が必要である。   FIG. 6 shows a bump forming process in the case where metal bumps are formed on a metal lead frame. In this example, metal bumps can be easily formed by using a wire bonder. Further, in this bump forming process, since the metal lead frame 13 does not have the elastic convex portion 29 as formed on the power semiconductor element 22, the metal bump forming portion is previously etched or etched as shown in FIG. It is preferable to provide a recess (concave portion) 37 having a depth of 30 to 50 μm by a mold method or the like. Then, the metal bumps 25 are sequentially formed in the depressions 37 in the same manner as in FIG. 5, so that a large number of metal bumps 25 are formed for each power semiconductor element as shown in FIG. 6B. Further, the above-described depression 37 also functions as an anchor effect of the metal bump 25. In addition, when using a copper wire for formation of the metal bump 25, the apparatus which added the reducing atmosphere in ball formation is required.

次に、図７には、パワー半導体素子を個片化するダンシング工程の様子が示されており、図７に示されるように、ウェハーリング（台）３８には搬送等のためにダイシングテープ（ＵＶテープ）３９が設けられ、このダイシングテープ３９の上に、バンプ形成工程が終了した集合基板（ウェハー）３１が配置されており、この集合基板３１がブレード４０（ダイシング法）によって個別化される。このときには、図４で説明したように、各パワー半導体素子２２の間の各弾性体凸部２９同士の隙間をダンシングラインＬｄとして切削が行われる。即ち、金属バンプ２５が形成された裏面を下にしてダイシングをする場合は、金属バンプ２５の高さが２５〜５０μｍ程度であり、このような高さの突起が多数配列された面をダイシングテープ３９に貼り付けるためには、８０〜１５０μｍのテープの糊厚が必要となるため現実的ではない。そこで、実施例では、金属バンプ形成面ではない表面側をダイシングテープ３９に貼り付けるが、この場合は、通常の集合基板３１の裏面側には全面に電極２４が形成されているため、目印となるダイシングラインがなく切削できないが、弾性体凸部２９を設けたことで、隣接するパワー半導体素子間の弾性体凸部２９間を目印にして（位置合せして）ブレード４０で切削し、パワー半導体素子２２を個片化することができる。   Next, FIG. 7 shows a state of a dancing process for dividing the power semiconductor element into pieces, and as shown in FIG. (UV tape) 39 is provided, and on this dicing tape 39, a collective substrate (wafer) 31 after the bump forming process is arranged, and this collective substrate 31 is individualized by a blade 40 (dicing method). . At this time, as described with reference to FIG. 4, the cutting is performed with the gap between the elastic convex portions 29 between the power semiconductor elements 22 as the dancing line Ld. That is, when dicing with the back surface on which the metal bumps 25 are formed facing down, the height of the metal bumps 25 is about 25 to 50 [mu] m, and the surface on which a large number of projections having such heights are arranged is a dicing tape. In order to affix to 39, the adhesive thickness of a tape of 80-150 micrometers is needed, and it is not realistic. Therefore, in the embodiment, the surface side which is not the metal bump forming surface is attached to the dicing tape 39. In this case, since the electrode 24 is formed on the entire back surface side of the normal collective substrate 31, the mark and Although there is no dicing line, cutting is not possible, but by providing the elastic convex portion 29, cutting is performed with the blade 40 using the blade 40 as a mark (alignment) between the elastic convex portions 29 between adjacent power semiconductor elements. The semiconductor element 22 can be singulated.

図８には、上記ダンシング工程後の各パワー半導体素子の取出し（ピックアップ）の様子が示されており、ここでは、集合基板３１から切り離された個々のパワー半導体素子２２がウェハーリング３８上のダイシングテープ３９（ＵＶ照射により粘着力を低下させた後）から剥がされながらピックアップされる。即ち、パワー半導体素子２２は、ダイシングテープ３９の下側より突上げ針４１によって突き上げられると同時に、中空化された円柱形のツールであるコレット４２にて吸着されることで、ダイシングテープ３９から剥離され、このコレット４２の吸着力でパワー半導体素子２２が保持される。   FIG. 8 shows a state where each power semiconductor element is taken out (pickup) after the above-described dancing process. Here, the individual power semiconductor elements 22 separated from the collective substrate 31 are diced on the wafer ring 38. The tape is picked up while being peeled off from the tape 39 (after the adhesive strength is reduced by UV irradiation). That is, the power semiconductor element 22 is pushed up from the lower side of the dicing tape 39 by the push-up needle 41 and at the same time is adsorbed by the collet 42 which is a hollow cylindrical tool, thereby peeling from the dicing tape 39. The power semiconductor element 22 is held by the suction force of the collet 42.

このようなパワー半導体素子２２の突上げでは、突上げ針４１が弾性体凸部２８に接触するので、パワー半導体素子２２の表面２３が保護され、この半導体素子自体やその表面電極へのダメージが回避される。   In such push-up of the power semiconductor element 22, the push-up needle 41 contacts the elastic convex portion 28, so that the surface 23 of the power semiconductor element 22 is protected, and damage to the semiconductor element itself and its surface electrode is prevented. Avoided.

図９には、金属バンプの接合工程（図５のように素子自体に金属バンプを設けた場合の接合工程）が示されており、図８のコレット４２で吸着保持されたパワー半導体素子２２は、ボンディングツール（中心部からのエアー吸着により保持するもの）４３に受け渡された後、このボンディングツール４３によって、図９（Ａ）のように、金属リードフレーム１３の接合位置に加熱・圧接される。このときの加熱温度は、例えば室温（又は１００℃）〜１５０℃で、接合荷重を金属バンプ当り０．２〜０．５Ｎとし、超音波振動（４０〜６０ｋＨｚ）を与えながら接合が行われる（図９（Ｂ））。即ち、ボンディングツール４３は超音波ホーンの先端部に取り付け固定されており、超音波ホーンがホーン長方向へ弾性振動を起こすのに同期して、ボンディングツール４３が超音波ホーン長方向に揺動することで、超音波振動が発生する。なお、金属リードフレーム１３や金属バンプ２５に対するクリーンルーム内の汚染の影響で接合が不完全になる恐れがある場合は、Ａｒプラズマ及び窒素雰囲気での保管等の管理を行うことで安定化することが可能である。   FIG. 9 shows a bonding process of metal bumps (bonding process in the case where metal bumps are provided on the element itself as shown in FIG. 5). The power semiconductor element 22 attracted and held by the collet 42 of FIG. After being transferred to the bonding tool (which is held by air adsorption from the center) 43, the bonding tool 43 is heated and pressed to the bonding position of the metal lead frame 13 as shown in FIG. The The heating temperature at this time is, for example, room temperature (or 100 ° C.) to 150 ° C., the bonding load is 0.2 to 0.5 N per metal bump, and bonding is performed while applying ultrasonic vibration (40 to 60 kHz) ( FIG. 9B). That is, the bonding tool 43 is attached and fixed to the tip of the ultrasonic horn, and the bonding tool 43 swings in the ultrasonic horn length direction in synchronization with the elastic horn causing elastic vibration in the horn length direction. As a result, ultrasonic vibration is generated. If there is a possibility that the bonding may be incomplete due to the contamination in the clean room with respect to the metal lead frame 13 or the metal bumps 25, the metal lead frame 13 or the metal bumps 25 can be stabilized by management such as storage in an Ar plasma and nitrogen atmosphere. Is possible.

そして、このような金属バンプ接合工程では、圧接時及び超音波振動時においてパワー半導体素子２２の表面２３に形成された弾性体凸部２７が表面２３とボンディングツール４３との接触をなくし、パワー半導体素子２２の表面電極（又は回路部）に傷やダメージが生じるのを防ぐことになる。また、ボンディングツール４３においても、パワー半導体素子２２との直接的な接触が避けられるため、ボンディングツール４３の滑りによる磨耗の発生が低下し、長寿命化が可能となる。即ち、従来、弾性体凸部２７がない場合には、ボンディングツール４３の先端面とパワー半導体素子２２の吸着面との間で、超音波振動方向で滑りが発生し、ボンディングツール４３の先端面が磨耗すると共に、この両者間の摩擦力が低下し超音波振動方向の滑りが更に悪化することで、接合不良を引き起こすことから、ボンディングツール４３は短い期間で定期交換が行われるが、弾性体凸部２７を設けたことで、ボンディングツール４３を長い期間使用することができるという利点がある。   In such a metal bump bonding process, the elastic convex portion 27 formed on the surface 23 of the power semiconductor element 22 at the time of pressure welding and ultrasonic vibration eliminates the contact between the surface 23 and the bonding tool 43, and the power semiconductor. This prevents the surface electrode (or circuit portion) of the element 22 from being scratched or damaged. Also, since the direct contact with the power semiconductor element 22 is avoided in the bonding tool 43, the occurrence of wear due to the sliding of the bonding tool 43 is reduced, and the life can be extended. That is, conventionally, when there is no elastic convex portion 27, slip occurs in the ultrasonic vibration direction between the tip surface of the bonding tool 43 and the suction surface of the power semiconductor element 22, and the tip surface of the bonding tool 43. Since the frictional force between them decreases and the slip in the ultrasonic vibration direction further deteriorates, causing bonding failure, the bonding tool 43 is periodically replaced in a short period of time. By providing the convex portion 27, there is an advantage that the bonding tool 43 can be used for a long period of time.

図１０には、金属バンプの接合工程（図６のようにリードフレームに金属バンプを設けた場合の接合工程）が示されており、この場合は、図６のように金属リードフレーム１３に形成した金属バンプ２５に対し、金属バンプを設けずにコレット４２で吸着保持されたパワー半導体素子４４の所定位置を上記と同様にして圧接し、超音波振動を与えることで接合が行われる。   FIG. 10 shows a bonding process of metal bumps (bonding process when metal bumps are provided on the lead frame as shown in FIG. 6). In this case, the metal bump is formed on the metal lead frame 13 as shown in FIG. A predetermined position of the power semiconductor element 44 adsorbed and held by the collet 42 without providing the metal bump is pressed against the metal bump 25 in the same manner as described above, and bonding is performed by applying ultrasonic vibration.

上記のような超音波振動による金属バンプ接合によれば、金属バンプ２５の潰し込み量が制御し易く、半田接合に比較して、バンプ接合部の厚み（縦方向）を任意かつ一定に設定することができ、応力の発生、クラックの発生等がなくなるという利点がある。   According to the metal bump bonding by ultrasonic vibration as described above, the crushing amount of the metal bump 25 is easy to control, and the thickness (vertical direction) of the bump bonding portion is set arbitrarily and constant as compared with the solder bonding. There is an advantage that generation of stress, generation of cracks and the like are eliminated.

１，１０，２２，４４…パワー半導体素子、 ２…半田、
３，１３…金属リードフレーム、 ４，１５…内部リード部、
５，１６…金属線、 ６…封止樹脂、
１１…表面電極、 １２…裏面電極、
１４，２５…金属バンプ、 ３１…集合基板、
２３…表面（電極）、 ２４…裏面（電極）、
２７，２８，２９…弾性体凸部（膜）、
３９…ダイシングテープ、 ４２…コレット、
４１…突上げ針、 ４３…ボンディングツール。 1, 10, 22, 44 ... power semiconductor element, 2 ... solder,
3, 13 ... Metal lead frame, 4, 15 ... Internal lead part,
5, 16 ... Metal wire, 6 ... Sealing resin,
11 ... Front electrode, 12 ... Back electrode,
14, 25 ... metal bumps, 31 ... collective substrate,
23 ... front surface (electrode), 24 ... back surface (electrode),
27, 28, 29 ... elastic body convex part (film),
39 ... Dicing tape, 42 ... Collet,
41 ... Push-up needle, 43 ... Bonding tool.

Claims (4)

表裏面に電極が形成されたパワー半導体素子と、このパワー半導体素子を接合し、かつ放熱板としても機能する金属リードフレームとを設け、この金属リードフレームの一部を放熱のために露出させながら全体を樹脂封止してなるパワー半導体装置において、
上記金属リードフレームに高純度の無酸素銅を用い、
上記パワー半導体素子の基板に炭化珪素を用い、かつ該パワー半導体素子の表面電極としてチタン膜の上にアルミニウム膜を形成し、このパワー半導体素子の表面電極を上記金属リードフレームの内部リードに銅線にて接合する構成とし、
上記パワー半導体素子の裏面電極として形成された金膜又は銀膜の上に、高純度の金又は銅からなる金属バンプを介して、上記金属リードフレームを接合してなることを特徴とするパワー半導体装置。 A power semiconductor element having electrodes formed on the front and back surfaces, and a metal lead frame that joins the power semiconductor element and also functions as a heat sink, and a part of the metal lead frame are exposed for heat dissipation In the power semiconductor device formed by resin sealing the whole,
Using high purity oxygen-free copper for the metal lead frame,
Silicon carbide is used for the substrate of the power semiconductor element, and an aluminum film is formed on the titanium film as the surface electrode of the power semiconductor element, and the surface electrode of the power semiconductor element is connected to the internal lead of the metal lead frame with a copper wire. It is configured to be joined at
A power semiconductor comprising the metal lead frame joined to a gold film or silver film formed as a back electrode of the power semiconductor element via a metal bump made of high-purity gold or copper. apparatus. 表裏面に電極が形成されたパワー半導体素子を設け、このパワー半導体素子を金属リードフレームに接合するパワー半導体装置の製造方法において、In the method of manufacturing a power semiconductor device in which a power semiconductor element having electrodes formed on the front and back surfaces is provided and the power semiconductor element is bonded to a metal lead frame,
上記パワー半導体素子の表面電極としてチタン膜の上にアルミニウム膜を形成し、このパワー半導体素子の表面電極を上記金属リードフレームの内部リードに銅線にて接合し、An aluminum film is formed on the titanium film as a surface electrode of the power semiconductor element, and the surface electrode of the power semiconductor element is bonded to an internal lead of the metal lead frame with a copper wire,
上記パワー半導体素子の表面電極又は裏面金属膜、又は上記金属リードフレームに、半田材でない金属バンプを形成し、Form a metal bump that is not a solder material on the front electrode or back surface metal film of the power semiconductor element, or the metal lead frame,
上記パワー半導体素子の金属バンプを形成しない面の外周に、弾性体からなる凸部を設けると共に、上記金属リードフレームの金属バンプの形成又は圧接位置に予め窪みを設け、Providing a convex portion made of an elastic body on the outer periphery of the surface of the power semiconductor element where the metal bump is not formed, and providing a depression in advance in the metal bump formation or pressure contact position of the metal lead frame,
上記パワー半導体素子を金属バンプが配置されない面から加圧しながら、超音波振動を与えることにより、上記パワー半導体素子と上記金属リードフレームとを接合することを特徴とするパワー半導体装置の製造方法。A method of manufacturing a power semiconductor device, wherein the power semiconductor element and the metal lead frame are joined by applying ultrasonic vibration while pressing the power semiconductor element from a surface where the metal bump is not disposed. 複数のパワー半導体素子が形成された集合基板の各パワー半導体素子に金属バンプを形成した後、この集合基板を切削することで、個々のパワー半導体素子を製作するとき、個々のパワー半導体素子の金属バンプ形成面の外周に、各パワー半導体素子間の境界を識別する隙間を残した状態で、弾性体からなる凸部を設けたことを特徴とする請求項２に記載のパワー半導体装置の製造方法。When forming individual power semiconductor elements by forming metal bumps on each power semiconductor element of the aggregate substrate on which a plurality of power semiconductor elements are formed and then cutting the aggregate substrate, the metal of each power semiconductor element 3. The method of manufacturing a power semiconductor device according to claim 2, wherein a protrusion made of an elastic body is provided on the outer periphery of the bump forming surface with a gap for identifying a boundary between the power semiconductor elements remaining. . 上記パワー半導体素子の上記金属バンプが配置されない面で、搬送時に金属針により突き上げられる部分に、弾性体を設けたことを特徴とする請求項２又は３記載のパワー半導体装置の製造方法。4. The method of manufacturing a power semiconductor device according to claim 2, wherein an elastic body is provided on a portion of the power semiconductor element on which the metal bumps are not disposed and is pushed up by a metal needle during transportation.

JP2012033266A 2012-02-17 2012-02-17 Power semiconductor device and manufacturing method thereof Active JP5946286B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012033266A JP5946286B2 (en) 2012-02-17 2012-02-17 Power semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012033266A JP5946286B2 (en) 2012-02-17 2012-02-17 Power semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2013171878A JP2013171878A (en) 2013-09-02
JP5946286B2 true JP5946286B2 (en) 2016-07-06

Family

ID=49265673

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012033266A Active JP5946286B2 (en) 2012-02-17 2012-02-17 Power semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP5946286B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6002437B2 (en) * 2012-05-17 2016-10-05 新日本無線株式会社 Semiconductor device and manufacturing method thereof

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63148646A (en) * 1986-12-12 1988-06-21 Toshiba Corp Semiconductor device
JPH04334049A (en) * 1991-05-09 1992-11-20 Sony Corp Package for semiconductor device, and semiconductor device using same
JPH10189851A (en) * 1996-12-24 1998-07-21 Hitachi Cable Ltd Lead frame for semiconductor
JP3811567B2 (en) * 1998-03-12 2006-08-23 株式会社日立製作所 Manufacturing method of semiconductor device
JP4260263B2 (en) * 1999-01-28 2009-04-30 株式会社ルネサステクノロジ Semiconductor device
JP2000252378A (en) * 1999-02-26 2000-09-14 Fujitsu Ltd Semiconductor device
JP4148848B2 (en) * 2003-08-06 2008-09-10 株式会社東芝 Manufacturing method of semiconductor device
JP5120917B2 (en) * 2006-11-30 2013-01-16 独立行政法人産業技術総合研究所 Semiconductor device and manufacturing method thereof
JP2011040610A (en) * 2009-08-12 2011-02-24 Fujikura Ltd Semiconductor device and method of manufacturing the same
JP2011216753A (en) * 2010-04-01 2011-10-27 Panasonic Corp Semiconductor device, and method of manufacturing the same

Also Published As

Publication number Publication date
JP2013171878A (en) 2013-09-02

Similar Documents

Publication Publication Date Title
JP4262672B2 (en) Semiconductor device and manufacturing method thereof
JP6433590B2 (en) Power semiconductor device manufacturing method and power semiconductor device
CN103035601A (en) Semiconductor device including diffusion soldered layer on sintered silver layer
JP2009206482A (en) Semiconductor device and its production process
JP3439417B2 (en) Connection conductor for semiconductor package, semiconductor package, and method for assembling semiconductor package
JP6448388B2 (en) Power semiconductor device
JP6102598B2 (en) Power module
JP2012243889A (en) Semiconductor device and manufacturing method of the same
EP1367644A1 (en) Semiconductor electronic device and method of manufacturing thereof
JP2010287726A (en) Semiconductor device
JP5946286B2 (en) Power semiconductor device and manufacturing method thereof
JP2006196765A (en) Semiconductor device
JP2015144169A (en) semiconductor module
JP2007027565A (en) Manufacturing method of semiconductor device
JP5444299B2 (en) Semiconductor device
JP2016086003A (en) Manufacturing method of power semiconductor device
JP5120917B2 (en) Semiconductor device and manufacturing method thereof
JP2015144199A (en) semiconductor device
JP5418654B2 (en) Semiconductor device
JP5884625B2 (en) Semiconductor device
US9799624B1 (en) Wire bonding method and wire bonding structure
JP2016134547A (en) Semiconductor device
JP2015053442A (en) Semiconductor device
JP5017228B2 (en) Semiconductor device
US20230017286A1 (en) Semiconductor die with stepped side surface

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20141205

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20160113

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160119

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160222

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20160517

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20160531

R150 Certificate of patent or registration of utility model

Ref document number: 5946286

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250