JP2016086003A - Manufacturing method of power semiconductor device - Google Patents

Manufacturing method of power semiconductor device Download PDF

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JP2016086003A
JP2016086003A JP2014215928A JP2014215928A JP2016086003A JP 2016086003 A JP2016086003 A JP 2016086003A JP 2014215928 A JP2014215928 A JP 2014215928A JP 2014215928 A JP2014215928 A JP 2014215928A JP 2016086003 A JP2016086003 A JP 2016086003A
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wire
power semiconductor
bonding
metal plate
semiconductor element
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翔平 小川
Shohei Ogawa
翔平 小川
藤野　純司
Junji Fujino
純司 藤野
祥久 内田
Yoshihisa Uchida
祥久 内田
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a power semiconductor device, capable of forming a semiconductor element without damaging it when performing wire bonding.SOLUTION: By previously joining a metal plate 4a to the bottom of one end 5a of a wire 5 to flatten the bottom and wire-bonding a connection surface of the one end 5a of the wire 5 flattened by the metal plate 4a to a surface electrode 3 of a power semiconductor element 3 die-bonded on an insulating substrate 1, energy concentration in bonding can be prevented and damage to the semiconductor element can be sufficiently suppressed.SELECTED DRAWING: Figure 4

Description

この発明は、半導体素子と外部電極との電気配線にワイヤボンディングを用いるパワー半導体装置の製造方法に関する。   The present invention relates to a method of manufacturing a power semiconductor device using wire bonding for electrical wiring between a semiconductor element and an external electrode.

従来、パワー半導体装置の電気配線のために、Ａｌワイヤボンディングが行われているが、高信頼化の要求からワイヤの材料を見直す必要があった。また、パワーモジュールに搭載される半導体素子として、動作温度が高く効率に優れているＳｉＣ（炭化ケイ素）半導体素子が、今後の主流となる可能性が高いため、パワーモジュールは、ＳｉＣ半導体素子に適用できることも同時に求められている。
そこで、機械強度が高く導電率が高いため信頼性と電流密度を向上することが可能なことから、Ｃｕワイヤボンディングの開発が行われている。しかし、従来のＡｌワイヤを用いた時と同様のウェッジボンディングで、Ｃｕワイヤを用いたボンディングを行った場合、ＣｕはＡｌと比較するとヤング率が高いため、ボンディング時に半導体素子にダメージを与えることが懸念される。半導体素子にダメージを与えることなくＣｕワイヤをボンディングする方法が求められている。 Conventionally, Al wire bonding has been performed for electric wiring of a power semiconductor device, but it has been necessary to review the material of the wire in order to achieve high reliability. Moreover, as a semiconductor element mounted on the power module, a SiC (silicon carbide) semiconductor element having a high operating temperature and excellent efficiency is likely to become the mainstream in the future. Therefore, the power module is applied to the SiC semiconductor element. What can be done is also required.
Therefore, Cu wire bonding has been developed because it has high mechanical strength and high electrical conductivity, so that reliability and current density can be improved. However, in the case of bonding using Cu wire in the same wedge bonding as when using conventional Al wire, Cu has a higher Young's modulus than Al, so it may damage semiconductor elements during bonding. Concerned. There is a need for a method of bonding Cu wires without damaging semiconductor elements.

特許文献１では、金属箔を半導体素子の電極上に配置し、金属箔と一緒にワイヤと半導体素子電極を接合することで半導体素子のダメージを抑制し、接合後、金属箔の余分な領域を取り除く技術が開示されている。また、特許文献２では、シート状部材を半導体素子電極に接合後、ワイヤやスタッドバンプのボンディングを行うことで半導体素子のダメージを抑制する技術が開示されている。   In Patent Document 1, a metal foil is arranged on an electrode of a semiconductor element, and the damage of the semiconductor element is suppressed by bonding the wire and the semiconductor element electrode together with the metal foil. The removal technique is disclosed. Patent Document 2 discloses a technique for suppressing damage to a semiconductor element by bonding a wire or stud bump after bonding a sheet-like member to a semiconductor element electrode.

特開平１０−２６１６６４号公報（段落００６０〜００６２、図１）Japanese Patent Laid-Open No. 10-261664 (paragraphs 0060-0062, FIG. 1) 特開２０００−１００８４８号公報（段落００１６、図１）JP 2000-1000084 (paragraph 0016, FIG. 1)

しかし、特許文献１では、金属箔を半導体素子電極とワイヤの間に配置し、金属箔と一緒にワイヤを電極に接合することから、一度の接合で二つの接合面を接合する必要があり、ワイヤより金属箔が柔らかいためワイヤの形状に沿って金属箔のみが選択的に変形し、半導体素子との接触面積が小さくなる。そのため、狭い領域にエネルギーが集中するので、半導体素子へのダメージを十分に抑制することができないという問題があった。また、金属箔の配置位置がずれる可能性があり、金属箔の配置位置がずれた場合にはワイヤボンダがボンディング位置を認識できず、エラーが発生するという問題があった。さらに、金属箔の余分な領域を取り除く際、ワイヤボンディング部にダメージが生じ、接合不良となるという問題があった。   However, in Patent Document 1, since the metal foil is disposed between the semiconductor element electrode and the wire, and the wire is bonded to the electrode together with the metal foil, it is necessary to bond the two bonding surfaces by one bonding. Since the metal foil is softer than the wire, only the metal foil is selectively deformed along the shape of the wire, and the contact area with the semiconductor element is reduced. For this reason, energy concentrates in a narrow region, and there is a problem that damage to the semiconductor element cannot be sufficiently suppressed. In addition, there is a possibility that the arrangement position of the metal foil may be shifted, and when the arrangement position of the metal foil is shifted, the wire bonder cannot recognize the bonding position and an error occurs. Furthermore, when removing the excess area | region of metal foil, there existed a problem that a wire bonding part was damaged and it became a joining defect.

特許文献２では、半導体素子の電極上にシート状部材を形成するが、パワー半導体装置を樹脂により絶縁封止する工程で、半導体素子の電極とシート状部材の間の未接合領域に樹脂が入り込まず、絶縁不良になるという問題があった。   In Patent Document 2, a sheet-like member is formed on an electrode of a semiconductor element, but the resin enters an unjoined region between the electrode of the semiconductor element and the sheet-like member in a process of insulatingly sealing the power semiconductor device with resin. In other words, there was a problem of poor insulation.

この発明は、上記のような課題を解決するためになされたものであり、ワイヤをボンディングする場合に、半導体素子にダメージを与えることなく、接合強度が高く、絶縁性に優れたボンディング部を、効率よく形成することを可能にするパワー半導体装置の製造方法を提供することを目的とする。   The present invention was made to solve the above-described problems.When bonding wires, a bonding portion having high bonding strength and excellent insulation without damaging a semiconductor element. It is an object of the present invention to provide a method of manufacturing a power semiconductor device that can be efficiently formed.

この発明のパワー半導体装置の製造方法は、ワイヤの接続面に金属板を接合して、パワー半導体素子の表面形状に応じた平坦な形状部を有する接続部を形成する工程と、ワイヤの接続面に形成された接続部を、パワー半導体素子の表面電極にボンディングする工程とを含むことを特徴とするものである。   The method for manufacturing a power semiconductor device according to the present invention includes a step of bonding a metal plate to a connection surface of a wire to form a connection portion having a flat shape portion corresponding to the surface shape of the power semiconductor element, and a connection surface of the wire And a step of bonding the connection portion formed on the surface electrode of the power semiconductor element.

この発明によれば、ワイヤにパワー半導体素子の表面形状に応じた平坦な形状部を有する接続部を形成して、ワイヤの接続部をパワー半導体素子の表面電極にボンディングすることで、半導体素子との接触面積を拡げることができ、ボンディングの際のエネルギー集中を防ぎ、半導体素子へのダメージを十分に抑制することができる。   According to the present invention, the connection portion having a flat shape portion corresponding to the surface shape of the power semiconductor element is formed on the wire, and the connection portion of the wire is bonded to the surface electrode of the power semiconductor element. The contact area can be expanded, energy concentration during bonding can be prevented, and damage to the semiconductor element can be sufficiently suppressed.

この発明の実施の形態１によるパワー半導体装置の外観を示す模式図である。It is a schematic diagram which shows the external appearance of the power semiconductor device by Embodiment 1 of this invention. この発明の実施の形態１によるパワー半導体装置の構成を示す拡大断面図である。It is an expanded sectional view which shows the structure of the power semiconductor device by Embodiment 1 of this invention. この発明の実施の形態１によるパワー半導体装置の製造工程を示す拡大断面図である。It is an expanded sectional view which shows the manufacturing process of the power semiconductor device by Embodiment 1 of this invention. この発明の実施の形態１によるパワー半導体装置の製造工程を示す拡大断面図である。It is an expanded sectional view which shows the manufacturing process of the power semiconductor device by Embodiment 1 of this invention. この発明の実施の形態１によるパワー半導体装置の製造工程の他の例を示す平面図である。It is a top view which shows the other example of the manufacturing process of the power semiconductor device by Embodiment 1 of this invention. この発明の実施の形態１によるパワー半導体装置の他の製造工程を示す拡大断面図である。It is an expanded sectional view which shows the other manufacturing process of the power semiconductor device by Embodiment 1 of this invention. この発明の実施の形態１によるパワー半導体装置の他の製造工程を示す拡大断面図である。It is an expanded sectional view which shows the other manufacturing process of the power semiconductor device by Embodiment 1 of this invention. この発明の実施の形態２によるパワー半導体装置の構成及び製造方向を示す外観模式図である。It is an external appearance schematic diagram which shows the structure and manufacturing direction of the power semiconductor device by Embodiment 2 of this invention.

実施の形態１．
この発明の実施の形態１であるパワー半導体装置について、図を参照しながら以下に説明する。
図１は、この発明の実施の形態１におけるパワー半導体装置１００の構成を示す外観模式図であり、図２は、図１のＡ−Ａ′線での矢視断面の部分拡大図である。パワー用半導体装置の構成は、実際にはさらに複数の部材を備えているが、説明を簡単にするため、説明に必要な部分のみを記載し、他の部分については省略している（例えば、ゲート配線用ワイヤや、ケース、封止樹脂等）。 Embodiment 1 FIG.
A power semiconductor device according to a first embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 is a schematic external view showing the configuration of a power semiconductor device 100 according to Embodiment 1 of the present invention, and FIG. 2 is a partially enlarged view taken along the line AA ′ of FIG. The configuration of the power semiconductor device actually includes a plurality of members. However, for the sake of simplicity, only the portions necessary for the description are described, and other portions are omitted (for example, Gate wiring wire, case, sealing resin, etc.).

図１および図２に示すように、パワー半導体装置１００は、絶縁基板１と、絶縁基板１上のパターン１ａにはんだ２により裏面電極３ｂをダイボンドされたパワー半導体素子３と、パワー半導体素子３の上部の表面電極３ａに接続部としての金属板４ａを介してワイヤボンディングされた電気配線用のワイヤ５とから構成される。   As shown in FIGS. 1 and 2, a power semiconductor device 100 includes an insulating substrate 1, a power semiconductor element 3 in which a back electrode 3 b is die-bonded to a pattern 1 a on the insulating substrate 1 by solder 2, It is composed of an electric wiring wire 5 wire-bonded to the upper surface electrode 3a via a metal plate 4a as a connecting portion.

絶縁基板１には、セラミック基板である窒化アルミニウム（ＡｌＮ）製ＤＢＣ（Direct Bonded Copper）基板（例えば、外形寸法４０ｍｍ×３０ｍｍ×厚さ０．６ｍｍ）が用いられる。絶縁基板１の表面には、Ｃｕ製の導体層であるパターン１ａ（例えば、パターン厚さ０．２ｍｍ）とパターン１ｂ（例えば、パターン厚さ０．２ｍｍ）が設けられている。パターン１ａ上にはパワー半導体素子３が配置され、パターン１ｂ上にはパワー半導体素子３の上部の表面電極３ａと、ワイヤ５の一端５ａと接続されるワイヤ５の他端５ｂとがウェッジワイヤボンディングされている。   As the insulating substrate 1, a DBC (Direct Bonded Copper) substrate made of aluminum nitride (AlN), which is a ceramic substrate (for example, external dimensions 40 mm × 30 mm × thickness 0.6 mm) is used. On the surface of the insulating substrate 1, a pattern 1a (for example, a pattern thickness of 0.2 mm) and a pattern 1b (for example, a pattern thickness of 0.2 mm), which are Cu conductive layers, are provided. The power semiconductor element 3 is arranged on the pattern 1a, and the surface electrode 3a on the upper side of the power semiconductor element 3 and the other end 5b of the wire 5 connected to one end 5a of the wire 5 are wedge-wire bonded on the pattern 1b. Has been.

なお、絶縁基板１は、ＡｌＮ基板に限るものではなく、セラミック基板としては、例えば、アルミナ（Ａｌ２Ｏ３）や炭化ケイ素（ＳｉＣ）、窒化ケイ素（Ｓｉ３Ｎ４）、などの絶縁基板基材を用いてもよい。セラミック基板以外では、ガラスエポキシ基板や、金属ベース基板でもよい。また、絶縁基板１は、ＤＢＣ基板としたが、ＤＢＣ基板をＮｉめっきしたものや、ＤＢＡ（Direct Bonded Aluminum、登録商標）基板などを用いてもよい。 The insulating substrate 1 is not limited to an AlN substrate. Examples of the ceramic substrate include an insulating substrate base such as alumina (Al 2 O 3 ), silicon carbide (SiC), silicon nitride (Si 3 N 4 ), and the like. A material may be used. Other than the ceramic substrate, a glass epoxy substrate or a metal base substrate may be used. Further, although the insulating substrate 1 is a DBC substrate, a DBC substrate plated with Ni, a DBA (Direct Bonded Aluminum, registered trademark) substrate, or the like may be used.

パワー半導体素子３としては、Ｓｉ製のＩＧＢＴ（Insulated Gate Bipolar Transistor、例えば、外形寸法１０ｍｍ×１０ｍｍ×厚さ０．１ｍｍ）を用いる。パワー半導体素子３には、表面電極３ａ（例えば、Ａｌ製、厚さ５ｕｍ）と裏面電極３ｂが設けられている。パワー半導体素子３は、裏面電極３ｂがはんだ２（例えば、Ｓｎ−Ａｇ−Ｃｕ）によりパターン１ａ上にダイボンドされる。また、パワー半導体素子３は、表面電極３ａが金属板４ａを介してワイヤ５の一端５ａとウェッジワイヤボンディングされることで、外部電極につながる絶縁基板１上のパターン１ｂに電気的に接続される。   As the power semiconductor element 3, Si IGBT (Insulated Gate Bipolar Transistor, for example, external dimensions 10 mm × 10 mm × thickness 0.1 mm) is used. The power semiconductor element 3 is provided with a front electrode 3a (for example, made of Al, thickness 5um) and a back electrode 3b. In the power semiconductor element 3, the back electrode 3 b is die-bonded on the pattern 1 a with solder 2 (for example, Sn—Ag—Cu). Further, the power semiconductor element 3 is electrically connected to the pattern 1b on the insulating substrate 1 connected to the external electrode by the surface electrode 3a being wedge-wire bonded to one end 5a of the wire 5 through the metal plate 4a. .

なお、パワー半導体素子３は、ＩＧＢＴに限るものではなく、他に、ＩＣ（Integrated Circuit）や、サイリスタ、ＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）のようなパワー半導体を用いることもできる。ＳＢＤ（Schottky Barrier Diode）やＪＢＳ（Junction Barrier Schottky）などのダイオードでもよい。また、パワー半導体以外の半導体パッケージを適用してもよい。
また、パワー半導体素子３は、シリコンウエハを基材とした一般的な素子でもよいが、この発明においては炭化ケイ素（ＳｉＣ）や窒化ガリウム（ＧａＮ）系材料、またはダイヤモンドといったシリコンと較べてバンドギャップが広い、いわゆるワイドバンドギャップ半導体材料を適用できる。
パワー半導体素子３の表面電極３ａは、Ａｌ製に限るものではなく、Ａｌ−Ｓｉや、Ａｌ−Ｓｉ−Ｃｕ、Ｃｕ、Ｎｉ、Ｎｉ／Ａｕなどの導体層としてもよい。表面電極３ａの厚さは、ワイヤボンディング後にパワー半導体素子３の性能に影響がないのであれば、５ｕｍ以下でもよい。
パワー半導体素子３をパターン１ａ上にダイボンドするはんだは、Ｓｎ−Ａｇ−Ｃｕはんだに限るものではなく、パワー半導体素子をダイボンドできれば、Ｐｂ入りはんだや、ＳｂやＮｉなどを添加したはんだ、ＡｕやＡｇ、Ｃｕなどのナノ粒子を用いた焼結接合であってもよい。 Note that the power semiconductor element 3 is not limited to the IGBT, and a power semiconductor such as an IC (Integrated Circuit), a thyristor, or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) can also be used. A diode such as SBD (Schottky Barrier Diode) or JBS (Junction Barrier Schottky) may be used. Further, a semiconductor package other than the power semiconductor may be applied.
The power semiconductor element 3 may be a general element based on a silicon wafer, but in the present invention, the band gap as compared with silicon such as silicon carbide (SiC), gallium nitride (GaN), or diamond. A so-called wide band gap semiconductor material can be applied.
The surface electrode 3a of the power semiconductor element 3 is not limited to Al but may be a conductor layer such as Al—Si, Al—Si—Cu, Cu, Ni, or Ni / Au. The thickness of the surface electrode 3a may be 5 μm or less as long as the performance of the power semiconductor element 3 is not affected after wire bonding.
The solder for die-bonding the power semiconductor element 3 on the pattern 1a is not limited to Sn-Ag-Cu solder. If the power semiconductor element can be die-bonded, solder containing Pb, solder added with Sb, Ni, or the like, Au or Ag Sintered bonding using nanoparticles such as Cu.

ワイヤ５は、Ｃｕ製のワイヤ（例えば、直径４００ｕｍ）を用いる。ワイヤ５の一端５ａは、金属板４ａを介してパワー半導体素子３の表面電極３ａと接続される。ワイヤ５の一端５ａ下面側の接続面は、予め金属板４ａに接合され、パワー半導体素子３の上部の表面電極３ａとウェッジワイヤボンディングされている。ワイヤ５の他端５ｂは、絶縁基板１のパターン１ｂにウェッジワイヤボンディングされている。ワイヤ５の一端５ａ下面側の接続面に、この金属板４ａを超音波接合し、パワー半導体素子３の表面の形状に対応する、平坦な形状部を有する接続部を形成することで、半導体素子との接触面積が拡がり、ボンディングの際のエネルギー集中を防ぐので、半導体素子へのダメージを十分に抑制することができる。
なお、ワイヤ５の材質は、Ｃｕ製としたが、これに限るものではない。電気配線部材として適切な導電率を有するものであれば、Ｃｕ系の合金や、純ＡｌやＡｌ系合金、ＡｕやＡｇ系の合金、Ｃｕなどの金属をコアとしＰｄやＡｌで被覆したワイヤでもよい。また、ＤＬＢ（Direct Lead Bonding）においてリードフレームとして使用されるＣｕなどの金属板でもよい。 As the wire 5, a Cu wire (for example, a diameter of 400 μm) is used. One end 5a of the wire 5 is connected to the surface electrode 3a of the power semiconductor element 3 through the metal plate 4a. The connection surface on the lower surface side of the end 5a of the wire 5 is bonded to the metal plate 4a in advance, and is wedge-bonded to the upper surface electrode 3a of the power semiconductor element 3. The other end 5 b of the wire 5 is wedge-wire bonded to the pattern 1 b of the insulating substrate 1. The metal plate 4 a is ultrasonically bonded to the connection surface on the lower surface side of the end 5 a of the wire 5, thereby forming a connection portion having a flat shape portion corresponding to the shape of the surface of the power semiconductor element 3. The contact area with the substrate increases and energy concentration during bonding is prevented, so that damage to the semiconductor element can be sufficiently suppressed.
In addition, although the material of the wire 5 was made from Cu, it is not restricted to this. As long as it has an appropriate electrical conductivity as an electrical wiring member, Cu-based alloy, pure Al or Al-based alloy, Au or Ag-based alloy, or a wire coated with Pd or Al with a metal such as Cu as a core Good. Further, a metal plate such as Cu used as a lead frame in DLB (Direct Lead Bonding) may be used.

接続部としての金属板４ａは、Ａｌ製（例えば、外形寸法０．５ｍｍ×１．０ｍｍ×厚さ２００ｕｍ）を用いる。金属板４ａは、ワイヤ５よりも小さいか同等の弾性係数を有することが望ましく、パワー半導体素子３の表面電極３ａとワイヤ５の一端５ａとの間に設けられ、ワイヤ５の一端５ａの接触面積を拡げるだけでなく、緩衝材として機能する。
なお、金属板４ａは、Ａｌ製に限るものではなく、この発明を用いたワイヤボンディング工程によりパワー半導体素子３にダメージを与えないのであれば、金属板４の材質はＳｉやＣｕを含有したＡｌ系の合金や、Ａｕ、Ａｇ、Ｃｕ、Ｓｎ、はんだ、これらを積層したクラッド材でもよい。さらに、電気配線用部材として適切な伝導率を持つ物質で、パワー半導体素子３にダメージを与えないための緩衝材としての役割を果たすことができるのであれば、金属フィラーを含有した樹脂などでもよい。 The metal plate 4a as the connection portion is made of Al (for example, outer dimensions 0.5 mm × 1.0 mm × thickness 200 μm). The metal plate 4a preferably has an elastic modulus smaller than or equal to that of the wire 5, and is provided between the surface electrode 3a of the power semiconductor element 3 and the one end 5a of the wire 5, and the contact area of the one end 5a of the wire 5 It not only expands, but also functions as a cushioning material.
The metal plate 4a is not limited to Al. If the power semiconductor element 3 is not damaged by the wire bonding process using the present invention, the metal plate 4 is made of Al containing Si or Cu. It may be a base alloy, Au, Ag, Cu, Sn, solder, or a clad material in which these are laminated. Furthermore, a resin having a suitable conductivity as a member for electrical wiring and a resin containing a metal filler may be used as long as it can serve as a buffer material for preventing damage to the power semiconductor element 3. .

次に、この発明の実施の形態１によるパワー半導体装置１００の製造方法について、図３及び図４に基づき説明する。図３は、この発明の実施の形態１によるパワー半導体装置１００のワイヤ５の一端５ａ下面側の接続面に金属板４ａを接合するための製造工程を示す断面図であり、図４は、ワイヤ５の一端５ａ下面側の接続面に接合した金属板４ａを接続部としてボンディングする製造工程を示す断面図である。   Next, a method for manufacturing the power semiconductor device 100 according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a cross-sectional view showing a manufacturing process for joining metal plate 4a to the connection surface on the lower surface side of one end 5a of wire 5 of power semiconductor device 100 according to the first embodiment of the present invention. 5 is a cross-sectional view showing a manufacturing process in which a metal plate 4a bonded to the connection surface on the lower surface side of one end 5a of FIG.

まず、図３（ａ）に示すように、ワイヤ５は、ワイヤボンディングヘッド８に取り付けられた一端５ａが、荷重を掛けて超音波を印加しても接合しにくい、十分に硬い材料で構成された平坦な台座７（例えば、ガラス製）上の金属板４（例えば、外形寸法１００ｍｍ×１００ｍｍ×厚さ２００ｕｍ）に押下される。金属板４は台座７に対し、真空吸着により固定されている。
なお、台座７は、ガラス製に限るものではなく、ワイヤボンディングにより金属板４と接合しにくいものであればタングステンカーバイドなどの金属や、イソダンプや、ポリイミドなどといった樹脂などを用いてもよい。
また、金属板４は、超音波を印加した時に接合部の大きさがワイヤ５の底面に接合し、ワイヤボンディングヘッド８の動作に追従してワイヤ５側に接合したまま上昇する程度に密着力が弱い膜であり、底面に平坦な面を形成できるのであれば、めっきやスパッタリングなどにより成膜した膜を利用してもよい。金属板４を台座７に固定する場合の固定方法は、端部を冶具により固定する方法や、台座７と接着材により固定する方法などでもよい。 First, as shown in FIG. 3A, the wire 5 is made of a sufficiently hard material in which one end 5a attached to the wire bonding head 8 is hard to be joined even when an ultrasonic wave is applied under a load. The metal plate 4 (for example, outer dimensions 100 mm × 100 mm × thickness 200 μm) on the flat base 7 (for example, made of glass) is pressed. The metal plate 4 is fixed to the base 7 by vacuum suction.
Note that the pedestal 7 is not limited to glass, and a metal such as tungsten carbide or a resin such as isopump or polyimide may be used as long as it is difficult to bond to the metal plate 4 by wire bonding.
Further, the metal plate 4 has an adhesive force such that when an ultrasonic wave is applied, the size of the bonded portion is bonded to the bottom surface of the wire 5 and rises while being bonded to the wire 5 side following the operation of the wire bonding head 8. As long as it is a weak film and a flat surface can be formed on the bottom surface, a film formed by plating or sputtering may be used. The method for fixing the metal plate 4 to the pedestal 7 may be a method for fixing the end portion with a jig, a method for fixing the pedestal 7 with an adhesive, or the like.

続いて、ワイヤボンディングヘッド８により押下されたワイヤ５の一端５ａは、電気配線のためのウェッジワイヤボンディングと同様に、荷重が掛けられたたまま超音波を印加され、金属板４と接合する。
この工程により、金属板４の上面はワイヤ５により変形するが、台座７が十分硬いために金属板４の下面は平坦な状態が維持される。また、このとき、超音波が印加された時の衝撃により、金属板４は、ワイヤ５との接合部の大きさに個片化される。 Subsequently, one end 5 a of the wire 5 pressed by the wire bonding head 8 is joined with the metal plate 4 by being applied with an ultrasonic wave while a load is applied, similarly to the wedge wire bonding for electric wiring.
By this step, the upper surface of the metal plate 4 is deformed by the wire 5, but since the base 7 is sufficiently hard, the lower surface of the metal plate 4 is maintained flat. At this time, the metal plate 4 is separated into pieces having the size of the joint portion with the wire 5 due to the impact when the ultrasonic wave is applied.

さらに、金属板４と台座７は接合しないため、ワイヤボンディングヘッド８が上昇するとワイヤが繰り出されることなく、ワイヤ５の一端５ａは、図３（ｃ）に示すように、個片化された金属板４ａが接合されたまま、ワイヤボンディングヘッド８の動作に追従して上昇する。   Further, since the metal plate 4 and the pedestal 7 are not joined, the wire 5 is not fed out when the wire bonding head 8 is raised, and the one end 5a of the wire 5 is separated into pieces of metal as shown in FIG. The plate 4a moves up following the operation of the wire bonding head 8 while being bonded.

次に、下面が平坦な金属板４ａが接合されたワイヤ５の一端５ａは、図４（ａ）に示すように、ワイヤボンディングヘッド８により、絶縁基板１上にダイボンドされたパワー半導体素子３の表面電極３ａ上に運搬される。   Next, one end 5a of the wire 5 to which the metal plate 4a having a flat bottom surface is bonded is connected to the power semiconductor element 3 die-bonded on the insulating substrate 1 by the wire bonding head 8, as shown in FIG. It is carried on the surface electrode 3a.

続いて、パワー半導体素子３の表面電極３ａ上に運搬されたワイヤ５の一端５ａは、図４（ｂ）に示すように、ワイヤボンディングヘッド８によりパワー半導体素子３の表面電極３ａ上に押下され、荷重が掛けられたたまま超音波を印加され、金属板４ａとともに表面電極３ａにウェッジワイヤボンディングされる。   Subsequently, one end 5a of the wire 5 conveyed onto the surface electrode 3a of the power semiconductor element 3 is pressed onto the surface electrode 3a of the power semiconductor element 3 by the wire bonding head 8, as shown in FIG. Then, an ultrasonic wave is applied while a load is applied, and wedge wire bonding is performed to the surface electrode 3a together with the metal plate 4a.

このとき、ワイヤ５の一端５ａ下面側の接続面には、金属板４ａが接合され、接続部としての金属板４ａの下面は平坦な状態になっているため、広い接触面積が得られる。そのため、荷重や超音波を印加した時のエネルギーを分散させることができるため、素子へのダメージを抑制でき、図４（ｃ）に示すように、接合を完了させることができる。
また、金属板４ａは、緩衝材として機能し、変形がパワー半導体素子３まで到達しないため、パワー半導体素子３にダメージを与えることなくワイヤ５をボンディングすることが可能となる。
さらに、予めワイヤ５の一端５ａ下面側の接続面に金属板４ａを接合しておくことから、ボンディング時に金属板がずれることを防ぐことで、ボンディング位置を正確に制御でき、接合不良を抑制できる。
また、金属板４ａとパワー半導体素子３間に隙間を形成しないので、特許文献２のように未接合で封止樹脂を充填できない部分が生じないため、絶縁不良を抑制できる。 At this time, the metal plate 4a is joined to the connection surface on the lower surface side of the one end 5a of the wire 5, and the lower surface of the metal plate 4a as the connection portion is flat, so that a wide contact area is obtained. Therefore, since energy when a load or an ultrasonic wave is applied can be dispersed, damage to the element can be suppressed, and bonding can be completed as shown in FIG.
Further, the metal plate 4a functions as a buffer material, and the deformation does not reach the power semiconductor element 3, so that the wire 5 can be bonded without damaging the power semiconductor element 3.
Furthermore, since the metal plate 4a is bonded to the connection surface on the lower surface side of the end 5a of the wire 5 in advance, the bonding position can be accurately controlled by preventing the metal plate from being displaced during bonding, and bonding failure can be suppressed. .
In addition, since no gap is formed between the metal plate 4a and the power semiconductor element 3, there is no portion that is not joined and cannot be filled with the sealing resin as in Patent Document 2, so that insulation failure can be suppressed.

その後、ワイヤを繰り出しながら絶縁基板１のパターン１ｂにワイヤボンディングヘッド８が移動し、ワイヤ５の他端５ｂが、絶縁基板１のパターン１ｂに対しボンディングされることで電気配線される。最後に、これらの部材は封止樹脂（図示なし）により、絶縁封止され、この発明の実施の形態１によるパワー半導体装置１００が得られる。
絶縁封止には、二液性ポッティング樹脂等の封止樹脂による封止や、トランスファーモールド、ゲルによる封止などが用いられる。 Thereafter, the wire bonding head 8 moves to the pattern 1b of the insulating substrate 1 while feeding the wire, and the other end 5b of the wire 5 is bonded to the pattern 1b of the insulating substrate 1 to be electrically wired. Finally, these members are insulated and sealed with a sealing resin (not shown), and the power semiconductor device 100 according to the first embodiment of the present invention is obtained.
For insulation sealing, sealing with a sealing resin such as a two-component potting resin, transfer molding, sealing with a gel, or the like is used.

以上のように、この発明の実施の形態１におけるパワー半導体装置１００では、ワイヤ５の一端５ａ下面側に、予め金属板４ａを超音波接合し、パワー半導体素子３の表面の形状に対応する、下面が平坦な金属板４ａを接続部としてパワー半導体素子３の表面電極３ａにボンディングするようにしたので、Ｃｕワイヤを用いたワイヤボンディング時でも、半導体素子との接触面積を拡げることで、ボンディングの際のエネルギー集中を防ぎ、半導体素子へのダメージを十分に抑制することができる。
また、予め金属板４ａを接合しておくことから、ボンディング時に金属板がずれることを防ぐことで、ボンディング位置を正確に制御でき、接合不良を抑制できる。
また、ワイヤの接続に必要な面積の金属板が個別に追従するため、ワイヤボンディング後に余分な金属板を取り除く工程が不要で、ワイヤボンディング部に余計なダメージを与えず、絶縁不良を抑制できる。 As described above, in the power semiconductor device 100 according to the first embodiment of the present invention, the metal plate 4a is ultrasonically bonded in advance to the lower surface side of the end 5a of the wire 5 to correspond to the shape of the surface of the power semiconductor element 3. Since the metal plate 4a having a flat bottom surface is used as a connection portion and bonded to the surface electrode 3a of the power semiconductor element 3, the bonding area of the semiconductor element can be increased by expanding the contact area with the semiconductor element even during wire bonding using a Cu wire. Energy concentration at the time can be prevented, and damage to the semiconductor element can be sufficiently suppressed.
In addition, since the metal plate 4a is bonded in advance, by preventing the metal plate from being displaced during bonding, the bonding position can be accurately controlled and bonding failure can be suppressed.
In addition, since the metal plates having the area necessary for wire connection follow individually, there is no need to remove the extra metal plate after the wire bonding, and the wire bonding portion is not damaged excessively and insulation failure can be suppressed.

また、金属板４ａは、超音波が印加された時の衝撃により、ワイヤ５との接合部の大きさに個片化される場合について説明したが、これに限るものではない。図５（ａ）に示すように、金属板４に予め切れ目４ａｂを形成しておき、超音波の印加の衝撃で接合部の大きさ程度に個片化しやすくしてもよい。切れ目４ａｂの作製方法は、機械的に切削により加工するか、写真製版により切れ絵を形成してもよい。このエッチングは、エッチング液に浸漬するウエットエッチングでも、プラズマなどを利用するドライエッチングでもよい。
この場合も、超音波を印加した時の衝撃及び切れ目を形成した効果と、ワイヤボンディングヘッド８が上昇するときに生じる応力とで、より確実に個片化できる。 Moreover, although the metal plate 4a demonstrated the case where it isolate | separates into the magnitude | size of a junction part with the wire 5 by the impact at the time of an ultrasonic wave being applied, it does not restrict to this. As shown in FIG. 5A, a cut 4ab may be formed in advance on the metal plate 4 so that it can be easily singulated to the size of the joint by the impact of application of ultrasonic waves. The cut line 4ab may be produced by mechanically processing by cutting or forming a cut picture by photolithography. This etching may be wet etching immersed in an etching solution or dry etching using plasma or the like.
Also in this case, it is possible to divide more reliably by the effect of forming an impact and a cut when applying ultrasonic waves and the stress generated when the wire bonding head 8 is raised.

また、図５（ｂ）および（ｃ）に示すように、予め個片化した金属板４ａを使用してもよい。この場合、シャーカットにより個片化され、シャーカットに使用した刃を金属板４ａから離さず、ワイヤ５との接合を開始することにより、個片化した金属板４ａの移動を防ぐことができるため、位置ずれを抑制することが可能となる。
このとき、個片化した金属板４ａをそれぞれ真空吸着により固定することが望ましいが、位置ずれせず、ワイヤ５と金属板４ａを接合することができるよう刃の高さを調整するならば、必ずしも固定する必要はない。 Further, as shown in FIGS. 5B and 5C, a metal plate 4a separated in advance may be used. In this case, movement of the separated metal plate 4a can be prevented by starting the joining with the wire 5 without separating the blade used for the shear cut from the metal plate 4a without separating the blade used for the shear cut. Therefore, it is possible to suppress positional deviation.
At this time, it is desirable to fix the separated metal plate 4a by vacuum suction, but if the height of the blade is adjusted so that the wire 5 and the metal plate 4a can be joined without being displaced, It is not necessarily fixed.

また、予め金属板４ａを個片化する方法として、ダイシングシートに金属板４ａを張付け、ダイサーによりカットし、ダイシングシートごと個片化した金属板４ａを台座７に固定してもよい。シャーカットで使用するような刃を押し付け、完全に切断せずに切れ目を形成しつつ、金属板４ａを固定するといった方法によりワイヤ５との接合を行ってもよい。いずれの場合も、切れ目の形状は長方形や楕円形でもよい。また、切れ目の溝はミシン目状やＶ字型、Ｕ字型いずれの状態でもよい。   In addition, as a method of dividing the metal plate 4 a into pieces, the metal plate 4 a may be attached to the dicing sheet, cut with a dicer, and the metal plate 4 a separated into pieces together with the dicing sheet may be fixed to the base 7. You may join with the wire 5 by the method of fixing the metal plate 4a, pressing the blade which is used by shear cutting, and forming a cut, without cutting completely. In any case, the cut shape may be a rectangle or an ellipse. Further, the cut groove may be perforated, V-shaped, or U-shaped.

また、この工程により運搬、接合され、パワー半導体素子３にダメージを与えなければ、金属板４ａは、２枚以上としてもよい。また、複数の金属板４ａを一度にまとめて接合しても、別々に接合するような工程としてもよい。   In addition, two or more metal plates 4a may be used as long as they are transported and bonded by this process and do not damage the power semiconductor element 3. Moreover, it is good also as a process of joining the several metal plate 4a collectively, or joining separately.

さらに、従来のＡｌワイヤボンディングを行う場合でも、この発明を利用すると、半導体素子の電極を薄くすることが可能となり、半導体素子の製造コストを低減することが可能となる。   Furthermore, even when conventional Al wire bonding is performed, if the present invention is used, the electrode of the semiconductor element can be made thin, and the manufacturing cost of the semiconductor element can be reduced.

なお、実施の形態１では、均一な板厚の金属板４を用いてワイヤの接続面に接合する方法を説明したが、金属板の板厚を変化させてもよい。例えば、図６および図７に示すように、中央部を厚くした金属板４１ａを用いることで、ワイヤボンディングにより中央の厚さが縮小し、ボンディング後の断面を観察した場合、厚さが均一になるようにすることで、底面にフラットな面を形成しやすくなる。   In the first embodiment, the method of bonding to the connection surface of the wire using the metal plate 4 having a uniform plate thickness has been described. However, the plate thickness of the metal plate may be changed. For example, as shown in FIGS. 6 and 7, by using a metal plate 41a having a thick central portion, the central thickness is reduced by wire bonding, and when the cross section after bonding is observed, the thickness is uniform. By doing so, it becomes easy to form a flat surface on the bottom surface.

実施の形態２．
実施の形態１では、ファーストボンディングを行う場合に、ワイヤ５の一端５ａに予め金属板４ａを接合する方法を説明したが、実施の形態２では、ステッチボンディングやセカンドボンディングを行う場合について説明する。 Embodiment 2. FIG.
In the first embodiment, the method of previously joining the metal plate 4a to the one end 5a of the wire 5 when performing the first bonding has been described, but in the second embodiment, the case of performing the stitch bonding or the second bonding will be described.

図８は、この発明の実施の形態２によるパワー半導体装置２００の構成および製造方法を示す外観模式図である。パワー半導体装置２００では、パワー半導体素子３を効率よく配置するために、ワイヤ５１の中間部５１ｃで、ステッチボンディングやセカンドボンディングを行う。この発明の実施の形態２によるパワー半導体装置２００においては、ステッチボンディングやセカンドボンディングを行う方法として、図８に示すような可動式の台座７１を用いる。   FIG. 8 is a schematic external view showing the configuration and manufacturing method of power semiconductor device 200 according to the second embodiment of the present invention. In the power semiconductor device 200, stitch bonding and second bonding are performed at the intermediate portion 51 c of the wire 51 in order to efficiently arrange the power semiconductor elements 3. In the power semiconductor device 200 according to the second embodiment of the present invention, a movable base 71 as shown in FIG. 8 is used as a method for performing stitch bonding or second bonding.

ワイヤ５１の一端５１ａがすでにボンディングされている場合、ワイヤ５１の中間部５１ｃに、実施の形態１のように金属板で接続部を形成する際に、台座がボンディング位置から離れているとワイヤ５１のループが変則的になり、すでに配線したワイヤと干渉することが懸念される。
そこで、台座７１を可動式の台座とし、ワイヤ５１の中間部５１ｃをボンディングするパワー半導体素子３の表面電極３ａの真上１〜２ｍｍの近接する位置に、金属板４が載置されている台座７１を移動させ、その位置でワイヤボンディングヘッド８によりワイヤ５１の中間部５１ｃを台座７１に押下することで、ワイヤ５１の中間部５１ｃ下面側の接続面に金属板４を接合することを可能とした。
ワイヤボンディングヘッド８により押下されたワイヤ５１の中間部５１ｃは、荷重が掛けられたたまま超音波を印加され、中間部５１ｃ下面側の接続面は金属板４と接合する。ワイヤ５１の中間部５１ｃは、金属板４が接合されたまま、ワイヤボンディングヘッド８の動作に追従して上昇し、金属板４が個片化される。その後、台座７１をボンディングに影響のない位置に退避させ、中間部５１ｃ下面側の接続面に接合された金属板４ａを接続部として、パワー半導体素子３の表面電極３ａとボンディングさせることができる。
このように、ステッチボンディングやセカンドボンディングをする場合においても、可動式の台座７１を用い、ワイヤ５１の中間部５１ｃ下面側の接続面に金属板４ａを接合することができ、接続部としての金属板４ａの下面は平坦な状態になっているため、半導体素子との接触面積を拡げることができ、ボンディングの際のエネルギー集中を防ぎ、半導体素子へのダメージを十分に抑制することができる。
パワー半導体装置２００のその他の構成および製造工程については、図１から図４に示す実施の形態１のパワー半導体装置１００と同様であり、同一の部分には同一の符号を付して、その説明を省略する。 When one end 51a of the wire 51 is already bonded, when the connecting portion is formed on the intermediate portion 51c of the wire 51 with a metal plate as in the first embodiment, if the pedestal is away from the bonding position, the wire 51 There is a concern that the loop may become irregular and interfere with already wired wires.
Therefore, the pedestal 71 is a movable pedestal, and the pedestal on which the metal plate 4 is placed at a position close to 1 to 2 mm directly above the surface electrode 3a of the power semiconductor element 3 to which the intermediate portion 51c of the wire 51 is bonded. It is possible to join the metal plate 4 to the connection surface on the lower surface side of the intermediate portion 51c of the wire 51 by moving the 71 and pressing the intermediate portion 51c of the wire 51 against the base 71 by the wire bonding head 8 at that position. did.
The intermediate portion 51 c of the wire 51 pressed by the wire bonding head 8 is applied with an ultrasonic wave while a load is applied, and the connection surface on the lower surface side of the intermediate portion 51 c is joined to the metal plate 4. The intermediate portion 51c of the wire 51 rises following the operation of the wire bonding head 8 while the metal plate 4 is bonded, and the metal plate 4 is separated into pieces. Thereafter, the pedestal 71 can be retracted to a position that does not affect the bonding, and the metal plate 4a bonded to the connection surface on the lower surface side of the intermediate portion 51c can be bonded to the surface electrode 3a of the power semiconductor element 3 as a connection portion.
As described above, even in the case of stitch bonding or second bonding, the metal plate 4a can be bonded to the connection surface on the lower surface side of the intermediate portion 51c of the wire 51 using the movable base 71, and the metal as the connection portion Since the lower surface of the plate 4a is flat, the contact area with the semiconductor element can be increased, energy concentration during bonding can be prevented, and damage to the semiconductor element can be sufficiently suppressed.
The other configuration and manufacturing process of power semiconductor device 200 are the same as those of power semiconductor device 100 of the first embodiment shown in FIGS. 1 to 4, and the same parts are denoted by the same reference numerals and the description thereof is omitted. Is omitted.

以上のように、この発明の実施の形態２におけるパワー半導体装置２００では、可動式の台座７１を用いて、ワイヤ５１の中間部５１ｃをボンディングするパワー半導体素子３の表面電極３ａの真上の位置で、中間部５１ｃ下面側の接続面に、予め金属板４ａを超音波接合し、パワー半導体素子３の表面の形状に対応する、下面が平坦な金属板４ａを接続部としてパワー半導体素子３の表面電極３ａにボンディングするようにしたので、ステッチボンディングやセカンドボンディングを行う場合であっても、ワイヤのループが変則的になったり、すでに配線したワイヤと干渉することなく、容易にワイヤの接続面に金属板を接合でき、Ｃｕワイヤを用いたワイヤボンディング時でも、半導体素子との接触面積を拡げることで、ボンディングの際のエネルギー集中を防ぎ、半導体素子へのダメージを十分に抑制することができる。
また、予め中間部５１ｃ下面側の接続面に金属板４ａを接合しておくことから、ボンディング時に金属板がずれることを防ぐことで、ボンディング位置を正確に制御でき、接合不良を抑制できる。
また、ワイヤの接続に必要な面積の金属板が個別に追従するため、ワイヤボンディング後に余分な金属板を取り除く工程が不要で、ワイヤボンディング部に余計なダメージを与えず、絶縁不良を抑制できる。 As described above, in the power semiconductor device 200 according to the second embodiment of the present invention, the position directly above the surface electrode 3a of the power semiconductor element 3 for bonding the intermediate portion 51c of the wire 51 using the movable base 71. Then, the metal plate 4a is ultrasonically bonded in advance to the connection surface on the lower surface side of the intermediate portion 51c, and the metal plate 4a having a flat lower surface corresponding to the shape of the surface of the power semiconductor element 3 is used as the connection portion. Since bonding is performed on the surface electrode 3a, even when stitch bonding or second bonding is performed, the wire loop can be easily connected without irregularities in the wire loop or interference with the already wired wire. A metal plate can be bonded to the substrate, and even during wire bonding using Cu wire, by expanding the contact area with the semiconductor element, Of preventing energy concentration, it is possible to sufficiently suppress damage to the semiconductor element.
Further, since the metal plate 4a is bonded to the connection surface on the lower surface side of the intermediate portion 51c in advance, the bonding position can be accurately controlled by preventing the metal plate from shifting during bonding, and bonding failure can be suppressed.
In addition, since the metal plates having the area necessary for wire connection follow individually, there is no need to remove the extra metal plate after the wire bonding, and the wire bonding portion is not damaged excessively and insulation failure can be suppressed.

なお、この実施の形態２においては、台座７１が可動式としたが、絶縁基板１および絶縁基板１に配置された各種部材とワイヤボンディングヘッド８が移動しても、同様の効果を得ることができる。   Although the pedestal 71 is movable in the second embodiment, the same effect can be obtained even if the wire bonding head 8 and the various members arranged on the insulating substrate 1 and the insulating substrate 1 move. it can.

また、この実施の形態２における製造方法でパワー半導体素子上でのステッチボンディングやセカンドボンディングを行う場合のファーストボンディングは、必ずしもこの発明によるパワー半導体素子上のボンディングである必要はない。例えば、ファーストボンディングは絶縁基板上のボンディングでもよい。   Further, the first bonding in the case where the stitch bonding or the second bonding is performed on the power semiconductor element by the manufacturing method in the second embodiment does not necessarily need to be the bonding on the power semiconductor element according to the present invention. For example, the first bonding may be bonding on an insulating substrate.

なお、この発明の実施の形態においては、ワイヤボンディングの方法はウェッジボンディングとしたがこれに限るものではなく、ボールボンドでもよい。したがって、ワイヤ５の線形はφ４００ｕｍとしたが、ワイヤ５が破断することなく金属板を持ち上げることが可能であればボールボンディングで用いられるようなφ１０〜８０ｕｍのワイヤや、ウェッジボンディングで用いられるφ８０〜５００ｕｍのワイヤでもよい。   In the embodiment of the present invention, the wire bonding method is wedge bonding, but the method is not limited to this, and ball bonding may be used. Therefore, although the wire 5 has a linear shape of φ400 μm, if the metal plate can be lifted without breaking the wire 5, a wire of φ10 to 80 μm used for ball bonding, or φ80 to used for wedge bonding. A 500 um wire may be used.

また、上述した実施の形態１および実施の形態２におけるパワー半導体装置を構成するパワー半導体素子３としては、珪素（Ｓｉ）によって形成されたものには限定されず、珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体によって形成してもよい。ワイドバンドギャップ半導体としては、例えば、炭化珪素（ＳｉＣ）、窒化ガリウム（ＧａＮ）、ダイヤモンドなどが挙げられことは、すでに述べたとおりである。   Further, power semiconductor element 3 constituting the power semiconductor device in the first and second embodiments described above is not limited to one formed of silicon (Si), and has a larger band gap than silicon. You may form with a wide band gap semiconductor. As described above, examples of the wide band gap semiconductor include silicon carbide (SiC), gallium nitride (GaN), and diamond.

このようなワイドバンドギャップ半導体によって形成されたパワー半導体素子は、耐電圧性が高く、許容電流密度も高い。また、耐熱性も高いため、放熱部材の冷却フィンの小型化や、空冷化が可能であるので、パワー半導体装置の一層の小型化が可能になる。   A power semiconductor element formed of such a wide band gap semiconductor has high voltage resistance and high allowable current density. Further, since the heat resistance is high, the cooling fins of the heat dissipating member can be downsized and air cooled, so that the power semiconductor device can be further downsized.

パワー半導体装置の小型化が進むと、放熱性を確保し、熱応力に対する長期信頼性への要求がさらに高度になる。このような要求に対しても、この発明のパワー半導体装置は、優れた効果を発揮する。   As miniaturization of power semiconductor devices progresses, the requirement for long-term reliability against thermal stress is further increased with ensuring heat dissipation. The power semiconductor device of the present invention exhibits excellent effects even in response to such demands.

なお、この発明は、発明の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略することが可能である。   It should be noted that within the scope of the invention, the embodiments can be freely combined, or the embodiments can be appropriately modified or omitted.

１ 絶縁基板、３ パワー半導体素子、３ａ 表側電極、４、４ａ 金属板、５ ワイヤ、７ 台座、８ ワイヤボンディングヘッド、４１ａ 金属板、５１ ワイヤ、７１ 台座、１００、２００、３００ パワー半導体装置   DESCRIPTION OF SYMBOLS 1 Insulation board | substrate, 3 Power semiconductor element, 3a Front side electrode 4, 4a Metal plate, 5 wire, 7 base, 8 Wire bonding head, 41a Metal plate, 51 wire, 71 base, 100, 200, 300 Power semiconductor device

Claims (8)

ワイヤの接続面に金属板を接合して、パワー半導体素子の表面形状に応じた平坦な形状部を有する接続部を形成する工程と、
前記ワイヤの接続面に形成された接続部を、前記パワー半導体素子の表面電極にボンディングする工程と
を含むことを特徴とするパワー半導体装置の製造方法。 Bonding a metal plate to the connection surface of the wire to form a connection portion having a flat shape portion corresponding to the surface shape of the power semiconductor element;
Bonding the connection portion formed on the connection surface of the wire to the surface electrode of the power semiconductor element. 前記接続部を形成する工程は、ワイヤボンディングヘッドで前記ワイヤを前記金属板を載置した台座に押下した状態で、超音波接合して形成することを特徴とする請求項１に記載のパワー半導体装置の製造方法。   2. The power semiconductor according to claim 1, wherein the connecting portion is formed by ultrasonic bonding in a state where the wire is pressed onto a pedestal on which the metal plate is placed by a wire bonding head. Device manufacturing method. 前記台座は、前記金属板と超音波接合されない材料で構成されていることを特徴とする請求項２に記載のパワー半導体装置の製造方法。   The method for manufacturing a power semiconductor device according to claim 2, wherein the base is made of a material that is not ultrasonically bonded to the metal plate. 前記台座は、前記接続部を形成する工程でのみ、前記パワー半導体素子の表面電極の上に近接して配置することを特徴とする請求項３に記載のパワー半導体装置の製造方法。   4. The method of manufacturing a power semiconductor device according to claim 3, wherein the pedestal is disposed close to the surface electrode of the power semiconductor element only in the step of forming the connection portion. 5. 前記金属板は、前記ワイヤよりも小さい弾性係数、または、同等の弾性係数を有することを特徴とする請求項１から請求項４のいずれか１項に記載のパワー半導体装置の製造方法。   5. The method of manufacturing a power semiconductor device according to claim 1, wherein the metal plate has an elastic coefficient smaller than or equivalent to that of the wire. 6. 前記ワイヤは、Ｃｕ製であり、前記金属板は、Ａｌ製であることを特徴とする請求項５に記載のパワー半導体装置の製造方法。   The method of manufacturing a power semiconductor device according to claim 5, wherein the wire is made of Cu, and the metal plate is made of Al. 前記パワー半導体素子は、ワイドバンドギャップ半導体であることを特徴とする請求項１から請求項６のいずれか１項に記載のパワー半導体装置の製造方法。   The method of manufacturing a power semiconductor device according to claim 1, wherein the power semiconductor element is a wide band gap semiconductor. 前記ワイドバンドギャップ半導体は、炭化ケイ素、窒化ガリウム系材料または、ダイヤモンドを用いた半導体であることを特徴とする請求項７に記載のパワー半導体装置の製造方法。
8. The method of manufacturing a power semiconductor device according to claim 7, wherein the wide band gap semiconductor is a semiconductor using silicon carbide, a gallium nitride-based material, or diamond.
JP2014215928A 2014-10-23 2014-10-23 Manufacturing method of power semiconductor device Pending JP2016086003A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110100314A (en) * 2017-06-09 2019-08-06 富士电机株式会社 The manufacturing method of semiconductor device and semiconductor device
JP2019135761A (en) * 2018-02-05 2019-08-15 株式会社東芝 Semiconductor module and method for manufacturing the same
JP7412998B2 (en) 2019-12-12 2024-01-15 ローム株式会社 Semiconductor device and semiconductor device manufacturing method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110100314A (en) * 2017-06-09 2019-08-06 富士电机株式会社 The manufacturing method of semiconductor device and semiconductor device
CN110100314B (en) * 2017-06-09 2022-08-09 富士电机株式会社 Semiconductor device and method for manufacturing semiconductor device
JP2019135761A (en) * 2018-02-05 2019-08-15 株式会社東芝 Semiconductor module and method for manufacturing the same
JP7412998B2 (en) 2019-12-12 2024-01-15 ローム株式会社 Semiconductor device and semiconductor device manufacturing method

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