JP5774292B2 - 回路装置およびその製造方法 - Google Patents
回路装置およびその製造方法 Download PDFInfo
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- JP5774292B2 JP5774292B2 JP2010247063A JP2010247063A JP5774292B2 JP 5774292 B2 JP5774292 B2 JP 5774292B2 JP 2010247063 A JP2010247063 A JP 2010247063A JP 2010247063 A JP2010247063 A JP 2010247063A JP 5774292 B2 JP5774292 B2 JP 5774292B2
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- Prior art keywords
- solder
- pad
- alloy layer
- circuit device
- manufacturing
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- 238000004519 manufacturing process Methods 0.000 title claims description 27
- 229910000679 solder Inorganic materials 0.000 claims description 228
- 229910045601 alloy Inorganic materials 0.000 claims description 80
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- 238000000034 method Methods 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 229910000765 intermetallic Inorganic materials 0.000 claims description 7
- 239000011159 matrix material Substances 0.000 claims description 7
- 230000008018 melting Effects 0.000 claims description 6
- 238000002844 melting Methods 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
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- 229910052802 copper Inorganic materials 0.000 description 13
- 238000007789 sealing Methods 0.000 description 13
- 229910000881 Cu alloy Inorganic materials 0.000 description 10
- 229910001128 Sn alloy Inorganic materials 0.000 description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 9
- 230000004907 flux Effects 0.000 description 8
- 239000000203 mixture Substances 0.000 description 5
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
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- 238000007650 screen-printing Methods 0.000 description 4
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000000843 powder Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
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- 230000005496 eutectics Effects 0.000 description 2
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- 230000002093 peripheral effect Effects 0.000 description 2
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- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910017482 Cu 6 Sn 5 Inorganic materials 0.000 description 1
- 239000010407 anodic oxide Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
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- 239000000945 filler Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Description
本実施の形態では、図1を参照して、本発明の回路装置の一例として混成集積回路装置10の構成を説明する。図1(A)は混成集積回路装置10の斜視図であり、図1(B)はその断面図である。図1(C)はトランジスタ14A(回路素子)が固着される構造を示す断面図である。
本実施の形態では、図2から図7を参照して、上記した混成集積回路装置10の製造方法を説明する。
本工程では、基板16の表面に導電パターン18を形成する。図2(A)は本工程での基板16の平面図であり、図2(B)はその断面図である。
本工程では、パッド18A〜18Dの上面に半田ペースト21Aを塗布する。
次に、パワートランジスタ以外の素子(小信号系トランジスタおよびチップ部品)の電気的接続を行い、パッド18Aの上面に離散的に半田19を形成する。
図6を参照して、次に、トランジスタ14Aが固着されたヒートシンク14Dを、パッド18Aの上面に固着する。
本工程では、リード11の固着および封止樹脂12の形成を行う。
11 リード
12 封止樹脂
14A トランジスタ
14B チップ部品
14C トランジスタ
14D ヒートシンク
15A 太線
15B 細線
16 基板
17 絶縁層
18 パターン
18A パッド
18B パッド
18C パッド
18D パッド
18E パッド
18F 配線パターン
19 半田
21 半田ペースト
21A 半田ペースト
22 合金層
23 合金層
30 シリンジ
31 半田ペースト
Claims (11)
- 主面を有する基板と、
前記基板の前記主面に形成され、主面を有する絶縁層と、
前記絶縁層の前記主面に形成された導電パターンを有し、第1金属から成り少なくとも1つのパッドを形成する金属膜と、
少なくとも一つの前記パッドに半田を介して固着された回路素子と、を具備し、
前記半田と前記パッドとの境界には、前記半田を構成する金属と前記第1金属とを含む金属間化合物から成る合金層が形成され、
前記合金層は、第1合金層と、前記第1合金層よりも薄い第2合金層を有し、
前記第1合金層は、互いに離間してマトリックス状に配置されることを特徴とする回路装置。 - 前記第2合金層は、前記第1合金層の間に格子状に形成されることを特徴とする請求項1に記載の回路装置。
- 前記回路素子は、その上面に半導体素子が固着されたヒートシンクであることを特徴とする請求項1または請求項2に記載の回路装置。
- 主面を有する基板と、前記基板の前記主面に形成された絶縁層と、前記絶縁層の主面に形成されて第1金属から成るパッドと、を用意し、前記パッドの上面に複数の第1半田ペーストを互いに離間して形成する工程と、
リフローにより第1半田ペーストを溶融させて第1半田構造を形成する工程と、
前記第1半田構造および前記パッドの上面が覆われるように第2半田ペーストを塗布する工程と、
前記第2半田ペーストの上面に回路素子を載置して加熱することにより、前記回路素子を前記パッドに固着する工程と、を具備し、
前記固着する工程では、複数の第2半田構造を形成し、前記第1半田構造と前記第2半田構造と前記パッドとの間に合金層を生成し、前記合金層は第1半田構造と第2半田構造と前記パッドの前記第1金属とを含む化合物を有し、前記合金層は第1合金層と第2合金層を有し、前記第2合金層は前記第1合金層よりも薄く、前記第1合金層は互いに離間してマトリックス状に配置されることを特徴とする回路装置の製造方法。 - 前記第1半田構造は前記パッドの上面に直に形成され、前記第2半田ペーストは前記第1半田構造の表面および前記パッドの上面に塗布されることを特徴とする請求項4に記載の回路装置の製造方法。
- 前記第1半田ペーストを、前記パッドの上面にマトリックス状に配置することを特徴とする請求項4または請求項5に記載の回路装置の製造方法。
- 前記第1半田構造と前記パッドとの境界部分には第1合金層が生成され、
前記第2半田ペーストを溶融することにより形成された第2半田構造と前記パッドとの境界部分には第2合金層が生成され、
前記第2合金層は、前記第1合金層よりも薄いことを特徴とする請求項4から請求項6の何れかに記載の回路装置の製造方法。 - 前記第1半田構造は平面視で、一辺の長さが3mm以下の四角形状に形成されることを特徴とする請求項4から請求項7の何れかに記載の回路装置の製造方法。
- 前記第1半田構造を形成する工程では、チップ素子または小信号トランジスタを、半田を介して前記基板の上面に固着することを特徴とする請求項4から請求項8の何れかに記載の回路装置の製造方法。
- 前記回路素子は、上面にトランジスタが固着されたヒートシンクであることを特徴とする請求項4から請求項9の何れかに記載の回路装置の製造方法。
- 前記第2合金層同士の間に、前記第1合金層をグリッド状に形成する工程、を更に具備することを特徴とする請求項4から請求項10の何れかに記載の回路装置の製造方法。
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JP2010247063A JP5774292B2 (ja) | 2010-11-04 | 2010-11-04 | 回路装置およびその製造方法 |
KR1020137011495A KR20130060361A (ko) | 2010-11-04 | 2011-10-12 | 회로 장치 및 그 제조 방법 |
US13/882,952 US9572294B2 (en) | 2010-11-04 | 2011-10-12 | Circuit device and method for manufacturing same |
CN201180053072.7A CN103201829B (zh) | 2010-11-04 | 2011-10-12 | 电路装置及其制造方法 |
PCT/JP2011/005716 WO2012060054A1 (ja) | 2010-11-04 | 2011-10-12 | 回路装置およびその製造方法 |
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JP4812429B2 (ja) | 2005-01-31 | 2011-11-09 | 三洋電機株式会社 | 回路装置の製造方法 |
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JP2007059485A (ja) * | 2005-08-22 | 2007-03-08 | Rohm Co Ltd | 半導体装置、基板及び半導体装置の製造方法 |
US20090085207A1 (en) * | 2007-09-28 | 2009-04-02 | Texas Instruments, Inc. | Ball grid array substrate package and solder pad |
US20090218124A1 (en) * | 2008-02-28 | 2009-09-03 | Motorola, Inc. | Method of filling vias with fusible metal |
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US9572294B2 (en) | 2017-02-14 |
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CN103201829B (zh) | 2016-08-10 |
KR20130060361A (ko) | 2013-06-07 |
US20130286594A1 (en) | 2013-10-31 |
WO2012060054A1 (ja) | 2012-05-10 |
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