JP5740820B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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Description
図1は、実施の形態1にかかる逆阻止型IGBTの耐圧構造部を示す断面図である。図1に示すように、逆阻止型IGBTの耐圧構造部は、n型ドリフト領域1(第3半導体領域)となるn型の基板のおもて面(第1主面)に設けられ、活性領域(図示省略)を囲む。基板のおもて面の面方位は、{100}面であってもよい。耐圧構造部において、n型ドリフト領域1のおもて面の表面層には、フローティングのp型領域であるフィールドリミッティングリング(FLR)2が複数設けられている。素子端部側に、FLR2と離れて、p型のチャネルストッパー3が設けられている。
図2は、実施の形態2にかかる逆阻止型IGBTの耐圧構造部を示す断面図である。実施の形態1において、へき開面21よりも活性領域(おもて面素子構造)側のp+型分離層11の不純物量を、n型ドリフト領域1からp+型分離層11内に伸びる空乏層がへき開面21に到達しない不純物量としてもよい。pn接合面がへき開面21とほぼ平行になるように、p+型分離層11が設けられていてもよい。
図3は、実施の形態3にかかる逆阻止型IGBTの耐圧構造部を示す断面図である。実施の形態1または実施の形態2において、異方性ウェットエッチングによって出現しやすい面を含むように、p+型分離層11を設けてもよい。
図5は、実施の形態4にかかるダイシングの要部を示す断面図である。図5には、ウェハ40のダイシングライン41の一部を示す(以下、図6,7においても同様)。ここでは、実施の形態1にかかる逆阻止型IGBT(図1参照)が複数形成されたウェハ40を例に、ウェハ40をダイシングする方法について説明する。図5に示すように、まず、n型ドリフト領域1となるn型のウェハ40のおもて面(第1主面)に例えばボロン(B)を導入し、熱拡散することによって、p+型分離層11を形成する(第1半導体領域工程)。p+型分離層11は、実施の形態1と同様に、後の工程で形成される凹部6の底面と側壁との境界を一辺とするへき開面を含むように形成されてもよい。n型ドリフト領域1の厚さt1は、例えば185μmであってもよい。p+型分離層11の拡散深さは、例えば75μmであってもよい。
図6は、実施の形態5にかかるダイシングの要部を示す断面図である。実施の形態4において、ダイシングブレード44に代えて、ウェハ40の表面に第1レーザ50を照射し、ウェハ40の表面層からウェハ40を例えば溶融または蒸散させることで、ウェハ40の表面層からウェハ40を除去してもよい。
図7は、実施の形態6にかかるダイシングの要部を示す断面図である。実施の形態4において、ダイシングブレード44に代えて、ウェハ40の内部にレーザ60を照射して、ウェハ40内部の所望の領域を改質することで、改質した領域から上のウェハ40を除去してもよい。
図8および図9は、実施の形態7にかかる凹部形成に用いるマスクの形成方法を示す断面図である。凹部形成に用いるマスクは、例えば、実施の形態1にかかる逆阻止型IGBTに凹部(図1参照)を形成するために用いる。ここでは、例えば実施の形態4の凹部形成工程における凹部の形成方法について説明する。まず、図8に示すように、ウェハ40の裏面(第2主面)の表面に、レジスト70を塗布する。ウェハ40のおもて面には、実施の形態4と同様に、例えば予めおもて面素子構造が形成されていてもよい。ついで、図9に示すように、露光および現像によってレジスト70をパターニングし、ウェハ40の凹部が形成される領域を露出する。これにより、凹部が形成される領域が露出した開口部73を有するレジストマスク71が完成する(マスク形成工程)。ついで、レジストマスク71をマスクとして、エッチングによって、ウェハ40に凹部を形成する。このとき、例えばアルカリエッチング液を用いて、異方性ウェットエッチングを行ってもよい。アルカリエッチング液には、例えばテトラメチルハイドロオキサイド(TMAH)、二硫酸アンモニウムおよびシリコンが含まれていてもよい。
図13は、実施の形態8にかかる凹部形成に用いるマスクのパターン形状を示す平面図である。また、図14は、凹部形成後の補償パターン近傍の凹部形状を示す鳥瞰図である。図14では、補償パターン74を有するレジストマスク71をマスクとして、ウェハ40に凹部(側壁のみを図示)を形成している。実施の形態7において、円形状を有する補償パターン74としてもよい。
図15〜図18は、凹部コーナー部の形状を表面方向から観察した電子顕微鏡写真である。まず、実施の形態7に従い、凹部を形成した試料を作製した(以下、第1実施例91とする:図15)。第1実施例91では、補償パターン幅を、上記(3)式を満たす50μmとした。また、実施の形態8に従い、凹部を形成した試料を作製した(以下、第2実施例92とする:図16)。第2実施例92では、補償パターン幅を、上記(4)式を満たす70μmとした。
図19は、補償パターン幅と凹部深さとの関係について示す特性図である。実施の形態7に従い、補償パターン幅および凹部深さを種々変更して、凹部を形成した試料を複数作製した(以下、第3実施例とする)。また、実施の形態8に従い、補償パターン幅および凹部深さを種々変更して、凹部を形成した試料を複数作製した(以下、第4実施例とする)。そして、凹部コーナー下端部にエッチング残りが確認されない条件を検討した。
図20〜図23は、補償パターン幅とエッチング量との関係について示す特性図である。図20および図22において、エッチング量とは、第1エッチング幅を示す。また、図21および図23において、エッチング量とは、第2エッチング幅を示す。まず、実施の形態7に従い、正方形状の補償パターンを有するレジストマスクを用いて、凹部を形成した試料を作製した(以下、第5実施例とする)。比較として、正方形状の補償パターンを有する酸化膜マスクを用いて、凹部を形成した試料を作製した(以下、第3比較例とする)。第3比較例のそれ以外の条件は、第5実施例と同様である。
2 フィールドリミッティングリング(FLR)
3 チャネルストッパー
4 層間絶縁膜
5 フィールドプレート(FP)
6 凹部
7 p型コレクタ領域
8 p型領域
11 p+型分離層
21 へき開面
t1 活性領域側の基板の厚さ
t2 素子端部側の基板の厚さ
w1 クラック幅
w11 設計マージン
θ1 へき開面と凹部底面の延長線とのなす角
Claims (10)
- 第1導電型の基板の第1主面に設けられたおもて面素子構造と、
前記基板の前記第1主面の素子端部に設けられた第2導電型の第1半導体領域と、
前記基板の第2主面から前記第1半導体領域に達する凹部と、
前記基板の前記第2主面に設けられ、前記第1半導体領域と電気的に接続された第2導電型の第2半導体領域と、を有し、
前記第1半導体領域は、前記凹部の底面と側壁の境界を一辺とするへき開面の、前記凹部の底面と側壁の境界から前記第1主面との交点までのすべてを内部に含み、前記へき開面と前記第1主面との交点は、前記凹部の底面と側壁の境界よりも内側にあることを特徴とする半導体装置。 - 前記第1半導体領域は、前記基板からなる第1導電型の第3半導体領域に隣接しており、
前記へき開面よりも前記おもて面素子構造側の前記第1半導体領域は、前記第3半導体領域から当該第1半導体領域内に伸びる空乏層が当該へき開面に到達しない不純物量を有することを特徴とする請求項1に記載の半導体装置。 - 前記不純物量の総量は、1.2×1012/cm2以上であることを特徴とする請求項2に記載の半導体装置。
- 第1導電型のウェハの第1主面に、第2導電型の第1半導体領域を形成する第1半導体領域工程と、
前記ウェハの前記第1主面に、おもて面素子構造を形成するおもて面素子構造工程と、
前記ウェハの第2主面から前記第1半導体領域に達する凹部を形成する凹部形成工程と、
前記ウェハの前記第2主面に、前記第1半導体領域と電気的に接続された第2導電型の第2半導体領域を形成する第2半導体領域工程と、
前記第1半導体領域の一部を除去して前記ウェハを切断し、当該ウェハをチップ状にする切断工程と、を備え、
前記第1半導体領域工程では、前記凹部の底面と側壁の境界を一辺とするへき開面の、前記凹部の底面と側壁の境界から前記第1主面との交点までのすべてを前記第1半導体領域の内部に含むように形成し、
前記切断工程では、前記第1半導体領域を、前記凹部の底面と側壁の境界を一辺とするへき開面の、前記凹部の底面と側壁の境界から前記第1主面との交点までのすべてを前記第1半導体領域の内部に含み、前記へき開面と前記第1主面との交点は、前記凹部の底面と側壁の境界よりも内側にあるように切断することを特徴とする半導体装置の製造方法。 - 前記切断工程では、前記第1半導体領域の切断面が、前記ウェハの前記第1主面と斜度を有するように、当該第1半導体領域を除去することを特徴とする請求項4に記載の半導体装置の製造方法。
- 前記切断工程では、ブレードを前記第1半導体領域の前記第1主面側から降下させ、当該ブレードの刃先が少なくとも前記凹部から下方に突出した時点で当該ブレードの降下を停止させることで、当該ウェハを切断することを特徴とする請求項4または5に記載の半導体装置の製造方法。
- 前記切断工程では、前記第1半導体領域の表面に第1レーザを照射し、当該第1半導体領域の表面からの深さが増すにつれて当該第1レーザの照射径を徐々に狭くすることで、前記ウェハを切断することを特徴とする請求項4または5に記載の半導体装置の製造方法。
- 前記切断工程では、前記第1半導体領域の表面から、露出させる前記切断面に沿って前記第1レーザの照射径を徐々に狭くすることを特徴とする請求項7に記載の半導体装置の製造方法。
- 前記切断工程では、前記第1半導体領域の内部の、露出させる切断面に沿った深さに第2レーザを照射し、当該照射した部分を改質し、ウェハに外力を加えることによって、当該改質した部分を境に当該第1半導体領域を分断することで、前記ウェハを切断することを特徴とする請求項4または5に記載の半導体装置の製造方法。
- 前記切断工程では、前記第1半導体領域の除去される領域の端部から中央部に向かって徐々に深く前記第2レーザを照射することを特徴とする請求項9に記載の半導体装置の製造方法。
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