JP5679626B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5679626B2 JP5679626B2 JP2008176958A JP2008176958A JP5679626B2 JP 5679626 B2 JP5679626 B2 JP 5679626B2 JP 2008176958 A JP2008176958 A JP 2008176958A JP 2008176958 A JP2008176958 A JP 2008176958A JP 5679626 B2 JP5679626 B2 JP 5679626B2
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- JP
- Japan
- Prior art keywords
- region
- stress
- semiconductor
- semiconductor device
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
- Measuring Fluid Pressure (AREA)
Description
2 スクライブ領域
3 応力を受けたくない素子領域
4 充填物
5 溝
6 保護膜
7 支持領域
8 緩衝領域
9 空洞
10 半導体基板
100 半導体装置
Claims (2)
- 半導体基板上のほぼ中央に配置された、対を成すMOSトランジスタを流れる等しい電流が応力によりずれてしまうカレントミラー回路が形成された素子領域と、
前記素子領域の周囲全体に設けられた、溝と前記溝に埋め込まれた充填物とからなる緩衝領域と、
前記緩衝領域の周囲に設けられた半導体素子形成領域と、
前記充填物表面を横切り、前記素子領域の中の素子と前記半導体素子形成領域の中の素子とを接続する配線と、からなり、
前記溝の深さは、前記素子領域の深さおよび前記半導体素子形成領域の深さよりも深く、
前記充填物のヤング率は、前記半導体基板のヤング率よりも小さいことを特徴とする半導体装置。 - 半導体基板上に形成された、対を成すMOSトランジスタを流れる等しい電流が応力によりずれてしまうカレントミラー回路が形成された素子領域と、
前記素子領域の周囲全体に設けられた、溝と前記溝に埋め込まれた充填物とからなる緩衝領域と、
前記緩衝領域の周囲に設けられた半導体素子形成領域と、
前記充填物表面を横切り、前記素子領域の中の素子と前記半導体素子形成領域の中の素子とを接続する配線と、からなり、
前記充填物のヤング率は、前記半導体基板のヤング率よりも小さいことを特徴とする半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008176958A JP5679626B2 (ja) | 2008-07-07 | 2008-07-07 | 半導体装置 |
US12/459,372 US8933541B2 (en) | 2008-07-07 | 2009-06-30 | Semiconductor device |
TW98122423A TWI471922B (zh) | 2008-07-07 | 2009-07-02 | 半導體裝置 |
KR1020090061068A KR101599901B1 (ko) | 2008-07-07 | 2009-07-06 | 반도체 장치 |
CN200910159707.6A CN101626018B (zh) | 2008-07-07 | 2009-07-07 | 半导体器件 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008176958A JP5679626B2 (ja) | 2008-07-07 | 2008-07-07 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010016296A JP2010016296A (ja) | 2010-01-21 |
JP5679626B2 true JP5679626B2 (ja) | 2015-03-04 |
Family
ID=41463725
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008176958A Expired - Fee Related JP5679626B2 (ja) | 2008-07-07 | 2008-07-07 | 半導体装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8933541B2 (ja) |
JP (1) | JP5679626B2 (ja) |
KR (1) | KR101599901B1 (ja) |
CN (1) | CN101626018B (ja) |
TW (1) | TWI471922B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10680012B2 (en) | 2018-09-18 | 2020-06-09 | Toshiba Memory Corporation | Semiconductor device |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9632622B2 (en) * | 2009-07-16 | 2017-04-25 | Apple Inc. | Ground detection for touch sensitive device |
TWI513452B (zh) * | 2011-08-08 | 2015-12-21 | Univ Ching Yun | 精神狀態監控及警示方法及其裝置 |
US10522452B2 (en) | 2011-10-18 | 2019-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods for semiconductor devices including forming trenches in workpiece to separate adjacent packaging substrates |
US9466666B2 (en) | 2012-05-03 | 2016-10-11 | Analog Devices Global | Localized strain relief for an integrated circuit |
JP6154582B2 (ja) * | 2012-06-14 | 2017-06-28 | ラピスセミコンダクタ株式会社 | 半導体装置およびその製造方法 |
CN104051501B (zh) * | 2013-03-15 | 2017-03-01 | 台湾积体电路制造股份有限公司 | 集成电路的支撑结构 |
US9640456B2 (en) * | 2013-03-15 | 2017-05-02 | Taiwan Semiconductor Manufacturing Company Limited | Support structure for integrated circuitry |
WO2015037166A1 (ja) * | 2013-09-11 | 2015-03-19 | パナソニックIpマネジメント株式会社 | 半導体装置 |
US9786609B2 (en) | 2013-11-05 | 2017-10-10 | Analog Devices Global | Stress shield for integrated circuit package |
US9887165B2 (en) * | 2014-12-10 | 2018-02-06 | Stmicroelectronics S.R.L. | IC with insulating trench and related methods |
US20170309577A1 (en) * | 2016-04-25 | 2017-10-26 | Infineon Technologies Ag | Method of manufacturing semiconductor devices |
TWI609468B (zh) | 2017-01-16 | 2017-12-21 | 欣興電子股份有限公司 | 封裝體裝置及其製造方法 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55123148A (en) * | 1979-03-16 | 1980-09-22 | Toshiba Corp | Manufacturing method of semiconductor device |
US4654120A (en) * | 1985-10-31 | 1987-03-31 | International Business Machines Corporation | Method of making a planar trench semiconductor structure |
US5098856A (en) * | 1991-06-18 | 1992-03-24 | International Business Machines Corporation | Air-filled isolation trench with chemically vapor deposited silicon dioxide cap |
JPH0837230A (ja) * | 1994-07-21 | 1996-02-06 | Mitsubishi Electric Corp | 半導体集積回路装置及びその製造方法 |
TW311242B (en) * | 1996-12-12 | 1997-07-21 | Winbond Electronics Corp | Die seal structure with trench and manufacturing method thereof |
DE19811604B4 (de) * | 1997-03-18 | 2007-07-12 | Kabushiki Kaisha Toshiba, Kawasaki | Halbleitervorrichtung |
KR100297737B1 (ko) * | 1998-09-24 | 2001-11-01 | 윤종용 | 반도체소자의 트렌치 소자 분리 방법 |
JP2000183149A (ja) * | 1998-12-10 | 2000-06-30 | Sanyo Electric Co Ltd | 半導体装置 |
US6690074B1 (en) * | 1999-12-10 | 2004-02-10 | Fillfactory | Radiation resistant semiconductor device structure |
JP4295927B2 (ja) * | 2001-04-23 | 2009-07-15 | 株式会社東芝 | 不揮発性半導体記憶装置の製造方法 |
FR2826179A1 (fr) * | 2001-06-14 | 2002-12-20 | St Microelectronics Sa | Tranchee d'isolement profonde et procede de realisation |
JP2003158205A (ja) * | 2001-11-26 | 2003-05-30 | Hitachi Ltd | 半導体装置及び製造方法 |
JP2003174082A (ja) * | 2001-12-06 | 2003-06-20 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US6939736B2 (en) * | 2003-07-31 | 2005-09-06 | Texas Instruments Incorporated | Ideal operational amplifier layout techniques for reducing package stress and configurations therefor |
JP4340578B2 (ja) * | 2004-04-09 | 2009-10-07 | 富士通株式会社 | 部品実装基板及び部品実装構造 |
JP5046529B2 (ja) * | 2005-02-25 | 2012-10-10 | 株式会社半導体エネルギー研究所 | 半導体装置 |
KR20070057576A (ko) * | 2005-12-02 | 2007-06-07 | 주식회사 하이닉스반도체 | 반도체 소자의 변형된 얕은 트렌치 소자 분리 형성 방법 |
JP4613852B2 (ja) * | 2006-02-24 | 2011-01-19 | ソニー株式会社 | 電子デバイス |
KR101204663B1 (ko) * | 2006-05-09 | 2012-11-26 | 에스케이하이닉스 주식회사 | 반도체소자의 리세스 게이트 전극 구조 및 그 형성방법 |
US20100029057A1 (en) * | 2006-09-21 | 2010-02-04 | Jsr Corporation | Silicone resin composition and method of forming a trench isolation |
JP5431638B2 (ja) * | 2006-10-27 | 2014-03-05 | ローム株式会社 | 半導体集積回路 |
JP5132928B2 (ja) * | 2006-12-25 | 2013-01-30 | パナソニック株式会社 | 半導体装置 |
US7488659B2 (en) * | 2007-03-28 | 2009-02-10 | International Business Machines Corporation | Structure and methods for stress concentrating spacer |
JP2009032967A (ja) * | 2007-07-27 | 2009-02-12 | Toshiba Corp | 半導体装置及びその製造方法 |
-
2008
- 2008-07-07 JP JP2008176958A patent/JP5679626B2/ja not_active Expired - Fee Related
-
2009
- 2009-06-30 US US12/459,372 patent/US8933541B2/en not_active Expired - Fee Related
- 2009-07-02 TW TW98122423A patent/TWI471922B/zh not_active IP Right Cessation
- 2009-07-06 KR KR1020090061068A patent/KR101599901B1/ko active IP Right Grant
- 2009-07-07 CN CN200910159707.6A patent/CN101626018B/zh not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10680012B2 (en) | 2018-09-18 | 2020-06-09 | Toshiba Memory Corporation | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
CN101626018A (zh) | 2010-01-13 |
KR101599901B1 (ko) | 2016-03-04 |
US8933541B2 (en) | 2015-01-13 |
US20100001377A1 (en) | 2010-01-07 |
KR20100005678A (ko) | 2010-01-15 |
TWI471922B (zh) | 2015-02-01 |
CN101626018B (zh) | 2014-05-07 |
TW201009907A (en) | 2010-03-01 |
JP2010016296A (ja) | 2010-01-21 |
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