JP5677685B2 - 回路基板、及びそれを用いた半導体装置 - Google Patents
回路基板、及びそれを用いた半導体装置 Download PDFInfo
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- JP5677685B2 JP5677685B2 JP2012554801A JP2012554801A JP5677685B2 JP 5677685 B2 JP5677685 B2 JP 5677685B2 JP 2012554801 A JP2012554801 A JP 2012554801A JP 2012554801 A JP2012554801 A JP 2012554801A JP 5677685 B2 JP5677685 B2 JP 5677685B2
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Description
銅貼りAlN基板と銅支持部材の熱膨張係数が互いに異なるため、これらの一体化物には残留熱応力ないし熱ひずみが発生する。銅貼りAlN基板や銅支持部材は一体化の際に、はんだ材の融点以上に加熱した後室温まで冷却する熱処理工程を経る。この場合、各部材ははんだ材の凝固点で互いに固定されたまま各部材固有の熱膨張係数に従って収縮し、接着部に熱応力ないし熱ひずみが残留するとともに変形を生ずる。
銅貼りAlN基板と銅支持部材の熱膨張係数が互いに異なるため、これらの一体化物にはそりを発生する。半導体装置にそりを生ずると、これを冷却フィンに取り付ける際に熱伝導グリースの装填が均一になされない。この結果、銅支持部材と冷却フィン間の熱的係合が良好になされず、この経路の放熱性が損なわれ、半導体装置の正常動作を困難にする。
半導体基体と銅貼りAlN基板をはんだ付けする工程(#1はんだ層の形成)と、同様のはんだ付けによる銅貼りAlN基板と銅支持部材との一体化工程(#2はんだ層の形成)が必要で、半導体装置の組み立て工数が多くなる。また、一般には#1はんだ層と#2はんだ層の形成工程では温度階層性(異なる融点を持つはんだ材)が必要になるが、既存の鉛フリーはんだ材の組み合わせでは十分な温度階層性を得ることは困難である。
(実施例1)
図2は本発明の半導体装置1000の基本構造を説明する平面及び断面模式図である。(a)は平面図、(b)は(a)におけるA−A′断面をそれぞれ示す。セラミックス基板110として表面に酸化物層150が形成された窒化珪素を用いた。セラミックス基板110の一方の面に銅製の回路配線板130が銀系の接合層120で接合され、他方の面に銅製の支持部材125′が銀系の接合層120で接合されて回路基板125を構成している。回路配線板130の上には半導体基体101が搭載されている。半導体基体101はMOS FET素子である。主端子30や補助端子31を設けてあるポリフェニルサルファイド製の樹脂ケース20が支持部材125′に取り付けられている。素子基体101と回路配線板130の間、半導体素子基体101と補助端子31の間、回路配線板130と主端子30の間には、Al細線117のワイヤボンディングが施されている。樹脂ケース20内にはシリコーンゲル樹脂22が充填され、樹脂ケース20の上部にはポリフェニルサルファイド製の樹脂蓋21が設けられている。ここで、セラミックス基板110に設けられた回路配線板130上には8個の素子基体101が銀系の接合層113により固着されている。また、回路配線板130には温度検出用サーミスタ素子がはんだ(いずれも図示を省略)により接合され、回路配線板130はAl細線117により補助端子31へ連絡されている。なお、図面では省略しているが、樹脂ケース20と支持部材125′の間、そして樹脂ケース20と樹脂蓋21の間はシリコーン接着樹脂(図示を省略)を用いて固定されている。樹脂蓋21の肉厚部には凹み25,主端子30には穴30′がそれぞれ設けられ、半導体装置1000を外部回路配線に連絡するためのネジ(図示を省略)が収納されている。主端子30や補助端子31はあらかじめ所定形状に打抜き成形された銅板にNiめっきを施したものであり、射出成形法によって樹脂ケース20に取り付けられている。
図10は半導体装置の要部を説明する模式図である。この図は、セラミックス板110としての窒化珪素板(30×50×0.3mm;表面酸化)と支持部材としての銅板125を一体化した絶縁基板2000に、半導体基体101をはんだ付け搭載した状態を示す。支持部材125の露出部にはNiめっき層(厚さ:6μm、図示を省略)が設けられている。支持部材125は42.4mm×85mm×3mmなる寸法を有し、その周縁部に取り付け穴(直径:5.6mm)125Fが設けられている。支持部材125とセラミックス基板110は実施例1と同様の酸化銀系系材からなる接合層120(厚さ:50μm、図示を省略)により一体化され、窒化珪素絶縁板110上に設けられた銅合金からなる回路配線板130(厚さ:0.4mm、図示を省略)に半導体基体101としてのMOS FET素子基体(7×7×0.28mm)101が8個搭載されている。
21 樹脂蓋
22 シリコーンゲル樹脂,エポキシ樹脂
25 凹み
30 主端子,端子
101 半導体基体,MOS FET素子基体,IGBT素子基体
110 セラミックス基板,窒化珪素板,窒化アルミニウム板
113,124 接合層
120 接合層
125 回路基板
125′ 支持部材
125F 取り付け穴
130 回路配線板
1000 半導体装置
Claims (10)
- 窒化物を含むセラミックス基板と、
前記セラミックス基板の一方の面に接合層を介して接合された回路配線板と、
前記セラミックス基板の他方の面に接合層を介して接合された金属支持部材と、を備え、
前記接合層が銀または銅を含む焼結体であり、
前記セラミックス基板と前記焼結体の接合界面に酸化物層を有し、
前記酸化物層は前記セラミックス基板側が多結晶層で構成され、前記焼結体側が非晶質層で構成され、
前記酸化物層が珪素またはアルミニウムの酸化物であることを特徴とする回路基板。 - 請求項1に記載の回路基板において、前記酸化物層の厚さが1nm〜10μmであることを特徴とする回路基板。
- 請求項1または2に記載の回路基板において、前記非晶質層の厚さが0.1nm〜100nmであることを特徴とする回路基板。
- 請求項1〜3のいずれか1項に記載の回路基板において、前記セラミックス基板が窒化珪素または窒化アルミニウムであることを特徴とする回路基板。
- 請求項1〜4のいずれか1項に記載の回路基板において、前記焼結体の熱伝導率が50W/mK〜430W/mKであることを特徴とする回路基板。
- 窒化物を含むセラミックス基板と、
前記セラミックス基板の一方の面に接合層を介して接合された回路配線板と、
前記セラミックス基板の他方の面に接合層を介して接合された金属支持部材と、
前記回路配線板に搭載された半導体素子と、を備え、
前記接合層が銀または銅を含む焼結体であり、
前記セラミックス基板と前記焼結体の接合界面に酸化物層を有し、
前記酸化物層は前記セラミックス基板側が多結晶層で構成され、前記焼結体側が非晶質層で構成され、
前記酸化物層が珪素またはアルミニウムの酸化物であることを特徴とする半導体装置。 - 請求項6に記載の半導体装置において、前記酸化物層の厚さが1nm〜10μmであることを特徴とする半導体装置。
- 請求項6または7に記載の半導体装置において、前記非晶質層の厚さが0.1nm〜100nmであることを特徴とする半導体装置。
- 請求項6〜8のいずれか1項に記載の半導体装置において、前記セラミックス基板が窒化珪素または窒化アルミニウムであることを特徴とする半導体装置。
- 請求項6〜9のいずれか1項に記載の半導体装置において、前記焼結体の熱伝導率が50W/mK〜430W/mKであることを特徴とする半導体装置。
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JP2012114224A (ja) * | 2010-11-24 | 2012-06-14 | Mitsubishi Materials Corp | ヒートシンク付パワーモジュール用基板、パワーモジュール及びパワーモジュール用基板の製造方法 |
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CA2038832C (fr) | 1991-03-22 | 1995-09-12 | Salim Dermarkar | Materiau pour composants electroniques passifs |
JP4077888B2 (ja) * | 1995-07-21 | 2008-04-23 | 株式会社東芝 | セラミックス回路基板 |
JP3180677B2 (ja) | 1996-08-22 | 2001-06-25 | 三菱マテリアル株式会社 | ヒートシンク付セラミック回路基板 |
JP2000277953A (ja) | 1999-03-23 | 2000-10-06 | Hitachi Metals Ltd | セラミックス回路基板 |
ATE400538T1 (de) * | 2001-03-16 | 2008-07-15 | Electrovac | Aiuminiumnitridsubstrat sowie verfahren zur vorbereitung dieses substrates auf die verbindung mit einer kupferfolie |
US20070231590A1 (en) * | 2006-03-31 | 2007-10-04 | Stellar Industries Corp. | Method of Bonding Metals to Ceramics |
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JP2006202938A (ja) * | 2005-01-20 | 2006-08-03 | Kojiro Kobayashi | 半導体装置及びその製造方法 |
JP2008198706A (ja) * | 2007-02-09 | 2008-08-28 | Hitachi Metals Ltd | 回路基板、その製造方法およびそれを用いた半導体モジュール |
JP2008244242A (ja) * | 2007-03-28 | 2008-10-09 | Hitachi Ltd | 半導体装置、その製造方法、複合金属体及びその製造方法 |
JP2009267374A (ja) * | 2008-03-31 | 2009-11-12 | Hitachi Ltd | 半導体装置及び接合材料 |
JP2010238784A (ja) * | 2009-03-30 | 2010-10-21 | Hitachi Cable Ltd | 半導体素子およびその製造方法 |
JP2011249802A (ja) * | 2010-05-27 | 2011-12-08 | Semikron Elektronik Gmbh & Co Kg | 低温加圧焼結接合を含む2個の接合素子の構成体およびその製造方法 |
JP2012114224A (ja) * | 2010-11-24 | 2012-06-14 | Mitsubishi Materials Corp | ヒートシンク付パワーモジュール用基板、パワーモジュール及びパワーモジュール用基板の製造方法 |
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WO2012102267A1 (ja) | 2012-08-02 |
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