US20130241007A1 - Use of band edge gate metals as source drain contacts - Google Patents
Use of band edge gate metals as source drain contacts Download PDFInfo
- Publication number
- US20130241007A1 US20130241007A1 US13/421,276 US201213421276A US2013241007A1 US 20130241007 A1 US20130241007 A1 US 20130241007A1 US 201213421276 A US201213421276 A US 201213421276A US 2013241007 A1 US2013241007 A1 US 2013241007A1
- Authority
- US
- United States
- Prior art keywords
- gate
- band edge
- metal
- layer
- depositing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 114
- 239000002184 metal Substances 0.000 title claims abstract description 114
- 150000002739 metals Chemical class 0.000 title description 7
- 238000000034 method Methods 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 238000000151 deposition Methods 0.000 claims abstract description 32
- 239000012212 insulator Substances 0.000 claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 230000004888 barrier function Effects 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims description 41
- 230000008569 process Effects 0.000 claims description 22
- 239000003989 dielectric material Substances 0.000 claims description 17
- 150000004767 nitrides Chemical class 0.000 claims description 13
- 229910045601 alloy Inorganic materials 0.000 claims description 10
- 239000000956 alloy Substances 0.000 claims description 10
- 239000002019 doping agent Substances 0.000 claims description 10
- 230000005669 field effect Effects 0.000 claims description 10
- 150000001247 metal acetylides Chemical class 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052697 platinum Inorganic materials 0.000 claims description 5
- 229910052702 rhenium Inorganic materials 0.000 claims description 5
- 229910052691 Erbium Inorganic materials 0.000 claims description 4
- 229910052769 Ytterbium Inorganic materials 0.000 claims description 4
- 229910052741 iridium Inorganic materials 0.000 claims description 4
- 229910052763 palladium Inorganic materials 0.000 claims description 4
- 229910052703 rhodium Inorganic materials 0.000 claims description 4
- 229910052707 ruthenium Inorganic materials 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 230000000873 masking effect Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 40
- 125000006850 spacer group Chemical group 0.000 description 12
- 239000007943 implant Substances 0.000 description 11
- 229910021332 silicide Inorganic materials 0.000 description 8
- 238000000231 atomic layer deposition Methods 0.000 description 7
- 238000001465 metallisation Methods 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- -1 SiN) Chemical class 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 241000894007 species Species 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910002244 LaAlO3 Inorganic materials 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 241000321453 Paranthias colonus Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910002370 SrTiO3 Inorganic materials 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 229910010303 TiOxNy Inorganic materials 0.000 description 1
- 229910003134 ZrOx Inorganic materials 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000006260 foam Substances 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 229910021350 transition metal silicide Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
- H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Definitions
- CMOS complementary metal oxide semiconductor
- S/D source/drain
- the exemplary embodiments of this invention provide a method to fabricate a structure.
- the method comprises providing a semiconductor substrate having intentionally doped surface regions, the intentionally doped surface regions corresponding to locations of a source and a drain of a transistor; depositing a layer a band edge gate metal onto a gate insulator layer in a gate region of the transistor while simultaneously depositing the band edge gate metal onto the surface of the semiconductor substrate to be in contact with the intentionally doped surface regions; and depositing a layer of contact metal over the band edge gate metal in the gate region and in the locations of the source and the drain.
- the exemplary embodiments of this invention provide a method to reduce a Schottky barrier height of source/drain contacts of a field effect transistor.
- the method comprises forming a gate stack comprising a gate insulator layer that overlies a surface of a semiconductor substrate; further forming the gate stack by depositing band edge gate metal on the gate insulator layer, while also depositing the band edge gate metal directly onto the surface of the semiconductor substrate at locations of the source/drain contacts; and further forming the gate stack by depositing contact metal over the band edge gate metal to form a gate contact and source/drain contacts.
- the exemplary embodiments of this invention provide a device that comprises a gate stack formed over a channel in a semiconductor substrate.
- the gate stack comprises a layer of gate insulator material, a layer of gate metal overlying the layer of gate insulator material, and a layer of contact metal overlying the layer band edge gate metal.
- the device further comprises source and drain contacts adjacent to the channel.
- the source and drain contacts each comprise a layer of the gate metal that overlies and is in direct electrical contact with a doped region of the semiconductor substrate, and a layer of contact metal that overlies the layer of gate metal.
- FIGS. 1A-1G collectively referred to as FIG. 1 , illustrate a process flow suitable for fabricating a transistor in accordance with embodiments of this invention, where
- FIG. 1A shows a partially fabricated preliminary structure for an nFET (left side of FIG. 1A ) and a pFET (right side of FIG. 1A );
- FIG. 1B shows the structure of FIG. 1A after poly exposure, a CMP and poly removal
- FIG. 1C shows the structure of FIG. 1B after a mask is applied everywhere but where a CA will be formed and a reactive ion etch is performed to define the CA;
- FIG. 1D shows the structure of FIG. 1C after the CA is masked and a gate dielectric layer is applied to the inner surfaces of openings left after dummy gate removal;
- FIG. 1E shows the structure of FIG. 1D after band edge (BE) gate metal deposition
- FIG. 1F shows the structure of FIG. 1E after a blanket deposition of CA metal
- FIG. 1G shows the structure of FIG. 1F after removal of the CA metal and the BE metal from the field.
- FIGS. 2A-2D collectively referred to as FIG. 2 , illustrate another process flow suitable for fabricating a transistor in accordance with embodiments of this invention, where
- FIG. 2A shows a partially fabricated preliminary structure for an nFET (left side of FIG. 2A ) and a pFET (right side of FIG. 2A ), where in this embodiment a gate dielectric layer (e.g., a high-k layer) is disposed beneath the dummy gate plug;
- a gate dielectric layer e.g., a high-k layer
- FIG. 2B shows the structure of FIG. 2A after poly exposure, a CMP and poly removal
- FIG. 2C shows the structure of FIG. 2B after a mask is applied everywhere but where a CA will be formed and a reactive ion etch is performed to define the CA;
- FIG. 2D shows the structure of FIG. 2C after band edge (BE) gate metal deposition.
- gate metals are used as S/D contacts.
- the gate metal deposition can be by physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD), as non-limiting examples of gate metal deposition processes.
- PVD physical vapor deposition
- CVD chemical vapor deposition
- ALD atomic layer deposition
- gate metal deposition processes include PVD, chemical vapor deposition (CVD) or atomic layer deposition (ALD), as non-limiting examples of gate metal deposition processes.
- nFET band edge
- BE gate metals include TiAl, TiAlN and TiN/Al/TiN as several non-limiting examples.
- pFET the BE gate metals include thicker TiN, Re, Pt (and their carbides and nitrides) as several non-limiting examples.
- the exemplary embodiments of this invention beneficially provide a BE gate metal as a S/D contact to reduce metal/Si contact resistance.
- a metal fill step can be simultaneously performed for the gate and the S/D.
- BE metal is conventionally referred to one of the conduction band edge (NMOS) or the valence band edge (PMOS) of the constituent semiconductor material.
- NMOS conduction band edge
- PMOS valence band edge
- a goal is to reduce or minimize the Schottky barrier height, i.e., the difference between the metal workfunction and the semiconductor (e.g., Si) electron affinity.
- the eWF (effective workfunction) on different gate dielectrics (for the gate) or directly on the Si is not the same as the vacuum WF. This is generally explained by the Fermi level pinning model. Different interfaces can have different pinning factors such that the eWF could vary on different dielectrics. However, there is still a correlation between the vacuum WF and the eWF: a higher WF metal exhibits a relatively higher eWF.
- a band edge gate metal (with the band edge eWF on high K) may no longer have a band edge eWF on the S/D depending on the pinning factor difference, but can still have an eWF that is closer to the band edge as compared to other metal choices.
- the use of the BE metal as a gate contact results in a reduction in the threshold voltage (Vt) of the FET.
- Vt threshold voltage
- the presence of the BE gate metal on the S/D also beneficially implies that there is no need to form silicide.
- Silicide is conventionally used to reduce the interface contact resistance and to function as an adhesion of the CA metal to the substrate.
- Nickel or Nickel-alloy silicides are typically used. It is known that the use of silicides can cause a yield loss due to metal diffusion into the substrate at typical processing temperatures (e.g., of about 300° C.) for silicide formation, especially through defects in substrates.
- the BE metals employed for fabricating the S/D contacts in accordance with the embodiments of this invention exhibit limited metal diffusion with no need of thermal treatment for silicide formation, thereby improving the yield.
- FIG. 1 presents an enlarged cross-sectional view of a substrate 10 having various layers disposed over a major surface thereof.
- the various layer thicknesses are not drawn to scale.
- FIG. 1A shows a partially fabricated preliminary structure for an nFET (left side of FIG. 1A ) and a pFET (right side of FIG. 1A ).
- the structures include a substrate 10 , such as a Si substrate, or a Ge substrate, or a SiGe substrate, or a substrate formed of a Group III-V material (e.g., GaAs or an alloy thereof).
- a Si substrate will be assumed for explaining the process flow, although it should be appreciated that the Si substrate 10 is a non-limiting example of a suitable substrate.
- the substrate 10 could be a bulk substrate or a silicon on insulator (SOI) substrate. In the case of an SOI substrate 10 there will be an underlying layer of buried oxide (BOX), not shown.
- SOI silicon on insulator
- nFETs and the pFETs can be formed on the same substrate 10 , and this will also be assumed in the ensuing discussion.
- portions of two adjacent transistors T1 and T2 are shown with, as a non-limiting example, a common Source or a common Drain (S/D) intentionally doped region 12 having associated extensions 14 A, 14 B.
- S/D region 12 can be made by an n+ implant (e.g., an As implant) while for the pFET the 12 the S/D region 12 can be made by a p+ implant (e.g., a B implant).
- the implant dopant species concentration may be in a range of about, for example, 1 ⁇ 10 20 to about 4 ⁇ 10 20 atoms/cm 3 .
- two dummy gate structures 16 A, 16 B having spacers 18 A, 18 B and an interlayer dielectric (ILD) layer 20 .
- the material of the dummy gate structures 16 A, 16 B may be amorphous Si or a nitride or any suitable sacrificial material
- the spacers 18 A, 18 B may be any suitable spacer material such as a nitride (e.g., SiN)
- the ILD 20 can be any suitable dielectric (oxide, such as SiO 2 ) material.
- the width of the dummy gates 16 A, 16 B defines the channel length of the resultant FETs and can be in a range of about, for example, 15 nm to about 35 nm, or more preferably about 20 nm to about 25 nm, and the height can be in a range of about 30 nm to about 50 nm.
- the spacing between the dummy gates 16 A, 16 B will typically be larger and may be in a range of about 30 nm to about 40 nm and will define at least in part the width of the Source or Drain contact area (CA) which can have similar dimensions to the gate dimensions.
- CA Source or Drain contact area
- the S/D region 12 is, for example, a Source
- a Drain region and extensions
- the processing described below applies equally to the Source and the Drain CAs.
- FIG. 1B shows the structure of FIG. 1A after poly exposure, a chemical-mechanical polish (CMP) and poly removal. At this point the material of the dummy gates 16 A, 16 B has been removed and the top surface of the ILD 20 has been planarized to the top of the spacers 18 A, 18 B.
- CMP chemical-mechanical polish
- FIG. 1C shows the structure of FIG. 1B after a mask is applied everywhere but where the CA will be formed, and a reactive ion etch (RIE) is performed to remove the ILD 20 within the CA to expose within an opening 22 the underlying surface of the substrate 10 in the S/D region 12 .
- the RIE chemistry is selected depending on the material of the ILD 20 .
- FIG. 1C shows the opening 22 as having sloping sidewalls. In other embodiments the sidewalls of the opening 22 can be substantially vertical, or the ILD material between the opposed spacers 18 B, 18 A can be removed entirely.
- the mask is also removed.
- FIG. 1D shows the structure of FIG. 1C after the CA is masked and a gate dielectric layer 24 is applied to the inner surfaces of the openings left after the material of the dummy gates 16 A, 16 B was removed in the process step of FIG. 1B .
- the gate dielectric layer 24 can be any suitable dielectric material that will not be affected by subsequent processing steps.
- One particularly suitable material is a high dielectric constant (high-k) material comprising a dielectric metal oxide having a dielectric constant that is greater than the dielectric constant of silicon nitride of 7.5.
- the high-k dielectric layer 24 may be formed by methods well known in the art including, for example, CVD and ALD.
- the dielectric metal oxide comprises a metal and oxygen, and optionally nitrogen and/or silicon.
- Exemplary high-k dielectric materials include HfO 2 , ZrO 2 , La 2 O 3 , Al 2 O 3 , TiO 2 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , HfO x N y , ZrO x N y , La 2 O x N y , Al 2 O x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y 2 O x N y , a silicate thereof, and an alloy thereof.
- Each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2.
- the thickness of the high-k dielectric layer 24 may be from about 1 nm to about 10 nm, with about 5 nm being one suitable value. The mask over the CA is then removed.
- FIG. 1E shows the structure of FIG. 1D after BE gate metal deposition.
- the pFET is masked and nFET n-BE metal 26 A is deposited.
- the mask is then removed from the pFET, the nFET is masked, and pFET p-BE metal 26 B is deposited.
- the mask is then removed from the nFET.
- the process flow could be reversed to deposit the p-BE metal 26 B first.
- the BE gate metal is deposited directly upon the high-k dielectric layer 24 in the gate regions, and deposited in the CA so that the exposed surface of the substrate 10 and the implanted S/D region 12 therein is directly contacted by the BE gate metal layer 26 A, 26 B.
- the BE gate metal 26 can have an exemplary thickness of up to about 20 nm, although a thickness of less than about 10 nm can be preferred.
- the BE metal 26 can be deposited, for example, by CVD, physical vapor deposition (PVD), or atomic layer deposition (ALD).
- Suitable and non-limiting nFET band edge metal 26 A choices can be: Al, Ti, Er, Yb, Ta and their alloys, carbides, and nitrides.
- Suitable and non-limiting pFET band edge metal 26 B choices can be: Pt, Ir, Pd, Rh, Co, Ni, Ru, Re, and their alloys, carbides and nitrides.
- FIG. 1F shows the structure of FIG. 1E after a blanket deposition of CA metal 28 .
- Any suitable contact metal can be employed such as, for example, Al, W or Cu, and the CA metal 28 can be deposited by any conventional process, including for example sputtering and CVD.
- FIG. 1G shows the structure of FIG. 1F after removal of the CA metal 28 and the BE metal 26 from the field dielectrics.
- a CMP can be performed to planarize the surface.
- the CA is provided with a dual metal damascene comprising the layer of BE metal 26 in direct contact with the semiconductor substrate 10 , and the Source or Drain implant region 12 , and the overlying layer of CA metal 28 .
- the layer of BE metal 26 in the CA in each type of transistor (nFET or pFET) is identical to the BE metal in the adjacent gate stack and can be deposited in the same process operation.
- the presence of the layer of BE metal 26 in the CA, in contact with the underlying semiconductor material of the S/D reduces the Schottky barrier height and thus beneficially reduces S/D resistance.
- the disclosed processing beneficially eliminates the need to form a silicide.
- FIGS. 1A-1G are for illustration purposes.
- the processes to achieve band edge metal in the gate stack and S/D contacts can be different.
- FIG. 2 for showing a non-limiting example of an alternative process flow using, for example, a gate-first process. Structures that are found also in the embodiment of FIG. 1 are labeled accordingly.
- FIG. 2A is analogous to FIG. 1A and shows a partially fabricated preliminary structure for an nFET (left side) and a pFET (right side).
- the structure includes the substrate 10 , such as a Si substrate, and shows portions of two adjacent transistors (T1 and T2).
- the common Source or common Drain (S/D) intentionally doped region 12 has the associated extensions 14 A, 14 B.
- the S/D region 12 can be made by an n+ implant (e.g., an As implant) while for the pFET the 12 the S/D region 12 can be made by a p+ implant (e.g., a B implant).
- the implant dopant species concentration may be in the range of about, for example, 1 ⁇ 10 20 to about 4 ⁇ 10 20 atoms/cm 3 .
- the two dummy gate structures 16 A, 16 B having spacers 18 A, 18 B and an interlayer dielectric (ILD) layer 20 .
- the material of the dummy gate structures 16 A, 16 B may be amorphous Si or a nitride or any suitable sacrificial material
- the spacers 18 A, 18 B may be any suitable spacer material such as a nitride (e.g., SiN)
- the ILD 20 can be any suitable dielectric (oxide, such as SiO 2 ) material.
- the various dopants and ranges of thicknesses, dimensions, dopant concentrations can be the same as described above for FIG. 1A .
- the layer of gate dielectric layer 24 has been applied to the substrate 10 prior to the formation of the two dummy gate structures 16 A, 16 B.
- the gate dielectric layer 24 can be any suitable dielectric material that will not be affected by subsequent processing steps, and can comprise a layer of high-k material as discussed above.
- the thickness of the high-k dielectric layer 24 may be from about 1 nm to about 10 nm, with about 5 nm being one suitable value.
- FIG. 2B shows the structure of FIG. 2A after poly exposure, a chemical-mechanical polish (CMP) and poly removal.
- CMP chemical-mechanical polish
- the material of the dummy gates 16 A, 16 B has been removed and the top surface of the ILD 20 has been planarized to the top of the spacers 18 A, 18 B.
- the removal of the dummy gates 16 A, 16 B exposes the surface of the underlying gate dielectric layer 24 .
- FIG. 2C shows the structure of FIG. 2B after a mask is applied everywhere but where the CA will be formed, and a reactive ion etch (RIE) is performed to remove the ILD 20 within the CA to expose within an opening 22 the underlying surface of the substrate 10 in the S/D region 12 .
- the RIE chemistry is selected depending on the material of the ILD 20 .
- FIG. 2C shows the opening 22 as having sloping sidewalls, although in other embodiments the sidewalls of the opening 22 can be substantially vertical, or the ILD material between the opposed spacers 18 B, 18 A can be removed entirely.
- the mask is also removed.
- FIG. 2D shows the structure of FIG. 2C after BE gate metal deposition.
- the pFET is masked and nFET n-BE metal 26 A is deposited.
- the mask is then removed from the pFET, the nFET is masked, and pFET p-BE metal 26 B is deposited.
- the mask is then removed from the nFET.
- the process flow could be reversed to deposit the p-BE metal 26 B first.
- the BE gate metal is deposited directly upon the high-k dielectric layer 24 at the bottom of the gate regions, and deposited in the CA so that the exposed surface of the substrate 10 and the implanted S/D region 12 therein is directly contacted by the BE gate metal layer 26 A, 26 B.
- the BE gate metal 26 can have an exemplary thickness of up to about 20 nm, although a thickness of less than about 10 nm can be preferred.
- the BE metal 26 can be deposited, for example, by CVD, physical vapor deposition (PVD), or atomic layer deposition (ALD).
- Suitable and non-limiting nFET band edge metal 26 A choices can be: Al, Ti, Er, Yb, Ta and their alloys, carbides, and nitrides.
- Suitable and non-limiting pFET band edge metal 26 B choices can be: Pt, Ir, Pd, Rh, Co, Ni, Ru, Re, and their alloys, carbides and nitrides.
- Processing then continues as described above with respect to FIG. 1F and FIG. 1G to perform the blanket deposition of the CA metal 28 , the removal of the CA metal 28 and the BE metal 26 from the field dielectrics, and a CMP operation to planarize the surface.
- FIGS. 1A-1G and FIGS. 2A-2D are described with regard to planar devices, the processes described herein may be used on common variants of FET devices including, e.g., FET devices with multi-fingered FIN and/or gate structures, FET devices of varying gate width and length, as well as ring oscillator devices.
- the transistor device can be connected to metalized pads or other devices by conventional ultra-large-scale integration (ULSI) metalization and lithographic techniques.
- ULSI ultra-large-scale integration
- transistor device contacts in addition to fabricating transistor device contacts as discussed above, further aspects of the present invention include methods to form contacts for other devices or otherwise constructing integrated circuits with various analog and digital circuitry.
- integrated circuit dies can be fabricated with various devices such as a field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, resistors, capacitors, inductors, etc., having contacts that are formed using methods as described herein.
- An integrated circuit in accordance with the present invention can be employed in applications, hardware, and/or electronic systems.
- Suitable hardware and systems in which such integrated circuits can be incorporated include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating such integrated circuits are considered part of this invention. Given the teachings of the exemplary embodiments of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of the invention.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Materials Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
- The exemplary embodiments of this invention relate generally to transistor devices and, more specifically, relate to complementary metal oxide semiconductor (CMOS) transistor devices and to the formation of source/drain (S/D) contacts for such devices.
- Contact resistance has become a dominating factor and consideration as transistor devices such as field effect transistor (FET) devices are scaled to smaller dimensions. There is a need to provide a process and a structure to reduce contact resistance (S/D contact resistance) that are compatible with existing processes and that are also cost effective.
- In a first aspect thereof the exemplary embodiments of this invention provide a method to fabricate a structure. The method comprises providing a semiconductor substrate having intentionally doped surface regions, the intentionally doped surface regions corresponding to locations of a source and a drain of a transistor; depositing a layer a band edge gate metal onto a gate insulator layer in a gate region of the transistor while simultaneously depositing the band edge gate metal onto the surface of the semiconductor substrate to be in contact with the intentionally doped surface regions; and depositing a layer of contact metal over the band edge gate metal in the gate region and in the locations of the source and the drain.
- In another aspect thereof the exemplary embodiments of this invention provide a method to reduce a Schottky barrier height of source/drain contacts of a field effect transistor. The method comprises forming a gate stack comprising a gate insulator layer that overlies a surface of a semiconductor substrate; further forming the gate stack by depositing band edge gate metal on the gate insulator layer, while also depositing the band edge gate metal directly onto the surface of the semiconductor substrate at locations of the source/drain contacts; and further forming the gate stack by depositing contact metal over the band edge gate metal to form a gate contact and source/drain contacts.
- In a still further aspect thereof the exemplary embodiments of this invention provide a device that comprises a gate stack formed over a channel in a semiconductor substrate. The gate stack comprises a layer of gate insulator material, a layer of gate metal overlying the layer of gate insulator material, and a layer of contact metal overlying the layer band edge gate metal. The device further comprises source and drain contacts adjacent to the channel. The source and drain contacts each comprise a layer of the gate metal that overlies and is in direct electrical contact with a doped region of the semiconductor substrate, and a layer of contact metal that overlies the layer of gate metal.
-
FIGS. 1A-1G , collectively referred to asFIG. 1 , illustrate a process flow suitable for fabricating a transistor in accordance with embodiments of this invention, where -
FIG. 1A shows a partially fabricated preliminary structure for an nFET (left side ofFIG. 1A ) and a pFET (right side ofFIG. 1A ); -
FIG. 1B shows the structure ofFIG. 1A after poly exposure, a CMP and poly removal; -
FIG. 1C shows the structure ofFIG. 1B after a mask is applied everywhere but where a CA will be formed and a reactive ion etch is performed to define the CA; -
FIG. 1D shows the structure ofFIG. 1C after the CA is masked and a gate dielectric layer is applied to the inner surfaces of openings left after dummy gate removal; -
FIG. 1E shows the structure ofFIG. 1D after band edge (BE) gate metal deposition; -
FIG. 1F shows the structure ofFIG. 1E after a blanket deposition of CA metal; and -
FIG. 1G shows the structure ofFIG. 1F after removal of the CA metal and the BE metal from the field. -
FIGS. 2A-2D , collectively referred to asFIG. 2 , illustrate another process flow suitable for fabricating a transistor in accordance with embodiments of this invention, where -
FIG. 2A shows a partially fabricated preliminary structure for an nFET (left side ofFIG. 2A ) and a pFET (right side ofFIG. 2A ), where in this embodiment a gate dielectric layer (e.g., a high-k layer) is disposed beneath the dummy gate plug; -
FIG. 2B shows the structure ofFIG. 2A after poly exposure, a CMP and poly removal; -
FIG. 2C shows the structure ofFIG. 2B after a mask is applied everywhere but where a CA will be formed and a reactive ion etch is performed to define the CA; and -
FIG. 2D shows the structure ofFIG. 2C after band edge (BE) gate metal deposition. - In accordance with an aspect of the exemplary embodiments of this invention gate metals are used as S/D contacts. The gate metal deposition can be by physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD), as non-limiting examples of gate metal deposition processes. For an n-type FET (nFET) band edge (BE) gate metals include TiAl, TiAlN and TiN/Al/TiN as several non-limiting examples. For a p-type FET (pFET) the BE gate metals include thicker TiN, Re, Pt (and their carbides and nitrides) as several non-limiting examples.
- The exemplary embodiments of this invention beneficially provide a BE gate metal as a S/D contact to reduce metal/Si contact resistance. By the use of these embodiments the need to provide a silicide can be eliminated. In addition there is a simplified process flow for fabricating metal contacts to the gate and the S/D, and a metal fill step can be simultaneously performed for the gate and the S/D.
- The concept of a BE metal is conventionally referred to one of the conduction band edge (NMOS) or the valence band edge (PMOS) of the constituent semiconductor material. A goal is to reduce or minimize the Schottky barrier height, i.e., the difference between the metal workfunction and the semiconductor (e.g., Si) electron affinity.
- It can be noted that the eWF (effective workfunction) on different gate dielectrics (for the gate) or directly on the Si is not the same as the vacuum WF. This is generally explained by the Fermi level pinning model. Different interfaces can have different pinning factors such that the eWF could vary on different dielectrics. However, there is still a correlation between the vacuum WF and the eWF: a higher WF metal exhibits a relatively higher eWF.
- As considered herein a band edge gate metal (with the band edge eWF on high K) may no longer have a band edge eWF on the S/D depending on the pinning factor difference, but can still have an eWF that is closer to the band edge as compared to other metal choices.
- For Silicon the conduction band edge Ec: 4.05 eV and the valence band edge Ev: 5.17 eV. The workfunctions for various metals are well characterized. Reference can be made, for example, to pages 18 and 19 of “Work Functions of the Transition Metals and Metal Silicides”, Timothy J. Drummond, Sandia National Laboratories, 1999 (SAN099-0391J).
- In accordance with the embodiments of this invention, for a FET having a gate stack the use of the BE metal as a gate contact results in a reduction in the threshold voltage (Vt) of the FET. By applying the gate stack BE metal(s) to the S/D contacts the Schottky barrier height is reduced and current can more readily flow between the semiconductor material and the contact metal, which is manifested as a reduction in S/D resistance.
- The presence of the BE gate metal on the S/D also beneficially implies that there is no need to form silicide. Silicide is conventionally used to reduce the interface contact resistance and to function as an adhesion of the CA metal to the substrate. In state-of-the-art FET devices, Nickel or Nickel-alloy silicides are typically used. It is known that the use of silicides can cause a yield loss due to metal diffusion into the substrate at typical processing temperatures (e.g., of about 300° C.) for silicide formation, especially through defects in substrates. The BE metals employed for fabricating the S/D contacts in accordance with the embodiments of this invention exhibit limited metal diffusion with no need of thermal treatment for silicide formation, thereby improving the yield.
- The exemplary and non-limiting embodiments of this invention are described with reference to the process flow depicted in
FIGS. 1A-1G , collectively referred to asFIG. 1 . In general,FIG. 1 presents an enlarged cross-sectional view of asubstrate 10 having various layers disposed over a major surface thereof. The various layer thicknesses are not drawn to scale. -
FIG. 1A shows a partially fabricated preliminary structure for an nFET (left side ofFIG. 1A ) and a pFET (right side ofFIG. 1A ). The structures include asubstrate 10, such as a Si substrate, or a Ge substrate, or a SiGe substrate, or a substrate formed of a Group III-V material (e.g., GaAs or an alloy thereof). A Si substrate will be assumed for explaining the process flow, although it should be appreciated that theSi substrate 10 is a non-limiting example of a suitable substrate. Thesubstrate 10 could be a bulk substrate or a silicon on insulator (SOI) substrate. In the case of anSOI substrate 10 there will be an underlying layer of buried oxide (BOX), not shown. While depicted on two separate substrates inFIG. 1 , it should be appreciated that the nFETs and the pFETs can be formed on thesame substrate 10, and this will also be assumed in the ensuing discussion. Note that portions of two adjacent transistors (T1 and T2) are shown with, as a non-limiting example, a common Source or a common Drain (S/D) intentionally dopedregion 12 having associatedextensions D region 12 can be made by an n+ implant (e.g., an As implant) while for the pFET the 12 the S/D region 12 can be made by a p+ implant (e.g., a B implant). The implant dopant species concentration may be in a range of about, for example, 1×1020 to about 4×1020 atoms/cm3. Also shown are twodummy gate structures layer 20. The material of thedummy gate structures spacers ILD 20 can be any suitable dielectric (oxide, such as SiO2) material. The width of thedummy gates dummy gates D region 12 is, for example, a Source, then it is assumed that a Drain region (and extensions) is present (not shown) on the opposite sides of thedummy gates left-most spacer 18A andright-most spacer 18B. The processing described below applies equally to the Source and the Drain CAs. -
FIG. 1B shows the structure ofFIG. 1A after poly exposure, a chemical-mechanical polish (CMP) and poly removal. At this point the material of thedummy gates ILD 20 has been planarized to the top of the spacers 18A, 18B. -
FIG. 1C shows the structure ofFIG. 1B after a mask is applied everywhere but where the CA will be formed, and a reactive ion etch (RIE) is performed to remove theILD 20 within the CA to expose within anopening 22 the underlying surface of thesubstrate 10 in the S/D region 12. The RIE chemistry is selected depending on the material of theILD 20. Note thatFIG. 1C shows theopening 22 as having sloping sidewalls. In other embodiments the sidewalls of theopening 22 can be substantially vertical, or the ILD material between theopposed spacers -
FIG. 1D shows the structure ofFIG. 1C after the CA is masked and agate dielectric layer 24 is applied to the inner surfaces of the openings left after the material of thedummy gates FIG. 1B . Thegate dielectric layer 24 can be any suitable dielectric material that will not be affected by subsequent processing steps. One particularly suitable material is a high dielectric constant (high-k) material comprising a dielectric metal oxide having a dielectric constant that is greater than the dielectric constant of silicon nitride of 7.5. The high-k dielectric layer 24 may be formed by methods well known in the art including, for example, CVD and ALD. The dielectric metal oxide comprises a metal and oxygen, and optionally nitrogen and/or silicon. Exemplary high-k dielectric materials include HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, Y2O3, HfOxNy, ZrOxNy, La2OxNy, Al2OxNy, TiOxNy, SrTiOxNy, LaAlOxNy, Y2OxNy, a silicate thereof, and an alloy thereof. Each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2. The thickness of the high-k dielectric layer 24 may be from about 1 nm to about 10 nm, with about 5 nm being one suitable value. The mask over the CA is then removed. -
FIG. 1E shows the structure ofFIG. 1D after BE gate metal deposition. In this process step the pFET is masked and nFET n-BE metal 26A is deposited. The mask is then removed from the pFET, the nFET is masked, and pFET p-BE metal 26B is deposited. The mask is then removed from the nFET. Of course, the process flow could be reversed to deposit the p-BE metal 26B first. The BE gate metal is deposited directly upon the high-k dielectric layer 24 in the gate regions, and deposited in the CA so that the exposed surface of thesubstrate 10 and the implanted S/D region 12 therein is directly contacted by the BEgate metal layer band edge metal 26A choices can be: Al, Ti, Er, Yb, Ta and their alloys, carbides, and nitrides. Suitable and non-limiting pFETband edge metal 26B choices can be: Pt, Ir, Pd, Rh, Co, Ni, Ru, Re, and their alloys, carbides and nitrides. -
FIG. 1F shows the structure ofFIG. 1E after a blanket deposition ofCA metal 28. Any suitable contact metal can be employed such as, for example, Al, W or Cu, and theCA metal 28 can be deposited by any conventional process, including for example sputtering and CVD. -
FIG. 1G shows the structure ofFIG. 1F after removal of theCA metal 28 and the BE metal 26 from the field dielectrics. A CMP can be performed to planarize the surface. - The end result is that the CA is provided with a dual metal damascene comprising the layer of BE metal 26 in direct contact with the
semiconductor substrate 10, and the Source orDrain implant region 12, and the overlying layer ofCA metal 28. The layer of BE metal 26 in the CA in each type of transistor (nFET or pFET) is identical to the BE metal in the adjacent gate stack and can be deposited in the same process operation. The presence of the layer of BE metal 26 in the CA, in contact with the underlying semiconductor material of the S/D, reduces the Schottky barrier height and thus beneficially reduces S/D resistance. The disclosed processing beneficially eliminates the need to form a silicide. - It can be noted that the exemplary embodiments disclosed above assume the same BE gate metal in the gate stack and in the S/D contacts, however they do not have to be the same.
- It is to be understood that the processes described by
FIGS. 1A-1G are for illustration purposes. The processes to achieve band edge metal in the gate stack and S/D contacts can be different. - For example, reference can be made to
FIG. 2 for showing a non-limiting example of an alternative process flow using, for example, a gate-first process. Structures that are found also in the embodiment ofFIG. 1 are labeled accordingly. -
FIG. 2A is analogous toFIG. 1A and shows a partially fabricated preliminary structure for an nFET (left side) and a pFET (right side). The structure includes thesubstrate 10, such as a Si substrate, and shows portions of two adjacent transistors (T1 and T2). The common Source or common Drain (S/D) intentionally dopedregion 12 has the associatedextensions D region 12 can be made by an n+ implant (e.g., an As implant) while for the pFET the 12 the S/D region 12 can be made by a p+ implant (e.g., a B implant). The implant dopant species concentration may be in the range of about, for example, 1×1020 to about 4×1020 atoms/cm3. Also shown are the twodummy gate structures layer 20. The material of thedummy gate structures spacers ILD 20 can be any suitable dielectric (oxide, such as SiO2) material. In general the various dopants and ranges of thicknesses, dimensions, dopant concentrations can be the same as described above forFIG. 1A . - However, in this embodiment the layer of
gate dielectric layer 24 has been applied to thesubstrate 10 prior to the formation of the twodummy gate structures gate dielectric layer 24 can be any suitable dielectric material that will not be affected by subsequent processing steps, and can comprise a layer of high-k material as discussed above. The thickness of the high-k dielectric layer 24 may be from about 1 nm to about 10 nm, with about 5 nm being one suitable value. -
FIG. 2B shows the structure ofFIG. 2A after poly exposure, a chemical-mechanical polish (CMP) and poly removal. At this point the material of thedummy gates ILD 20 has been planarized to the top of the spacers 18A, 18B. In this embodiment the removal of thedummy gates gate dielectric layer 24. -
FIG. 2C shows the structure ofFIG. 2B after a mask is applied everywhere but where the CA will be formed, and a reactive ion etch (RIE) is performed to remove theILD 20 within the CA to expose within anopening 22 the underlying surface of thesubstrate 10 in the S/D region 12. The RIE chemistry is selected depending on the material of theILD 20.FIG. 2C shows theopening 22 as having sloping sidewalls, although in other embodiments the sidewalls of theopening 22 can be substantially vertical, or the ILD material between theopposed spacers -
FIG. 2D shows the structure ofFIG. 2C after BE gate metal deposition. In this process step the pFET is masked and nFET n-BE metal 26A is deposited. The mask is then removed from the pFET, the nFET is masked, and pFET p-BE metal 26B is deposited. The mask is then removed from the nFET. As in the embodiment ofFIG. 1E , the process flow could be reversed to deposit the p-BE metal 26B first. The BE gate metal is deposited directly upon the high-k dielectric layer 24 at the bottom of the gate regions, and deposited in the CA so that the exposed surface of thesubstrate 10 and the implanted S/D region 12 therein is directly contacted by the BEgate metal layer band edge metal 26A choices can be: Al, Ti, Er, Yb, Ta and their alloys, carbides, and nitrides. Suitable and non-limiting pFETband edge metal 26B choices can be: Pt, Ir, Pd, Rh, Co, Ni, Ru, Re, and their alloys, carbides and nitrides. - Processing then continues as described above with respect to
FIG. 1F andFIG. 1G to perform the blanket deposition of theCA metal 28, the removal of theCA metal 28 and the BE metal 26 from the field dielectrics, and a CMP operation to planarize the surface. - It is to be understood that although the exemplary embodiments discussed above with reference to
FIGS. 1A-1G andFIGS. 2A-2D are described with regard to planar devices, the processes described herein may be used on common variants of FET devices including, e.g., FET devices with multi-fingered FIN and/or gate structures, FET devices of varying gate width and length, as well as ring oscillator devices. Moreover, the transistor device can be connected to metalized pads or other devices by conventional ultra-large-scale integration (ULSI) metalization and lithographic techniques. - It is to be understood that in addition to fabricating transistor device contacts as discussed above, further aspects of the present invention include methods to form contacts for other devices or otherwise constructing integrated circuits with various analog and digital circuitry. In particular, integrated circuit dies can be fabricated with various devices such as a field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, resistors, capacitors, inductors, etc., having contacts that are formed using methods as described herein. An integrated circuit in accordance with the present invention can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems in which such integrated circuits can be incorporated include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating such integrated circuits are considered part of this invention. Given the teachings of the exemplary embodiments of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of the invention.
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural foams as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
- The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the concepts of this invention for various embodiments with various modifications as are suited to the particular use contemplated.
- As such, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims As but some examples, the use of other similar or equivalent semiconductor fabrication processes, including material deposition processes and material removal processes may be used by those skilled in the art. Further, the exemplary embodiments are not intended to be limited to only those materials, metals, insulators, dopants, dopant concentrations, layer thicknesses and the like that were specifically disclosed above. Any and all such and similar modifications of the teachings of this invention will still fall within the scope of this invention.
Claims (20)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/421,276 US20130241007A1 (en) | 2012-03-15 | 2012-03-15 | Use of band edge gate metals as source drain contacts |
US13/611,736 US8741753B2 (en) | 2012-03-15 | 2012-09-12 | Use of band edge gate metals as source drain contacts |
PCT/US2013/030468 WO2013138316A1 (en) | 2012-03-15 | 2013-03-12 | Use of band edge gate metals as source drain contacts |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/421,276 US20130241007A1 (en) | 2012-03-15 | 2012-03-15 | Use of band edge gate metals as source drain contacts |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/611,736 Continuation US8741753B2 (en) | 2012-03-15 | 2012-09-12 | Use of band edge gate metals as source drain contacts |
Publications (1)
Publication Number | Publication Date |
---|---|
US20130241007A1 true US20130241007A1 (en) | 2013-09-19 |
Family
ID=49156879
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/421,276 Abandoned US20130241007A1 (en) | 2012-03-15 | 2012-03-15 | Use of band edge gate metals as source drain contacts |
US13/611,736 Active US8741753B2 (en) | 2012-03-15 | 2012-09-12 | Use of band edge gate metals as source drain contacts |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/611,736 Active US8741753B2 (en) | 2012-03-15 | 2012-09-12 | Use of band edge gate metals as source drain contacts |
Country Status (2)
Country | Link |
---|---|
US (2) | US20130241007A1 (en) |
WO (1) | WO2013138316A1 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140264483A1 (en) * | 2013-03-15 | 2014-09-18 | Naomi Yoshida | Metal gate structures for field effect transistors and method of fabrication |
WO2015127363A1 (en) * | 2014-02-21 | 2015-08-27 | Samsung Electronics, Co., Ltd. | Integrated circuit devices including contacts and methods of forming the same |
US9472628B2 (en) | 2014-07-14 | 2016-10-18 | International Business Machines Corporation | Heterogeneous source drain region and extension region |
US9685509B2 (en) | 2013-07-30 | 2017-06-20 | Samsung Electronics Co., Ltd. | Finfet devices including high mobility channel materials with materials of graded composition in recessed source/drain regions |
US10147793B2 (en) | 2013-07-30 | 2018-12-04 | Samsung Electronics Co., Ltd. | FinFET devices including recessed source/drain regions having optimized depths |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5640379B2 (en) | 2009-12-28 | 2014-12-17 | ソニー株式会社 | Manufacturing method of semiconductor device |
US20130241007A1 (en) * | 2012-03-15 | 2013-09-19 | International Business Machines Corporation | Use of band edge gate metals as source drain contacts |
US9024376B2 (en) * | 2013-01-25 | 2015-05-05 | Unisantis Electronics Singapore Pte. Ltd. | Vertical transistor with dielectrically-isolated work-function metal electrodes surrounding the semiconductor pillar |
US9136131B2 (en) * | 2013-11-04 | 2015-09-15 | Globalfoundries Inc. | Common fill of gate and source and drain contacts |
US9725310B2 (en) * | 2013-12-20 | 2017-08-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Micro electromechanical system sensor and method of forming the same |
US9190488B1 (en) * | 2014-08-13 | 2015-11-17 | Globalfoundries Inc. | Methods of forming gate structure of semiconductor devices and the resulting devices |
US20160104621A1 (en) * | 2014-10-10 | 2016-04-14 | Globalfoundries Inc. | Semiconductor device having common contact and gate properties |
KR102224386B1 (en) | 2014-12-18 | 2021-03-08 | 삼성전자주식회사 | Method for fabricating an integrated circuit device |
US9589851B2 (en) * | 2015-07-16 | 2017-03-07 | International Business Machines Corporation | Dipole-based contact structure to reduce metal-semiconductor contact resistance in MOSFETs |
TWI658593B (en) * | 2015-08-10 | 2019-05-01 | 聯華電子股份有限公司 | Semiconductor device and a fabrication method thereof |
US9735111B2 (en) | 2015-09-23 | 2017-08-15 | International Business Machines Corporation | Dual metal-insulator-semiconductor contact structure and formulation method |
US10446550B2 (en) * | 2017-10-13 | 2019-10-15 | Globalfoundries Inc. | Cut inside replacement metal gate trench to mitigate N-P proximity effect |
Family Cites Families (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5681779A (en) * | 1994-02-04 | 1997-10-28 | Lsi Logic Corporation | Method of doping metal layers for electromigration resistance |
JP2874626B2 (en) * | 1996-01-23 | 1999-03-24 | 日本電気株式会社 | Method for manufacturing semiconductor device |
US6261932B1 (en) * | 1999-07-29 | 2001-07-17 | Fairchild Semiconductor Corp. | Method of fabricating Schottky diode and related structure |
US7126169B2 (en) * | 2000-10-23 | 2006-10-24 | Matsushita Electric Industrial Co., Ltd. | Semiconductor element |
BE1015721A3 (en) | 2003-10-17 | 2005-07-05 | Imec Inter Uni Micro Electr | METHOD FOR REDUCING THE CONTACT RESISTANCE OF THE CONNECTION AREAS OF A SEMICONDUCTOR DEVICE. |
JP2005209782A (en) * | 2004-01-21 | 2005-08-04 | Toshiba Corp | Semiconductor device |
JP2005294789A (en) * | 2004-03-10 | 2005-10-20 | Toshiba Corp | Semiconductor device and its manufacturing method |
KR100634503B1 (en) * | 2004-03-12 | 2006-10-16 | 삼성전자주식회사 | Light emitting device and method of manufacturing thereof |
JP2006060045A (en) * | 2004-08-20 | 2006-03-02 | Toshiba Corp | Semiconductor device |
US7598545B2 (en) | 2005-04-21 | 2009-10-06 | International Business Machines Corporation | Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices |
JP4490336B2 (en) * | 2005-06-13 | 2010-06-23 | シャープ株式会社 | Semiconductor device and manufacturing method thereof |
US7432567B2 (en) | 2005-12-28 | 2008-10-07 | International Business Machines Corporation | Metal gate CMOS with at least a single gate metal and dual gate dielectrics |
US20070267762A1 (en) * | 2006-05-19 | 2007-11-22 | Interuniversitair Microelektronica Centrum Vzw (Imec) | Semiconductor devices |
US7816729B2 (en) * | 2006-08-08 | 2010-10-19 | Fwu-Iuan Hshieh | Trenched MOSFET device with trenched contacts |
JP4247257B2 (en) * | 2006-08-29 | 2009-04-02 | 株式会社東芝 | Manufacturing method of semiconductor device |
US7812414B2 (en) | 2007-01-23 | 2010-10-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid process for forming metal gates |
US8021904B2 (en) * | 2007-02-01 | 2011-09-20 | Cree, Inc. | Ohmic contacts to nitrogen polarity GaN |
US20080191285A1 (en) | 2007-02-09 | 2008-08-14 | Chih-Hsin Ko | CMOS devices with schottky source and drain regions |
JP4960125B2 (en) * | 2007-03-22 | 2012-06-27 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
US20080277726A1 (en) | 2007-05-08 | 2008-11-13 | Doris Bruce B | Devices with Metal Gate, High-k Dielectric, and Butted Electrodes |
US8159035B2 (en) | 2007-07-09 | 2012-04-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal gates of PMOS devices having high work functions |
US20090101972A1 (en) * | 2007-10-17 | 2009-04-23 | Gaines R Stockton | Process for fabricating a field-effect transistor with doping segregation used in source and/or drain |
JP5221112B2 (en) * | 2007-11-29 | 2013-06-26 | 株式会社東芝 | Semiconductor device manufacturing method and semiconductor device |
US8097500B2 (en) | 2008-01-14 | 2012-01-17 | International Business Machines Corporation | Method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device |
JP2010010266A (en) | 2008-06-25 | 2010-01-14 | Nec Electronics Corp | Method for manufacturing semiconductor device and semiconductor device |
US20110114914A1 (en) * | 2008-07-25 | 2011-05-19 | Hideaki Numata | Field effect transistor and circuit device |
US7838353B2 (en) | 2008-08-12 | 2010-11-23 | International Business Machines Corporation | Field effect transistor with suppressed corner leakage through channel material band-edge modulation, design structure and method |
US8022474B2 (en) * | 2008-09-30 | 2011-09-20 | Infineon Technologies Austria Ag | Semiconductor device |
JP4730422B2 (en) * | 2008-10-24 | 2011-07-20 | 住友電気工業株式会社 | Group III nitride semiconductor electronic device, method of fabricating group III nitride semiconductor electronic device, and group III nitride semiconductor epitaxial wafer |
US7999298B2 (en) * | 2008-12-30 | 2011-08-16 | Intel Corporation | Embedded memory cell and method of manufacturing same |
JP2010206002A (en) * | 2009-03-04 | 2010-09-16 | Fuji Electric Systems Co Ltd | P-channel silicon carbide mosfet |
JP5443789B2 (en) * | 2009-03-09 | 2014-03-19 | 株式会社東芝 | Semiconductor device |
US8110467B2 (en) | 2009-04-21 | 2012-02-07 | International Business Machines Corporation | Multiple Vt field-effect transistor devices |
EP2278636A1 (en) * | 2009-07-21 | 2011-01-26 | Sony Corporation | Uses of dithiocarbamate compounds |
US8536654B2 (en) | 2010-01-13 | 2013-09-17 | Texas Instruments Incorporated | Structure and method for dual work function metal gate CMOS with selective capping |
DE102011005718B4 (en) * | 2011-03-17 | 2012-10-31 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | A method of reducing the equivalent thickness of high-k dielectrics in field effect transistors by performing a low temperature anneal process |
JP5613640B2 (en) * | 2011-09-08 | 2014-10-29 | 株式会社東芝 | Manufacturing method of semiconductor device |
US8420519B1 (en) * | 2011-11-01 | 2013-04-16 | GlobalFoundries, Inc. | Methods for fabricating integrated circuits with controlled P-channel threshold voltage |
US9006800B2 (en) * | 2011-12-14 | 2015-04-14 | Avogy, Inc. | Ingan ohmic source contacts for vertical power devices |
US8546212B2 (en) * | 2011-12-21 | 2013-10-01 | United Microelectronics Corp. | Semiconductor device and fabricating method thereof |
US8735236B2 (en) * | 2011-12-29 | 2014-05-27 | Globalfoundries Inc. | High-k metal gate electrode structure formed by removing a work function on sidewalls in replacement gate technology |
US20130241007A1 (en) * | 2012-03-15 | 2013-09-19 | International Business Machines Corporation | Use of band edge gate metals as source drain contacts |
US8765592B2 (en) * | 2012-03-29 | 2014-07-01 | Texas Instruments Incorporated | Multi-landing contact etching |
US8951855B2 (en) * | 2012-04-24 | 2015-02-10 | United Microelectronics Corp. | Manufacturing method for semiconductor device having metal gate |
-
2012
- 2012-03-15 US US13/421,276 patent/US20130241007A1/en not_active Abandoned
- 2012-09-12 US US13/611,736 patent/US8741753B2/en active Active
-
2013
- 2013-03-12 WO PCT/US2013/030468 patent/WO2013138316A1/en active Application Filing
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140264483A1 (en) * | 2013-03-15 | 2014-09-18 | Naomi Yoshida | Metal gate structures for field effect transistors and method of fabrication |
US9018054B2 (en) * | 2013-03-15 | 2015-04-28 | Applied Materials, Inc. | Metal gate structures for field effect transistors and method of fabrication |
US9685509B2 (en) | 2013-07-30 | 2017-06-20 | Samsung Electronics Co., Ltd. | Finfet devices including high mobility channel materials with materials of graded composition in recessed source/drain regions |
US10147793B2 (en) | 2013-07-30 | 2018-12-04 | Samsung Electronics Co., Ltd. | FinFET devices including recessed source/drain regions having optimized depths |
WO2015127363A1 (en) * | 2014-02-21 | 2015-08-27 | Samsung Electronics, Co., Ltd. | Integrated circuit devices including contacts and methods of forming the same |
US9431492B2 (en) | 2014-02-21 | 2016-08-30 | Samsung Electronics Co., Ltd. | Integrated circuit devices including contacts and methods of forming the same |
US9472628B2 (en) | 2014-07-14 | 2016-10-18 | International Business Machines Corporation | Heterogeneous source drain region and extension region |
US10158001B2 (en) | 2014-07-14 | 2018-12-18 | International Business Machines Corporation | Heterogeneous source drain region and extension region |
US10170587B2 (en) | 2014-07-14 | 2019-01-01 | International Business Machines Corporation | Heterogeneous source drain region and extension region |
Also Published As
Publication number | Publication date |
---|---|
WO2013138316A1 (en) | 2013-09-19 |
US20130241008A1 (en) | 2013-09-19 |
US8741753B2 (en) | 2014-06-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8741753B2 (en) | Use of band edge gate metals as source drain contacts | |
US8962412B2 (en) | Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same | |
US8836038B2 (en) | CMOS dual metal gate semiconductor device | |
US8373219B2 (en) | Method of fabricating a gate stack integration of complementary MOS device | |
US9947528B2 (en) | Structure and method for nFET with high k metal gate | |
US8008145B2 (en) | High-K metal gate structure fabrication method including hard mask | |
US7745890B2 (en) | Hybrid metal fully silicided (FUSI) gate | |
EP3711098A1 (en) | Replacement metal gate processes for vertical transport field-effect transistor | |
US20070228480A1 (en) | CMOS device having PMOS and NMOS transistors with different gate structures | |
US20070296052A1 (en) | Methods of forming silicide regions and resulting MOS devices | |
US8026539B2 (en) | Metal oxide semiconductor devices having doped silicon-compromising capping layers and methods for fabricating the same | |
US8581351B2 (en) | Replacement gate with reduced gate leakage current | |
US20120273901A1 (en) | Semiconductor device and method for manufacturing the same | |
US10461169B2 (en) | Semiconductor device structure and method for forming the same | |
US10811433B2 (en) | High-voltage transistor device with thick gate insulation layers | |
KR20180029823A (en) | Complimentary metal-oxide-semiconductor circuit having transistors with different threshold voltages and method of manufacturing the same | |
US20120018739A1 (en) | Body contact device structure and method of manufacture | |
CN220963349U (en) | Semiconductor device with a semiconductor device having a plurality of semiconductor chips | |
US20240112957A1 (en) | Barrier layer for weakened boundary effect | |
CN107437527B (en) | Through contact using silicide |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LAVOIE, CHRISTIAN;SOLOMON, PAUL M.;ZHANG, ZHEN;SIGNING DATES FROM 20120222 TO 20120224;REEL/FRAME:027870/0769 Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHOI, KISIK;YANG, BIN;SIGNING DATES FROM 20120312 TO 20120313;REEL/FRAME:027870/0903 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO PAY ISSUE FEE |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |