JP5536897B2 - 縦型パワートランジスタ装置、半導体チップ、および縦型パワートランジスタ装置の製造方法 - Google Patents
縦型パワートランジスタ装置、半導体チップ、および縦型パワートランジスタ装置の製造方法 Download PDFInfo
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
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Description
示した本発明の実施形態は、ほとんどの部分において当業者にとって既知である電子部品や回路を用いて実装されていることから、本発明の基本的な概念が理解され認められることに必要と見なされる程度を越えては、また本発明の教示を不明瞭にしたり紛らわしくしたりしないよう、詳細な説明はしない。
Claims (8)
- 縦型パワートランジスタ装置において、
III−V族半導体材料から形成された基板であって、該基板の第1の側に凹部を有する基板と、
少なくとも部分的に前記基板の凹部内に設けられる多層スタックと、を備え
前記多層スタックは、
前記凹部内に配置されて第1のIII−V族半導体材料から形成された第1の層と、
第2のIII−V族半導体材料から形成された第2の層と、
前記第1の層と前記第2の層との界面に形成されたヘテロ接合部と、
前記凹部において前記基板から前記ヘテロ接合部を電気的に絶縁するべく、該凹部内において該基板と前記第1の層との間に配置された半絶縁層とを備え、
前記基板の第1の側と反対側の第2の側には、該基板に電気的に接続される第1コンタクトが形成され、
前記基板の第1の側において、前記多層スタック上には第2コンタクトおよびゲートコンタクトが形成され、
前記半絶縁層および前記第1の層は前記基板の面に平行な水平面において該基板の凹部の側面によって囲まれており、該半絶縁層は前記凹部の側面に隣接する前記基板の領域に向かって水平方向に電流を流すように構成される、装置。 - 前記多層スタックは、前記第2の層上に形成されて該第2の層の酸化を防止するように構成される第3の層をさらに備え、前記第2コンタクトおよび前記ゲートコンタクトは該第3の層上に形成される、請求項1に記載の装置。
- 前記半絶縁層は、III族窒化物材料、III族窒化物材料の二元系、III族窒化物材料の三元系、III族窒化物材料の四元系、p型のドーパントを含む窒化ガリウム、AlGaN、InGaN、およびAlInNからなる群から選択されるIII−V族の半導体材料から形成される、請求項1または2に記載の装置。
- 前記第1の層、前記第2の層またはその両方は、III族窒化物材料、III族窒化物材料の二元系、III族窒化物材料の三元系、III族窒化物材料の四元系、GaN、AlGaN、InGaN、およびAlInNからなる群から選択される、ドープされた、または意図的にドープされていないIII−V族半導体材料から形成される、請求項1〜3のいずれか一項に記載の装置。
- 半導体チップにおいて、
請求項1〜4のいずれか一項に記載の縦型パワートランジスタ装置の構造を備える第1のパワートランジスタ装置と、
請求項1〜4のいずれか一項に記載の縦型パワートランジスタ装置の構造を備える第2のパワートランジスタ装置と、を備え、
前記第1および第2のパワートランジスタ装置の基板は、該第1および第2のパワートランジスタ装置に共通した基板であって、該基板は前記第1のパワートランジスタ装置における第1の多層スタックと前記第2のパワートランジスタ装置における第2の多層スタックとの間の垂直ドリフト領域を支持可能であり、
前記半導体チップはさらに、
前記第1および第2のパワートランジスタ装置における前記第1および第2の多層スタックの対向する側面の間の接続領域であって、該第1および第2の多層スタックのヘテロ接合部を垂直ドリフト領域に電気的に結合させるための接続領域、を備える半導体チップ。 - 前記接続領域は、前記第1の多層スタックにおける第1の層と前記第2の多層スタックにおける第1の層とを架橋するように配列されたイオン注入領域を備える、請求項5に記載の半導体チップ。
- 前記イオン注入領域は、前記第1の多層スタックにおける第2の層および第3の層と、前記第2の多層スタックにおける第2の層および第3の層とを架橋する、請求項2に従属する請求項6に記載の半導体チップ。
- 縦型トランジスタ装置の製造方法において、
III−V族半導体材料の窒化物から形成されている基板を提供する工程と、
前記基板の第1の側において該基板内にエッチングによって凹部を形成する工程と、
第1のIII−V族半導体材料から形成される第1の層を前記凹部内に成長させる工程と、
第2のIII−V族半導体材料から形成される第2の層を成長させる工程と、
前記第1の層と前記第2の層との界面にヘテロ接合部を形成する工程と、
前記凹部において前記基板から前記ヘテロ接合部を電気的に絶縁して該凹部の側面に隣接する前記基板の領域に向かって水平方向に電流を流すべく、前記凹部内において前記基板と前記第1の層との間に配置される半絶縁層を成長させる工程と、
前記基板の第1の側と反対側の第2の側に第1コンタクトを形成する工程と、
前記第1コンタクトと前記基板とを電気的に接続する工程と、
前記基板の第1の側において、第2コンタクトおよびゲートコンタクトを形成する工程と、を備える方法。
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PCT/IB2009/056014 WO2011061573A1 (en) | 2009-11-19 | 2009-11-19 | Vertical power transistor device, semiconductor die and method of manufacturing a vertical power transistor device |
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JP2013511833A JP2013511833A (ja) | 2013-04-04 |
JP5536897B2 true JP5536897B2 (ja) | 2014-07-02 |
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US (1) | US9825162B2 (ja) |
EP (1) | EP2502274B1 (ja) |
JP (1) | JP5536897B2 (ja) |
CN (1) | CN102612750B (ja) |
TW (1) | TWI524517B (ja) |
WO (1) | WO2011061573A1 (ja) |
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JP5536897B2 (ja) * | 2009-11-19 | 2014-07-02 | フリースケール セミコンダクター インコーポレイテッド | 縦型パワートランジスタ装置、半導体チップ、および縦型パワートランジスタ装置の製造方法 |
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EP2502274A4 (en) | 2013-05-01 |
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CN102612750A (zh) | 2012-07-25 |
JP2013511833A (ja) | 2013-04-04 |
TW201140823A (en) | 2011-11-16 |
CN102612750B (zh) | 2015-07-29 |
TWI524517B (zh) | 2016-03-01 |
US20120217511A1 (en) | 2012-08-30 |
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US9825162B2 (en) | 2017-11-21 |
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