JP5535486B2 - 絶縁体上に半導体が設けられた構造(soi)を有するボディコンタクト素子の形成方法及び装置 - Google Patents
絶縁体上に半導体が設けられた構造(soi)を有するボディコンタクト素子の形成方法及び装置 Download PDFInfo
- Publication number
- JP5535486B2 JP5535486B2 JP2008554454A JP2008554454A JP5535486B2 JP 5535486 B2 JP5535486 B2 JP 5535486B2 JP 2008554454 A JP2008554454 A JP 2008554454A JP 2008554454 A JP2008554454 A JP 2008554454A JP 5535486 B2 JP5535486 B2 JP 5535486B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- active region
- active
- gate structure
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 74
- 238000000034 method Methods 0.000 title claims description 31
- 239000012212 insulator Substances 0.000 title description 6
- 210000000746 body region Anatomy 0.000 claims description 10
- 229910021332 silicide Inorganic materials 0.000 claims description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 8
- 238000002513 implantation Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 5
- 230000000873 masking effect Effects 0.000 claims 1
- 239000002019 doping agent Substances 0.000 description 13
- 125000006850 spacer group Chemical group 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 230000008901 benefit Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 239000007943 implant Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000000872 buffer Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
- H01L29/78615—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect with a body contact
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Description
上記の実施例がn型素子の作製について参照しながら説明されているとはいえ、本明細書に記載された方法及び構造はp型素子にも同様に適用されうることに留意して欲しい。その場合図を参照しながら論じられた伝導型が反対になる。
Claims (3)
- 半導体素子の作製方法であって:
絶縁層の上に設けられた半導体層をパターニングして第1活性領域及び第2活性領域を形成する工程であって、前記第1活性領域の高さは前記第2活性領域とは異なり、前記第1活性領域の少なくとも一部は低濃度ドープされていて、かつ前記第2活性領域の少なくとも一部は高濃度ドープされている、工程;
前記第1活性領域の上部と側部及び前記第2活性領域の少なくとも一部にわたってゲート構造を形成する工程であって、チャネル領域は、前記ゲート構造に隣接する、前記の第1活性領域の上部と側部に沿って設けられる、工程;
前記ゲート構造の形成後、前記半導体素子のドレイン領域又はソース領域のいずれかの領域のみから前記第2活性領域の一部を除去して前記絶縁層を曝露する工程であって、前記の半導体素子のドレイン領域又はソース領域のいずれかの領域が前記半導体素子のドレイン領域である、工程;並びに
シリサイド領域を形成する工程であって、
前記シリサイド領域は、前記半導体素子のソース領域内の前記ゲート構造の下に位置していない前記第1活性領域を、前記第2活性領域と接続し、
前記第1活性領域は該第1活性領域の側壁間であって前記チャネル領域の外側でかつ前記ゲート構造の下にボディ領域を有し、
前記シリサイド領域は、前記ボディ領域と前記ソース領域内の前記ゲート構造の下に存在しない前記第1活性領域との間の接続を供し、かつ
前記シリサイド領域は、前記ソース領域内の前記ゲート構造の下に位置していない前記第2活性領域全体に行き渡り、下に存在する前記絶縁層にまで延在する、
工程;
を有する方法。 - 前記絶縁層の上に設けられた半導体層をパターニングして第1活性領域及び第2活性領域を形成する工程が:
前記第1活性領域をマスクする工程;及び
前記第2活性領域へ注入を実行する工程;
をさらに有する、請求項1に記載の方法。 - 前記半導体層をパターニングする工程が、前記第2活性領域に隣接する第3活性領域、及び前記第3活性領域に隣接する第4活性領域を形成する工程をさらに有し、
前記第2活性領域は前記第1活性領域と第3活性領域との間に存在し、
前記第3活性領域は前記第2活性領域と第4活性領域との間に存在し、
前記ゲート構造を形成する工程が、前記第3及び第4活性領域にわたって前記ゲート構造を形成する工程を有し、
前記ゲート構造の下に存在する前記第1及び第3活性領域の一部は同一の高さ及び伝導型を有し、かつ
前記ゲート構造の下に存在する前記第2及び第4活性領域の一部は同一の高さ及び伝導型を有する、
請求項1に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/349,875 | 2006-02-08 | ||
US11/349,875 US7446001B2 (en) | 2006-02-08 | 2006-02-08 | Method for forming a semiconductor-on-insulator (SOI) body-contacted device with a portion of drain region removed |
PCT/US2007/060843 WO2007098305A2 (en) | 2006-02-08 | 2007-01-22 | Method and apparatus for forming a semiconductor-on-insulator (soi) body-contacted device |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2009526409A JP2009526409A (ja) | 2009-07-16 |
JP2009526409A5 JP2009526409A5 (ja) | 2010-03-11 |
JP5535486B2 true JP5535486B2 (ja) | 2014-07-02 |
Family
ID=38333175
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008554454A Active JP5535486B2 (ja) | 2006-02-08 | 2007-01-22 | 絶縁体上に半導体が設けられた構造(soi)を有するボディコンタクト素子の形成方法及び装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7446001B2 (ja) |
JP (1) | JP5535486B2 (ja) |
CN (1) | CN101379614B (ja) |
TW (1) | TWI414023B (ja) |
WO (1) | WO2007098305A2 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7964897B2 (en) * | 2008-07-22 | 2011-06-21 | Honeywell International Inc. | Direct contact to area efficient body tie process flow |
CN101931008B (zh) * | 2010-07-13 | 2015-04-08 | 中国科学院上海微***与信息技术研究所 | 一种具有体接触结构的pd soi器件 |
KR20140040543A (ko) * | 2012-09-26 | 2014-04-03 | 삼성전자주식회사 | 핀 구조의 전계효과 트랜지스터, 이를 포함하는 메모리 장치 및 그 반도체 장치 |
US9064725B2 (en) * | 2012-12-14 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET with embedded MOS varactor and method of making same |
JP6373686B2 (ja) | 2014-08-22 | 2018-08-15 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9177968B1 (en) | 2014-09-19 | 2015-11-03 | Silanna Semiconductor U.S.A., Inc. | Schottky clamped radio frequency switch |
CN106571359B (zh) * | 2015-10-10 | 2019-08-27 | 中芯国际集成电路制造(北京)有限公司 | 静电放电保护结构及其形成方法 |
JP6612937B2 (ja) * | 2018-07-18 | 2019-11-27 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4835584A (en) * | 1986-11-27 | 1989-05-30 | American Telephone And Telegraph Company, At&T Bell Laboratories | Trench transistor |
US4753895A (en) * | 1987-02-24 | 1988-06-28 | Hughes Aircraft Company | Method of forming low leakage CMOS device on insulating substrate |
US4922315A (en) * | 1987-11-13 | 1990-05-01 | Kopin Corporation | Control gate lateral silicon-on-insulator bipolar transistor |
US4906587A (en) * | 1988-07-29 | 1990-03-06 | Texas Instruments Incorporated | Making a silicon-on-insulator transistor with selectable body node to source node connection |
US5008723A (en) * | 1989-12-29 | 1991-04-16 | Kopin Corporation | MOS thin film transistor |
USH1435H (en) * | 1991-10-21 | 1995-05-02 | Cherne Richard D | SOI CMOS device having body extension for providing sidewall channel stop and bodytie |
US5821575A (en) * | 1996-05-20 | 1998-10-13 | Digital Equipment Corporation | Compact self-aligned body contact silicon-on-insulator transistor |
JP4014677B2 (ja) * | 1996-08-13 | 2007-11-28 | 株式会社半導体エネルギー研究所 | 絶縁ゲイト型半導体装置 |
US5932911A (en) * | 1996-12-13 | 1999-08-03 | Advanced Micro Devices, Inc. | Bar field effect transistor |
US6355532B1 (en) * | 1999-10-06 | 2002-03-12 | Lsi Logic Corporation | Subtractive oxidation method of fabricating a short-length and vertically-oriented channel, dual-gate, CMOS FET |
JP3504212B2 (ja) * | 2000-04-04 | 2004-03-08 | シャープ株式会社 | Soi構造の半導体装置 |
JP2002033484A (ja) * | 2000-07-18 | 2002-01-31 | Mitsubishi Electric Corp | 半導体装置 |
US7163864B1 (en) * | 2000-10-18 | 2007-01-16 | International Business Machines Corporation | Method of fabricating semiconductor side wall fin |
US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
US6538284B1 (en) * | 2001-02-02 | 2003-03-25 | Advanced Micro Devices, Inc. | SOI device with body recombination region, and method |
JP4304884B2 (ja) * | 2001-06-06 | 2009-07-29 | 日本電気株式会社 | 半導体装置及びその製造方法 |
JP4115158B2 (ja) * | 2002-04-24 | 2008-07-09 | シャープ株式会社 | 半導体装置およびその製造方法 |
JP4546021B2 (ja) * | 2002-10-02 | 2010-09-15 | ルネサスエレクトロニクス株式会社 | 絶縁ゲート型電界効果型トランジスタ及び半導体装置 |
US6885055B2 (en) * | 2003-02-04 | 2005-04-26 | Lee Jong-Ho | Double-gate FinFET device and fabricating method thereof |
DE10318604B4 (de) * | 2003-04-24 | 2008-10-09 | Qimonda Ag | Feldeffekttransistor |
US7013447B2 (en) * | 2003-07-22 | 2006-03-14 | Freescale Semiconductor, Inc. | Method for converting a planar transistor design to a vertical double gate transistor design |
US6953738B2 (en) * | 2003-12-12 | 2005-10-11 | Freescale Semiconductor, Inc. | Method and apparatus for forming an SOI body-contacted transistor |
-
2006
- 2006-02-08 US US11/349,875 patent/US7446001B2/en active Active
-
2007
- 2007-01-08 TW TW096100710A patent/TWI414023B/zh active
- 2007-01-22 CN CN2007800050278A patent/CN101379614B/zh active Active
- 2007-01-22 WO PCT/US2007/060843 patent/WO2007098305A2/en active Application Filing
- 2007-01-22 JP JP2008554454A patent/JP5535486B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
WO2007098305A2 (en) | 2007-08-30 |
CN101379614B (zh) | 2010-12-08 |
US20070181946A1 (en) | 2007-08-09 |
WO2007098305A3 (en) | 2008-03-13 |
TW200737359A (en) | 2007-10-01 |
TWI414023B (zh) | 2013-11-01 |
JP2009526409A (ja) | 2009-07-16 |
US7446001B2 (en) | 2008-11-04 |
CN101379614A (zh) | 2009-03-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5063352B2 (ja) | 高移動性バルク・シリコンpfet | |
JP5535486B2 (ja) | 絶縁体上に半導体が設けられた構造(soi)を有するボディコンタクト素子の形成方法及び装置 | |
JP4965080B2 (ja) | 半導体装置及びその製造方法 | |
US20080064173A1 (en) | Semiconductor device, cmos device and fabricating methods of the same | |
JP2006148077A (ja) | 延伸スペーサを利用した半導体デバイスおよびその形成方法 | |
CN107634056B (zh) | 半导体装置及其形成方法 | |
KR102449211B1 (ko) | 전계 효과 트랜지스터를 포함하는 반도체 소자 | |
JP2009055027A (ja) | Mosトランジスタの製造方法、および、これにより製造されたmosトランジスタ | |
JPWO2008123491A1 (ja) | 電離衝突によるキャリア増倍を用いた半導体素子及びその作製方法 | |
JP2008071957A (ja) | 半導体装置及びその製造方法 | |
JP4519442B2 (ja) | Mosトランジスター及びその製造方法 | |
WO2023108789A1 (zh) | 一种半导体器件及其制造方法 | |
WO2018163605A1 (ja) | 半導体装置及び半導体装置の製造方法 | |
KR101544509B1 (ko) | 트랜지스터를 갖는 반도체소자의 제조방법 | |
JP4495073B2 (ja) | 半導体素子の製造方法 | |
JP2009266868A (ja) | Mosfetおよびmosfetの製造方法 | |
CN104241266B (zh) | 半导体整合装置 | |
JP4573849B2 (ja) | 半導体装置の製造方法 | |
JP2519541B2 (ja) | 半導体装置 | |
CN111725138B (zh) | 一种半导体器件的制造方法 | |
WO2006109221A2 (en) | Lateral bipolar transistor | |
JP2005142475A (ja) | 半導体装置および半導体装置の製造方法 | |
KR100591124B1 (ko) | 반도체 소자 및 그의 제조 방법 | |
TWI553866B (zh) | 半導體裝置及其製造方法 | |
TWI521708B (zh) | 具有應變層植入絕緣溝槽之電晶體裝置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100121 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20100121 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120814 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120815 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20121114 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130430 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130729 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20131022 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140121 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140325 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140423 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5535486 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |