JP5519140B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP5519140B2 JP5519140B2 JP2008276394A JP2008276394A JP5519140B2 JP 5519140 B2 JP5519140 B2 JP 5519140B2 JP 2008276394 A JP2008276394 A JP 2008276394A JP 2008276394 A JP2008276394 A JP 2008276394A JP 5519140 B2 JP5519140 B2 JP 5519140B2
- Authority
- JP
- Japan
- Prior art keywords
- well
- impurity concentration
- semiconductor substrate
- conductivity type
- peak position
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 116
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000012535 impurity Substances 0.000 claims description 91
- 239000000758 substrate Substances 0.000 claims description 83
- 238000005468 ion implantation Methods 0.000 claims description 30
- 239000000463 material Substances 0.000 claims description 24
- 239000010410 layer Substances 0.000 claims description 22
- 238000009792 diffusion process Methods 0.000 claims description 19
- 239000002344 surface layer Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 9
- 238000002955 isolation Methods 0.000 description 19
- 229910004298 SiO 2 Inorganic materials 0.000 description 15
- 238000009826 distribution Methods 0.000 description 14
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 11
- 229910052796 boron Inorganic materials 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000005465 channeling Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910021486 amorphous silicon dioxide Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 231100000957 no side effect Toxicity 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Description
2、102 Nウェル(第1ウェル)
3、103 Nウェル(第1ウェル)
4、104 Pウェル(第2ウェル)
5、105 Pウェル(第3ウェル)
6、106 トレンチ分離絶縁膜
7、8、107、108 N+拡散層(拡散層)
9、10、109、110 深入りNウェル
11 Pウェル(第4ウェル)
Claims (7)
- 第1導電型の半導体基板と、
前記半導体基板の表層にて所定間隔をおいて配されるとともに、第1導電型の逆導電型の第2導電型の2つの第1ウェルと、
前記半導体基板の表層にて2つの前記第1ウェルの間に配されるとともに、前記半導体基板よりも不純物濃度が高い第1導電型の第2ウェルと、
前記半導体基板中であって少なくとも前記第2ウェルの不純物濃度のピーク位置よりも下方の領域に不純物濃度のピーク位置が配されるとともに、前記半導体基板よりも不純物濃度が高く、かつ、前記第2ウェルよりも不純物濃度が低い第1導電型の第3ウェルと、
前記半導体基板中であって少なくとも前記第3ウェルの不純物濃度のピーク位置よりも下方の領域に不純物濃度のピーク位置が配されるとともに、前記半導体基板よりも不純物濃度が高く、かつ、前記第2ウェルよりも不純物濃度が低い第1導電型の第4ウェルと、
を備え、
前記第1ウェル上に配されるとともに、前記第1ウェルよりも不純物濃度が高い第2導電型の拡散層を備えることを特徴とする半導体装置。 - 前記第3ウェルの不純物濃度のピーク位置は、前記半導体基板中であって少なくとも前記第2ウェル及び前記第1ウェルの不純物濃度のピーク位置よりも下方の領域に配されることを特徴とする請求項1記載の半導体装置。
- 前記第3ウェルの不純物濃度のピーク位置は、前記第2ウェルの不純物濃度のピーク位置よりも0.3μm以上かつ0.8μm以下の範囲で深く、
前記第4ウェルの不純物濃度のピーク位置は、前記第3ウェルの不純物濃度のピーク位置よりも0.3μm以上かつ0.9μm以下の範囲で深いことを特徴とする請求項1又は2記載の半導体装置。 - 前記第3ウェル及び前記第4ウェルの不純物濃度は、2つの前記第1ウェルの間の間隔が狭くなるに従い高く設定されていることを特徴とする請求項1乃至3のいずれか一に記載の半導体装置。
- 前記第3ウェル及び前記第4ウェルは、イオン注入により形成された領域であることを特徴とする請求項1乃至4のいずれか一に記載の半導体装置。
- 第1導電型の半導体基板全面にイオン注入を行うことで第1導電型の第4ウェルを形成する工程と、
前記半導体基板全面にイオン注入を行うことで前記第4ウェルの不純物濃度のピーク位置よりも浅い位置に不純物濃度のピーク位置が配されるように第1導電型の第3ウェルを形成する工程と、
前記第3ウェルの不純物濃度のピーク位置よりも浅い前記半導体基板の表層部の所定領域に不純物濃度のピーク位置が配されるように第1導電型の第2ウェルを形成する工程と、
前記第3ウェルの不純物濃度のピーク位置よりも浅い前記半導体基板の表層部の前記第2ウェルの両隣に不純物濃度のピーク位置が配されるように第1導電型の逆導電型の第2導電型の第1ウェルを形成する工程と、
前記第1ウェル上に、前記第1ウェルの不純物濃度よりも高い第2導電型の拡散層を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 第1導電型の半導体基板表面に所定領域に開口部を有するマスク材を形成する工程と、
前記マスク材をマスクとして前記半導体基板にイオン注入を行うことで第1導電型の第4ウェルを形成する工程と、
前記マスク材をマスクとして前記半導体基板にイオン注入を行うことで前記第4ウェルの不純物濃度のピーク位置よりも浅い位置に不純物濃度のピーク位置が配されるように第1導電型の第3ウェルを形成する工程と、
前記マスク材をマスクとして前記第3ウェルの不純物濃度のピーク位置よりも浅い前記半導体基板の表層部に不純物濃度のピーク位置が配されるように第1導電型の第2ウェルを形成する工程と、
前記マスク材を除去した後、前記第3ウェルの不純物濃度のピーク位置よりも浅い前記半導体基板の表層部の前記第2ウェルの両隣に不純物濃度のピーク位置が配されるように第1導電型の逆導電型の第2導電型の第1ウェルを形成する工程と、
前記第1ウェル上に、前記第1ウェルの不純物濃度よりも高い第2導電型の拡散層を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008276394A JP5519140B2 (ja) | 2008-10-28 | 2008-10-28 | 半導体装置及びその製造方法 |
US12/606,634 US8148774B2 (en) | 2008-10-28 | 2009-10-27 | Method of fabricating semiconductor device with a high breakdown voltage between neighboring wells |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008276394A JP5519140B2 (ja) | 2008-10-28 | 2008-10-28 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010108959A JP2010108959A (ja) | 2010-05-13 |
JP5519140B2 true JP5519140B2 (ja) | 2014-06-11 |
Family
ID=42116665
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008276394A Expired - Fee Related JP5519140B2 (ja) | 2008-10-28 | 2008-10-28 | 半導体装置及びその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8148774B2 (ja) |
JP (1) | JP5519140B2 (ja) |
Families Citing this family (54)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8273617B2 (en) | 2009-09-30 | 2012-09-25 | Suvolta, Inc. | Electronic devices and systems, and methods for making and using the same |
US8421162B2 (en) | 2009-09-30 | 2013-04-16 | Suvolta, Inc. | Advanced transistors with punch through suppression |
US8530286B2 (en) | 2010-04-12 | 2013-09-10 | Suvolta, Inc. | Low power semiconductor transistor structure and method of fabrication thereof |
US8569128B2 (en) | 2010-06-21 | 2013-10-29 | Suvolta, Inc. | Semiconductor structure and method of fabrication thereof with mixed metal types |
US8759872B2 (en) | 2010-06-22 | 2014-06-24 | Suvolta, Inc. | Transistor with threshold voltage set notch and method of fabrication thereof |
US8377783B2 (en) | 2010-09-30 | 2013-02-19 | Suvolta, Inc. | Method for reducing punch-through in a transistor device |
US8404551B2 (en) | 2010-12-03 | 2013-03-26 | Suvolta, Inc. | Source/drain extension control for advanced transistors |
US8461875B1 (en) | 2011-02-18 | 2013-06-11 | Suvolta, Inc. | Digital circuits having improved transistors, and methods therefor |
US8525271B2 (en) | 2011-03-03 | 2013-09-03 | Suvolta, Inc. | Semiconductor structure with improved channel stack and method for fabrication thereof |
US8400219B2 (en) | 2011-03-24 | 2013-03-19 | Suvolta, Inc. | Analog circuits having improved transistors, and methods therefor |
US8748270B1 (en) | 2011-03-30 | 2014-06-10 | Suvolta, Inc. | Process for manufacturing an improved analog transistor |
US8796048B1 (en) | 2011-05-11 | 2014-08-05 | Suvolta, Inc. | Monitoring and measurement of thin film layers |
US8999861B1 (en) | 2011-05-11 | 2015-04-07 | Suvolta, Inc. | Semiconductor structure with substitutional boron and method for fabrication thereof |
US8811068B1 (en) | 2011-05-13 | 2014-08-19 | Suvolta, Inc. | Integrated circuit devices and methods |
US8569156B1 (en) | 2011-05-16 | 2013-10-29 | Suvolta, Inc. | Reducing or eliminating pre-amorphization in transistor manufacture |
US8735987B1 (en) | 2011-06-06 | 2014-05-27 | Suvolta, Inc. | CMOS gate stack structures and processes |
US8995204B2 (en) | 2011-06-23 | 2015-03-31 | Suvolta, Inc. | Circuit devices and methods having adjustable transistor body bias |
US8629016B1 (en) | 2011-07-26 | 2014-01-14 | Suvolta, Inc. | Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer |
US8748986B1 (en) | 2011-08-05 | 2014-06-10 | Suvolta, Inc. | Electronic device with controlled threshold voltage |
KR101891373B1 (ko) | 2011-08-05 | 2018-08-24 | 엠아이이 후지쯔 세미컨덕터 리미티드 | 핀 구조물을 갖는 반도체 디바이스 및 그 제조 방법 |
US8645878B1 (en) | 2011-08-23 | 2014-02-04 | Suvolta, Inc. | Porting a circuit design from a first semiconductor process to a second semiconductor process |
US8614128B1 (en) | 2011-08-23 | 2013-12-24 | Suvolta, Inc. | CMOS structures and processes based on selective thinning |
US8713511B1 (en) | 2011-09-16 | 2014-04-29 | Suvolta, Inc. | Tools and methods for yield-aware semiconductor manufacturing process target generation |
US9236466B1 (en) | 2011-10-07 | 2016-01-12 | Mie Fujitsu Semiconductor Limited | Analog circuits having improved insulated gate transistors, and methods therefor |
US8895327B1 (en) | 2011-12-09 | 2014-11-25 | Suvolta, Inc. | Tipless transistors, short-tip transistors, and methods and circuits therefor |
US8819603B1 (en) | 2011-12-15 | 2014-08-26 | Suvolta, Inc. | Memory circuits and methods of making and designing the same |
US8883600B1 (en) | 2011-12-22 | 2014-11-11 | Suvolta, Inc. | Transistor having reduced junction leakage and methods of forming thereof |
US8599623B1 (en) | 2011-12-23 | 2013-12-03 | Suvolta, Inc. | Circuits and methods for measuring circuit elements in an integrated circuit device |
US8877619B1 (en) | 2012-01-23 | 2014-11-04 | Suvolta, Inc. | Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom |
US8970289B1 (en) | 2012-01-23 | 2015-03-03 | Suvolta, Inc. | Circuits and devices for generating bi-directional body bias voltages, and methods therefor |
US9093550B1 (en) | 2012-01-31 | 2015-07-28 | Mie Fujitsu Semiconductor Limited | Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same |
US9406567B1 (en) | 2012-02-28 | 2016-08-02 | Mie Fujitsu Semiconductor Limited | Method for fabricating multiple transistor devices on a substrate with varying threshold voltages |
US8863064B1 (en) | 2012-03-23 | 2014-10-14 | Suvolta, Inc. | SRAM cell layout structure and devices therefrom |
US9299698B2 (en) | 2012-06-27 | 2016-03-29 | Mie Fujitsu Semiconductor Limited | Semiconductor structure with multiple transistors having various threshold voltages |
US8637955B1 (en) | 2012-08-31 | 2014-01-28 | Suvolta, Inc. | Semiconductor structure with reduced junction leakage and method of fabrication thereof |
US9112057B1 (en) | 2012-09-18 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Semiconductor devices with dopant migration suppression and method of fabrication thereof |
US9041126B2 (en) | 2012-09-21 | 2015-05-26 | Mie Fujitsu Semiconductor Limited | Deeply depleted MOS transistors having a screening layer and methods thereof |
CN104854698A (zh) | 2012-10-31 | 2015-08-19 | 三重富士通半导体有限责任公司 | 具有低变化晶体管***电路的dram型器件以及相关方法 |
US8816754B1 (en) | 2012-11-02 | 2014-08-26 | Suvolta, Inc. | Body bias circuits and methods |
US9093997B1 (en) | 2012-11-15 | 2015-07-28 | Mie Fujitsu Semiconductor Limited | Slew based process and bias monitors and related methods |
US9070477B1 (en) | 2012-12-12 | 2015-06-30 | Mie Fujitsu Semiconductor Limited | Bit interleaved low voltage static random access memory (SRAM) and related methods |
US9112484B1 (en) | 2012-12-20 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Integrated circuit process and bias monitors and related methods |
US9268885B1 (en) | 2013-02-28 | 2016-02-23 | Mie Fujitsu Semiconductor Limited | Integrated circuit device methods and models with predicted device metric variations |
US8994415B1 (en) | 2013-03-01 | 2015-03-31 | Suvolta, Inc. | Multiple VDD clock buffer |
US8988153B1 (en) | 2013-03-09 | 2015-03-24 | Suvolta, Inc. | Ring oscillator with NMOS or PMOS variation insensitivity |
US9299801B1 (en) | 2013-03-14 | 2016-03-29 | Mie Fujitsu Semiconductor Limited | Method for fabricating a transistor device with a tuned dopant profile |
US9449967B1 (en) | 2013-03-15 | 2016-09-20 | Fujitsu Semiconductor Limited | Transistor array structure |
US9112495B1 (en) | 2013-03-15 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Integrated circuit device body bias circuits and methods |
US9478571B1 (en) | 2013-05-24 | 2016-10-25 | Mie Fujitsu Semiconductor Limited | Buried channel deeply depleted channel transistor |
US8976575B1 (en) | 2013-08-29 | 2015-03-10 | Suvolta, Inc. | SRAM performance monitor |
US9710006B2 (en) | 2014-07-25 | 2017-07-18 | Mie Fujitsu Semiconductor Limited | Power up body bias circuits and methods |
US9319013B2 (en) | 2014-08-19 | 2016-04-19 | Mie Fujitsu Semiconductor Limited | Operational amplifier input offset correction with transistor threshold voltage adjustment |
WO2018030008A1 (ja) * | 2016-08-12 | 2018-02-15 | 富士電機株式会社 | 半導体集積回路 |
US10020386B1 (en) * | 2017-03-09 | 2018-07-10 | Globalfoundries Inc. | High-voltage and analog bipolar devices |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5034337A (en) * | 1989-02-10 | 1991-07-23 | Texas Instruments Incorporated | Method of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devices |
JPH0567753A (ja) * | 1991-04-17 | 1993-03-19 | Mitsubishi Electric Corp | 二重構造ウエルを有する半導体装置およびその製造方法 |
JP2965783B2 (ja) * | 1991-07-17 | 1999-10-18 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
US6225674B1 (en) * | 1999-04-02 | 2001-05-01 | Motorola, Inc. | Semiconductor structure and method of manufacture |
JP2002289704A (ja) | 2001-03-23 | 2002-10-04 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2003060073A (ja) * | 2001-08-10 | 2003-02-28 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US20080197408A1 (en) * | 2002-08-14 | 2008-08-21 | Advanced Analogic Technologies, Inc. | Isolated quasi-vertical DMOS transistor |
JP2004235475A (ja) * | 2003-01-30 | 2004-08-19 | Nec Electronics Corp | 半導体装置 |
US8030731B2 (en) * | 2007-03-28 | 2011-10-04 | Advanced Analogic Technologies, Inc. | Isolated rectifier diode |
-
2008
- 2008-10-28 JP JP2008276394A patent/JP5519140B2/ja not_active Expired - Fee Related
-
2009
- 2009-10-27 US US12/606,634 patent/US8148774B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US8148774B2 (en) | 2012-04-03 |
JP2010108959A (ja) | 2010-05-13 |
US20100102420A1 (en) | 2010-04-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5519140B2 (ja) | 半導体装置及びその製造方法 | |
JP5703790B2 (ja) | 半導体装置及びその製造方法 | |
JP2009021502A (ja) | 半導体装置およびその製造方法 | |
JP2008084996A (ja) | 高耐圧トランジスタ、これを用いた半導体装置及び高耐圧トランジスタの製造方法 | |
JP2014203851A (ja) | 半導体装置及びその製造方法 | |
JP2006013450A (ja) | 半導体装置およびその製造方法 | |
KR100672156B1 (ko) | 반도체 소자의 소자분리막 및 이의 형성방법 | |
CN1316630C (zh) | 半导体器件及其制造方法 | |
KR101477606B1 (ko) | 반도체 구조의 형성방법 | |
KR20060017985A (ko) | 반도체 소자 및 그 제조방법 | |
JP4744103B2 (ja) | 抵抗素子を含む半導体装置及びその製造方法 | |
JP5547986B2 (ja) | 半導体装置およびその製造方法 | |
JP2009135493A (ja) | 静電気放電保護素子及びその製造方法 | |
KR101450436B1 (ko) | 반도체 소자의 웰 형성 방법 | |
US6664602B2 (en) | Semiconductor device and method of manufacturing the same | |
JP2006060173A (ja) | 半導体装置及びその製造方法 | |
JP2015005639A (ja) | 半導体装置 | |
JP6243748B2 (ja) | 半導体素子及びその製造方法 | |
JP2010232361A (ja) | 半導体記憶装置 | |
KR20060019367A (ko) | 보이드가 없는 게이트 전극을 구비한 mos 트랜지스터의제조방법 | |
JP2006324375A (ja) | 半導体装置及びその製造方法 | |
JP4048183B2 (ja) | 半導体装置の製造方法 | |
JP6619187B2 (ja) | 半導体装置および半導体装置の製造方法 | |
KR101097982B1 (ko) | 반도체 소자 및 그 제조방법 | |
JP2005109064A (ja) | 半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20110926 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130612 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130625 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130819 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140401 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140403 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5519140 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |