JP5489992B2 - 電界効果トランジスタ・デバイスの製造方法 - Google Patents
電界効果トランジスタ・デバイスの製造方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 53
- 230000005669 field effect Effects 0.000 title claims description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 29
- 125000006850 spacer group Chemical group 0.000 claims description 46
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 34
- 229910052710 silicon Inorganic materials 0.000 claims description 34
- 239000010703 silicon Substances 0.000 claims description 34
- 150000004767 nitrides Chemical class 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 23
- 239000000945 filler Substances 0.000 claims description 22
- 230000008569 process Effects 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 20
- 238000001020 plasma etching Methods 0.000 claims description 19
- 238000001459 lithography Methods 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 238000011049 filling Methods 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- 239000003989 dielectric material Substances 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 238000000609 electron-beam lithography Methods 0.000 claims 1
- 238000005516 engineering process Methods 0.000 description 22
- 239000011295 pitch Substances 0.000 description 22
- 230000015572 biosynthetic process Effects 0.000 description 13
- 238000001878 scanning electron micrograph Methods 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 10
- 230000003071 parasitic effect Effects 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 230000009977 dual effect Effects 0.000 description 5
- 238000005259 measurement Methods 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000002860 competitive effect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000011835 investigation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- PCLURTMBFDTLSK-UHFFFAOYSA-N nickel platinum Chemical compound [Ni].[Pt] PCLURTMBFDTLSK-UHFFFAOYSA-N 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 229910052720 vanadium Inorganic materials 0.000 description 2
- 238000003631 wet chemical etching Methods 0.000 description 2
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
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- 238000004140 cleaning Methods 0.000 description 1
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- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
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- 230000037431 insertion Effects 0.000 description 1
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- 150000002500 ions Chemical class 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
- H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/902—Specified use of nanostructure
- Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
- Y10S977/936—Specified use of nanostructure for electronic or optoelectronic application in a transistor or 3-terminal device
- Y10S977/938—Field effect transistors, FETS, with nanowire- or nanotube-channel region
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- Engineering & Computer Science (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
Description
Claims (13)
- 電界効果トランジスタ・デバイスを製造する方法であって、
基板上にシリコン層を形成するステップと、
前記シリコン層上で複数のフィンを形成するためのフィン・リソグラフィー・ハードマスクをパターニングするステップと、
前記フィン・リソグラフィー・ハードマスクの中央部分の上面及び側面を覆うダミー・ゲート構造を配置するステップと、
前記ダミー・ゲート構造の周りにフィラー層を堆積させるステップと、
前記ダミー・ゲート構造を除去して、前記デバイスのソース領域およびドレイン領域から前記デバイスのフィン領域を区別する、前記フィン・リソグラフィー・ハードマスクの前記中央部分の上を中心とするトレンチを、前記フィラー層に形成するステップと、
前記フィン領域内の前記フィン・リソグラフィー・ハードマスクを使用して、前記シリコン層をエッチングして複数のフィンを形成するステップと、
前記トレンチをゲート材料で充填して、前記フィンの上にゲート・スタックを形成するステップと、
前記フィラー層を除去して、前記デバイスの前記ソース領域および前記ドレイン領域を露出するステップとを順次実行することを含み、
前記ソース領域および前記ドレイン領域は無傷であって前記ゲート・スタックと自己整合させられている、方法。 - 前記トレンチを前記ゲート材料で充填して前記ゲート・スタックを形成するステップの前に、前記フィン領域から前記フィン・リソグラフィー・ハードマスクを除去するステップをさらに含む、請求項1に記載の方法。
- 前記トレンチの1つまたはそれ以上の側壁と前記フィンの1つまたはそれ以上の表面との少なくとも一部分の上で前記トレンチ内に窒化物スペーサ材料を堆積させるステップと、
50パーセントと80パーセントとの間の時限オーバー・エッチングを伴う、反応イオン・エッチングを使用して、前記フィンの前記表面から前記スペーサ材料を選択的に除去するステップと、をさらに含む、請求項1または2に記載の方法。 - 前記フィンの表面と比べて前記トレンチの側壁の上により多くのゲート誘電体材料を設けるために差分誘電体成長を用いて前記トレンチの前記側壁のうちの1つまたはそれ以上と前記フィンの1つまたはそれ以上の前記表面との少なくとも一部分の上に前記ゲート誘電体材料を設けるステップをさらに含む、請求項1乃至3のいずれかに記載の方法。
- 前記ゲート・スタックはフレア形部分を有し、
前記ゲートから前記フレア形部分を除去するステップをさらに含む、請求項1乃至4のいずれかに記載の方法。 - 前記ダミー・ゲート構造は多結晶シリコンを含み、
100ナノメートルと150ナノメートルの間の高さと、30ナノメートルと50ナノメートルの間の長さとを有する、請求項1乃至5のいずれかに記載の方法。 - 前記ゲート・スタックは多結晶シリコン、金属および金属/多結晶シリコン・ハイブリッドのうちの1つまたはそれ以上を含む、請求項1乃至6のいずれかに記載の方法。
- 前記フィン・リソグラフィー・ハードマスクは、窒化物フィン・ハードマスク層と酸化物フィン・ハードマスク層とを含む二重ハードマスク構造である、請求項1乃至7のいずれかに記載の方法。
- 前記フィンはシリコン選択的反応イオン・エッチングを用いてエッチングされる、請求項1乃至8のいずれかに記載の方法。
- 前記ゲート・スタックはダマシン・プロセスを用いて前記トレンチ内に形成される、請求項1乃至9のいずれかに記載の方法。
- 前記フィン・リソグラフィー・ハードマスクをパターニングする前記ステップは、
電子線リソグラフィーを用いてレジスト材料スタックをパターニングするステップと、
前記レジスト材料スタックのパターンを炭素ベースのレジストに転写するステップと、
反応イオン・エッチングによって前記転写後の炭素ベースのレジストを用いて前記フィン・リソグラフィー・ハードマスクをパターニングするステップと、をさらに含む、請求項1乃至10のいずれかに記載の方法。 - ホウ素およびリンのうちの1つまたはそれ以上を含むドーピング材で前記ゲート・スタックをドープするステップをさらに含む、請求項1乃至11のいずれかに記載の方法。
- 前記ソース領域および前記ドレイン領域のうちの1つまたはそれ以上の上にシリサイド領域を形成するステップをさらに含む、請求項1乃至12のいずれかに記載の方法。
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US11/765,931 | 2007-06-20 | ||
US11/765,931 US7923337B2 (en) | 2007-06-20 | 2007-06-20 | Fin field effect transistor devices with self-aligned source and drain regions |
PCT/EP2008/056733 WO2008155208A1 (en) | 2007-06-20 | 2008-06-02 | Fin field effect transistor devices with self-aligned source and drain regions |
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EP (1) | EP2168151A1 (ja) |
JP (1) | JP5489992B2 (ja) |
KR (2) | KR20120079487A (ja) |
TW (1) | TW200908160A (ja) |
WO (1) | WO2008155208A1 (ja) |
Cited By (1)
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US9768255B2 (en) | 2015-04-14 | 2017-09-19 | Samsung Electronics Co., Ltd. | Semiconductor devices including contact structures that partially overlap silicide layers |
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FR2707169B1 (fr) * | 1993-06-04 | 1995-09-01 | Pasteur Institut | Antigène cellulaire CD26 impliqué dans l'infection par un rétrovirus hiv. nouveaux inhibiteurs de l'infection par HIV. * (Dipeptidyl-peptidase IV). |
FR2707170A1 (fr) * | 1993-06-04 | 1995-01-13 | Pasteur Institut | Expression des récepteurs CD4 et CD26 dans des cellules recombinantes, inhibiteurs du récepteur CD26. |
US7446352B2 (en) | 2006-03-09 | 2008-11-04 | Tela Innovations, Inc. | Dynamic array architecture |
US8225239B2 (en) | 2006-03-09 | 2012-07-17 | Tela Innovations, Inc. | Methods for defining and utilizing sub-resolution features in linear topology |
US8225261B2 (en) | 2006-03-09 | 2012-07-17 | Tela Innovations, Inc. | Methods for defining contact grid in dynamic array architecture |
US8653857B2 (en) | 2006-03-09 | 2014-02-18 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
US7908578B2 (en) | 2007-08-02 | 2011-03-15 | Tela Innovations, Inc. | Methods for designing semiconductor device with dynamic array section |
US7763534B2 (en) | 2007-10-26 | 2010-07-27 | Tela Innovations, Inc. | Methods, structures and designs for self-aligning local interconnects used in integrated circuits |
US8839175B2 (en) | 2006-03-09 | 2014-09-16 | Tela Innovations, Inc. | Scalable meta-data objects |
US7956421B2 (en) | 2008-03-13 | 2011-06-07 | Tela Innovations, Inc. | Cross-coupled transistor layouts in restricted gate level layout architecture |
US8247846B2 (en) | 2006-03-09 | 2012-08-21 | Tela Innovations, Inc. | Oversized contacts and vias in semiconductor chip defined by linearly constrained topology |
US9035359B2 (en) | 2006-03-09 | 2015-05-19 | Tela Innovations, Inc. | Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods |
US9230910B2 (en) | 2006-03-09 | 2016-01-05 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
US8541879B2 (en) | 2007-12-13 | 2013-09-24 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US9009641B2 (en) | 2006-03-09 | 2015-04-14 | Tela Innovations, Inc. | Circuits with linear finfet structures |
US8448102B2 (en) | 2006-03-09 | 2013-05-21 | Tela Innovations, Inc. | Optimizing layout of irregular structures in regular layout context |
US8245180B2 (en) | 2006-03-09 | 2012-08-14 | Tela Innovations, Inc. | Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same |
US9563733B2 (en) | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
US8658542B2 (en) | 2006-03-09 | 2014-02-25 | Tela Innovations, Inc. | Coarse grid design methods and structures |
US8286107B2 (en) | 2007-02-20 | 2012-10-09 | Tela Innovations, Inc. | Methods and systems for process compensation technique acceleration |
US8667443B2 (en) | 2007-03-05 | 2014-03-04 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
US8030163B2 (en) * | 2007-12-26 | 2011-10-04 | Intel Corporation | Reducing external resistance of a multi-gate device using spacer processing techniques |
US8453094B2 (en) | 2008-01-31 | 2013-05-28 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
US7939443B2 (en) | 2008-03-27 | 2011-05-10 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
JP4518180B2 (ja) * | 2008-04-16 | 2010-08-04 | ソニー株式会社 | 半導体装置、および、その製造方法 |
US8631383B2 (en) * | 2008-06-30 | 2014-01-14 | Qimonda Ag | Integrated circuits, standard cells, and methods for generating a layout of an integrated circuit |
SG192532A1 (en) | 2008-07-16 | 2013-08-30 | Tela Innovations Inc | Methods for cell phasing and placement in dynamic array architecture and implementation of the same |
US9122832B2 (en) | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
US8153493B2 (en) * | 2008-08-28 | 2012-04-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET process compatible native transistor |
US8120073B2 (en) * | 2008-12-31 | 2012-02-21 | Intel Corporation | Trigate transistor having extended metal gate electrode |
US7893492B2 (en) * | 2009-02-17 | 2011-02-22 | International Business Machines Corporation | Nanowire mesh device and method of fabricating same |
US8331068B2 (en) * | 2009-02-19 | 2012-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | ESD protection for FinFETs |
JP2010258124A (ja) * | 2009-04-23 | 2010-11-11 | Renesas Electronics Corp | 半導体装置及び半導体装置の製造方法 |
US8422273B2 (en) | 2009-05-21 | 2013-04-16 | International Business Machines Corporation | Nanowire mesh FET with multiple threshold voltages |
US8053318B2 (en) * | 2009-06-25 | 2011-11-08 | International Business Machines Corporation | FET with replacement gate structure and method of fabricating the same |
US8472227B2 (en) * | 2010-01-27 | 2013-06-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits and methods for forming the same |
US8661392B2 (en) | 2009-10-13 | 2014-02-25 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the Same |
US20110101506A1 (en) * | 2009-10-29 | 2011-05-05 | International Business Machines Corporation | Stress Memorization Technique Using Silicon Spacer |
US8399314B2 (en) | 2010-03-25 | 2013-03-19 | International Business Machines Corporation | p-FET with a strained nanowire channel and embedded SiGe source and drain stressors |
DE102010029527B4 (de) | 2010-05-31 | 2012-04-05 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Verfahren zur Herstellung eines selbstjustierenden Transistors mit Mehrfachgate auf einem Vollsubstrat |
US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
DE102010064283B4 (de) * | 2010-12-28 | 2012-12-27 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | Verfahren zur Herstellung eines selbstjustierten Steg-Transistors auf einem Vollsubstrat durch eine späte Stegätzung |
DE102011003232B4 (de) * | 2011-01-27 | 2013-03-28 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | Herstellverfahren für Metallgateelektrodenstrukturen mit großem ε, die durch ein Austauschgateverfahren auf der Grundlage einer verbesserten Ebenheit von Platzhaltermaterialien hergestellt sind |
US20120306000A1 (en) * | 2011-05-31 | 2012-12-06 | International Business Machines Corporation | Formation of Field Effect Transistor Devices |
KR101797961B1 (ko) * | 2011-06-09 | 2017-11-16 | 삼성전자주식회사 | 반도체 장치의 제조 방법 |
US8637359B2 (en) | 2011-06-10 | 2014-01-28 | International Business Machines Corporation | Fin-last replacement metal gate FinFET process |
US8441072B2 (en) * | 2011-09-02 | 2013-05-14 | United Microelectronics Corp. | Non-planar semiconductor structure and fabrication method thereof |
US8723272B2 (en) * | 2011-10-04 | 2014-05-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and method of manufacturing same |
US9018090B2 (en) | 2011-10-10 | 2015-04-28 | International Business Machines Corporation | Borderless self-aligned metal contact patterning using printable dielectric materials |
US9368502B2 (en) | 2011-10-17 | 2016-06-14 | GlogalFoundries, Inc. | Replacement gate multigate transistor for embedded DRAM |
US8420459B1 (en) | 2011-10-20 | 2013-04-16 | International Business Machines Corporation | Bulk fin-field effect transistors with well defined isolation |
US8580624B2 (en) * | 2011-11-01 | 2013-11-12 | International Business Machines Corporation | Nanowire FET and finFET hybrid technology |
US8569125B2 (en) | 2011-11-30 | 2013-10-29 | International Business Machines Corporation | FinFET with improved gate planarity |
US8563376B2 (en) | 2011-12-16 | 2013-10-22 | International Business Machines Corporation | Hybrid CMOS nanowire mesh device and bulk CMOS device |
US8709888B2 (en) | 2011-12-16 | 2014-04-29 | International Business Machines Corporation | Hybrid CMOS nanowire mesh device and PDSOI device |
US8722472B2 (en) | 2011-12-16 | 2014-05-13 | International Business Machines Corporation | Hybrid CMOS nanowire mesh device and FINFET device |
WO2013095474A1 (en) * | 2011-12-21 | 2013-06-27 | Intel Corporation | Methods for forming fins for metal oxide semiconductor device structures |
CN113540080A (zh) | 2011-12-22 | 2021-10-22 | 英特尔公司 | 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法 |
US9048260B2 (en) | 2011-12-31 | 2015-06-02 | Intel Corporation | Method of forming a semiconductor device with tall fins and using hard mask etch stops |
US8643120B2 (en) * | 2012-01-06 | 2014-02-04 | International Business Machines Corporation | FinFET with fully silicided gate |
US8759184B2 (en) * | 2012-01-09 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs and the methods for forming the same |
US8557648B2 (en) | 2012-01-11 | 2013-10-15 | International Business Machines Corporation | Recessed source and drain regions for FinFETs |
US8659097B2 (en) | 2012-01-16 | 2014-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Control fin heights in FinFET structures |
US8697523B2 (en) | 2012-02-06 | 2014-04-15 | International Business Machines Corporation | Integration of SMT in replacement gate FINFET process flow |
US8637371B2 (en) | 2012-02-16 | 2014-01-28 | International Business Machines Corporation | Non-planar MOSFET structures with asymmetric recessed source drains and methods for making the same |
KR101876793B1 (ko) * | 2012-02-27 | 2018-07-11 | 삼성전자주식회사 | 전계효과 트랜지스터 및 그 제조 방법 |
US8987835B2 (en) | 2012-03-27 | 2015-03-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET with a buried semiconductor material between two fins |
US8652932B2 (en) | 2012-04-17 | 2014-02-18 | International Business Machines Corporation | Semiconductor devices having fin structures, and methods of forming semiconductor devices having fin structures |
US8946782B2 (en) | 2012-04-19 | 2015-02-03 | International Business Machines Corporation | Method for keyhole repair in replacement metal gate integration through the use of a printable dielectric |
CN102646643B (zh) * | 2012-05-03 | 2014-03-12 | 上海华力微电子有限公司 | 基于SOI的积累型Si-NWFET制备方法 |
CN102646642B (zh) * | 2012-05-03 | 2014-01-29 | 上海华力微电子有限公司 | 基于SOI的后栅型积累模式Si-NWFET制备方法 |
US8796812B2 (en) | 2012-07-30 | 2014-08-05 | International Business Machines Corporation | Self-aligned trench over fin |
US8754527B2 (en) | 2012-07-31 | 2014-06-17 | International Business Machines Corporation | Self aligned borderless contact |
US8669167B1 (en) | 2012-08-28 | 2014-03-11 | International Business Machines Corporation | Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices |
US8987093B2 (en) * | 2012-09-20 | 2015-03-24 | International Business Machines Corporation | Multigate finFETs with epitaxially-grown merged source/drains |
US8765563B2 (en) * | 2012-09-28 | 2014-07-01 | Intel Corporation | Trench confined epitaxially grown device layer(s) |
US8969963B2 (en) | 2012-10-12 | 2015-03-03 | International Business Machines Corporation | Vertical source/drain junctions for a finFET including a plurality of fins |
US9177820B2 (en) * | 2012-10-24 | 2015-11-03 | Globalfoundries U.S. 2 Llc | Sub-lithographic semiconductor structures with non-constant pitch |
US8766363B2 (en) | 2012-11-07 | 2014-07-01 | International Business Machines Corporation | Method and structure for forming a localized SOI finFET |
US8987823B2 (en) | 2012-11-07 | 2015-03-24 | International Business Machines Corporation | Method and structure for forming a localized SOI finFET |
US8799848B1 (en) * | 2013-01-15 | 2014-08-05 | International Business Machines Corporation | Methods for modeling of FinFET width quantization |
US8927397B2 (en) | 2013-02-07 | 2015-01-06 | International Business Machines Corporation | Diode structure and method for gate all around silicon nanowire technologies |
US9190419B2 (en) | 2013-02-07 | 2015-11-17 | International Business Machines Corporation | Diode structure and method for FINFET technologies |
US9006087B2 (en) | 2013-02-07 | 2015-04-14 | International Business Machines Corporation | Diode structure and method for wire-last nanomesh technologies |
US9368366B2 (en) | 2013-02-14 | 2016-06-14 | Asml Netherlands B.V. | Methods for providing spaced lithography features on a substrate by self-assembly of block copolymers |
US10121861B2 (en) | 2013-03-15 | 2018-11-06 | Intel Corporation | Nanowire transistor fabrication with hardmask layers |
US8969155B2 (en) | 2013-05-10 | 2015-03-03 | International Business Machines Corporation | Fin structure with varying isolation thickness |
US9793378B2 (en) | 2013-05-31 | 2017-10-17 | Stmicroelectronics, Inc. | Fin field effect transistor device with reduced overlap capacitance and enhanced mechanical stability |
US9209086B2 (en) | 2013-07-22 | 2015-12-08 | Globalfoundries Inc. | Low temperature salicide for replacement gate nanowires |
KR102072410B1 (ko) | 2013-08-07 | 2020-02-03 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
US9515163B2 (en) * | 2013-09-09 | 2016-12-06 | Globalfoundries Inc. | Methods of forming FinFET semiconductor devices with self-aligned contact elements using a replacement gate process and the resulting devices |
KR102136234B1 (ko) | 2013-10-03 | 2020-07-21 | 인텔 코포레이션 | 나노와이어 트랜지스터들을 위한 내부 스페이서들 및 그 제조 방법 |
CN104576380B (zh) * | 2013-10-13 | 2017-09-15 | 中国科学院微电子研究所 | 一种finfet制造方法 |
CN104576386B (zh) * | 2013-10-14 | 2018-01-12 | 中国科学院微电子研究所 | 一种FinFET及其制造方法 |
KR102085525B1 (ko) | 2013-11-27 | 2020-03-09 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
EP2887399B1 (en) * | 2013-12-20 | 2017-08-30 | Imec | A method for manufacturing a transistor device and associated device |
CN104752224B (zh) * | 2013-12-31 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | FinFET器件及其制作方法 |
KR102224525B1 (ko) | 2014-02-03 | 2021-03-08 | 삼성전자주식회사 | 레이아웃 디자인 시스템, 이를 이용하여 제조한 반도체 장치 및 그 반도체 장치의 제조 방법 |
US9543407B2 (en) * | 2014-02-27 | 2017-01-10 | International Business Machines Corporation | Low-K spacer for RMG finFET formation |
US9209095B2 (en) * | 2014-04-04 | 2015-12-08 | International Business Machines Corporation | III-V, Ge, or SiGe fin base lateral bipolar transistor structure and method |
CN105225951B (zh) | 2014-05-30 | 2018-08-10 | 中芯国际集成电路制造(上海)有限公司 | 鳍式场效应晶体管的形成方法 |
US9443978B2 (en) | 2014-07-14 | 2016-09-13 | Samsung Electronics Co., Ltd. | Semiconductor device having gate-all-around transistor and method of manufacturing the same |
US9659827B2 (en) | 2014-07-21 | 2017-05-23 | Samsung Electronics Co., Ltd. | Methods of manufacturing semiconductor devices by forming source/drain regions before gate electrode separation |
KR102202753B1 (ko) | 2014-08-11 | 2021-01-14 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
CN105470133B (zh) * | 2014-09-06 | 2018-07-31 | 中国科学院微电子研究所 | 半导体器件制造方法 |
KR102217246B1 (ko) | 2014-11-12 | 2021-02-18 | 삼성전자주식회사 | 집적회로 소자 및 그 제조 방법 |
US9985112B2 (en) | 2015-02-06 | 2018-05-29 | International Business Machines Corporation | Sloped finFET with methods of forming same |
US9443738B2 (en) * | 2015-02-06 | 2016-09-13 | Globalfoundries Inc. | Integrated circuits with middle of line capacitance reduction in self-aligned contact process flow and fabrication methods |
US9496338B2 (en) | 2015-03-17 | 2016-11-15 | International Business Machines Corporation | Wire-last gate-all-around nanowire FET |
KR102317646B1 (ko) | 2015-04-14 | 2021-10-27 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
US10269968B2 (en) * | 2015-06-03 | 2019-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including fin structures and manufacturing method thereof |
US10170608B2 (en) | 2015-06-30 | 2019-01-01 | International Business Machines Corporation | Internal spacer formation from selective oxidation for fin-first wire-last replacement gate-all-around nanowire FET |
US9431521B1 (en) * | 2015-09-18 | 2016-08-30 | International Business Machines Corporation | Stress memorization technique for strain coupling enhancement in bulk finFET device |
US9768272B2 (en) | 2015-09-30 | 2017-09-19 | International Business Machines Corporation | Replacement gate FinFET process using a sit process to define source/drain regions, gate spacers and a gate cavity |
US10177143B2 (en) | 2015-10-28 | 2019-01-08 | Taiwan Semiconductor Manufacturing Company Limited | FinFET device and method for fabricating the same |
US9559192B1 (en) | 2015-11-18 | 2017-01-31 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device |
US9397006B1 (en) | 2015-12-04 | 2016-07-19 | International Business Machines Corporation | Co-integration of different fin pitches for logic and analog devices |
US9698251B1 (en) | 2016-09-26 | 2017-07-04 | International Business Machines Corporation | Fin reveal last for finfet |
US9754798B1 (en) | 2016-09-28 | 2017-09-05 | International Business Machines Corporation | Hybridization fin reveal for uniform fin reveal depth across different fin pitches |
US9985109B2 (en) | 2016-10-25 | 2018-05-29 | International Business Machines Corporation | FinFET with reduced parasitic capacitance |
US10269647B2 (en) * | 2017-01-20 | 2019-04-23 | Applied Materials, Inc. | Self-aligned EPI contact flow |
JP7026120B2 (ja) * | 2017-02-10 | 2022-02-25 | ノースイースタン ユニバーシティ | 化学機械的平坦化なしで製作されたナノ要素プリンティング用のダマシンテンプレート |
US10242867B2 (en) * | 2017-05-18 | 2019-03-26 | Globalfoundaries Inc. | Gate pickup method using metal selectivity |
US10374066B2 (en) | 2017-07-11 | 2019-08-06 | International Business Machines Corporation | Fin and shallow trench isolation replacement to prevent gate collapse |
US10134739B1 (en) | 2017-07-27 | 2018-11-20 | Globalfoundries Inc. | Memory array with buried bitlines below vertical field effect transistors of memory cells and a method of forming the memory array |
US10460993B2 (en) * | 2017-11-30 | 2019-10-29 | Intel Corporation | Fin cut and fin trim isolation for advanced integrated circuit structure fabrication |
DE102018126911A1 (de) | 2017-11-30 | 2019-06-06 | Intel Corporation | Gate-Schnitt und Finnentrimmisolation für fortschrittliche Integrierter-Schaltkreis-Struktur-Fertigung |
US10636894B2 (en) | 2018-03-09 | 2020-04-28 | Globalfoundries Inc. | Fin-type transistors with spacers on the gates |
US10529831B1 (en) | 2018-08-03 | 2020-01-07 | Globalfoundries Inc. | Methods, apparatus, and system for forming epitaxial formations with reduced risk of merging |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6118161A (en) * | 1997-04-30 | 2000-09-12 | Texas Instruments Incorporated | Self-aligned trenched-channel lateral-current-flow transistor |
JP4939690B2 (ja) * | 2001-01-30 | 2012-05-30 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US6635923B2 (en) | 2001-05-24 | 2003-10-21 | International Business Machines Corporation | Damascene double-gate MOSFET with vertical channel regions |
JP2003229575A (ja) * | 2002-02-04 | 2003-08-15 | Hitachi Ltd | 集積半導体装置及びその製造方法 |
US6974729B2 (en) * | 2002-07-16 | 2005-12-13 | Interuniversitair Microelektronica Centrum (Imec) | Integrated semiconductor fin device and a method for manufacturing such device |
US7358121B2 (en) | 2002-08-23 | 2008-04-15 | Intel Corporation | Tri-gate devices and methods of fabrication |
US6762483B1 (en) * | 2003-01-23 | 2004-07-13 | Advanced Micro Devices, Inc. | Narrow fin FinFET |
US6764884B1 (en) * | 2003-04-03 | 2004-07-20 | Advanced Micro Devices, Inc. | Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device |
US6911383B2 (en) * | 2003-06-26 | 2005-06-28 | International Business Machines Corporation | Hybrid planar and finFET CMOS devices |
US7013447B2 (en) | 2003-07-22 | 2006-03-14 | Freescale Semiconductor, Inc. | Method for converting a planar transistor design to a vertical double gate transistor design |
KR100487567B1 (ko) * | 2003-07-24 | 2005-05-03 | 삼성전자주식회사 | 핀 전계효과 트랜지스터 형성 방법 |
US6897098B2 (en) | 2003-07-28 | 2005-05-24 | Intel Corporation | Method of fabricating an ultra-narrow channel semiconductor device |
JP3860582B2 (ja) * | 2003-07-31 | 2006-12-20 | 株式会社東芝 | 半導体装置の製造方法 |
US6835618B1 (en) | 2003-08-05 | 2004-12-28 | Advanced Micro Devices, Inc. | Epitaxially grown fin for FinFET |
JP2005086024A (ja) * | 2003-09-09 | 2005-03-31 | Toshiba Corp | 半導体装置及びその製造方法 |
US6927104B2 (en) * | 2003-09-15 | 2005-08-09 | Chartered Semiconductor Manufacturing Ltd. | Method of forming double-gated silicon-on-insulator (SOI) transistors with corner rounding |
US7018551B2 (en) * | 2003-12-09 | 2006-03-28 | International Business Machines Corporation | Pull-back method of forming fins in FinFets |
US7186599B2 (en) | 2004-01-12 | 2007-03-06 | Advanced Micro Devices, Inc. | Narrow-body damascene tri-gate FinFET |
US7087471B2 (en) | 2004-03-15 | 2006-08-08 | International Business Machines Corporation | Locally thinned fins |
DE102004031385B4 (de) | 2004-06-29 | 2010-12-09 | Qimonda Ag | Verfahren zur Herstellung von Stegfeldeffekttransistoren in einer DRAM-Speicherzellenanordnung, Feldeffekttransistoren mit gekrümmtem Kanal und DRAM-Speicherzellenanordnung |
US6960509B1 (en) * | 2004-06-30 | 2005-11-01 | Freescale Semiconductor, Inc. | Method of fabricating three dimensional gate structure using oxygen diffusion |
US6949768B1 (en) * | 2004-10-18 | 2005-09-27 | International Business Machines Corporation | Planar substrate devices integrated with finfets and method of manufacture |
US7094650B2 (en) | 2005-01-20 | 2006-08-22 | Infineon Technologies Ag | Gate electrode for FinFET device |
US7488650B2 (en) * | 2005-02-18 | 2009-02-10 | Infineon Technologies Ag | Method of forming trench-gate electrode for FinFET device |
US20060249784A1 (en) | 2005-05-06 | 2006-11-09 | International Business Machines Corporation | Field effect transistor device including an array of channel elements and methods for forming |
EP1727194A1 (en) | 2005-05-27 | 2006-11-29 | Interuniversitair Microelektronica Centrum vzw ( IMEC) | Method for high topography patterning |
-
2007
- 2007-06-20 US US11/765,931 patent/US7923337B2/en active Active
-
2008
- 2008-06-02 KR KR1020127016721A patent/KR20120079487A/ko not_active Application Discontinuation
- 2008-06-02 JP JP2010512624A patent/JP5489992B2/ja active Active
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- 2009-08-20 US US12/544,939 patent/US8592280B2/en active Active
-
2013
- 2013-10-17 US US14/056,853 patent/US8890261B2/en active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9768255B2 (en) | 2015-04-14 | 2017-09-19 | Samsung Electronics Co., Ltd. | Semiconductor devices including contact structures that partially overlap silicide layers |
US10403717B2 (en) | 2015-04-14 | 2019-09-03 | Samsung Electronics Co., Ltd. | Semiconductor devices including contact structures that partially overlap silicide layers |
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KR20100029738A (ko) | 2010-03-17 |
KR20120079487A (ko) | 2012-07-12 |
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