JP5432492B2 - 絶縁ゲート型半導体装置 - Google Patents
絶縁ゲート型半導体装置 Download PDFInfo
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- JP5432492B2 JP5432492B2 JP2008252999A JP2008252999A JP5432492B2 JP 5432492 B2 JP5432492 B2 JP 5432492B2 JP 2008252999 A JP2008252999 A JP 2008252999A JP 2008252999 A JP2008252999 A JP 2008252999A JP 5432492 B2 JP5432492 B2 JP 5432492B2
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- 239000004065 semiconductor Substances 0.000 title claims description 43
- 239000000758 substrate Substances 0.000 claims description 52
- 230000001681 protective effect Effects 0.000 claims description 23
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 226
- 150000004767 nitrides Chemical class 0.000 description 13
- 239000012535 impurity Substances 0.000 description 12
- 108091006146 Channels Proteins 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 10
- 210000000746 body region Anatomy 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- 239000011241 protective layer Substances 0.000 description 1
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- 229910000679 solder Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
つまり、ゲートパッド部28pと、配線部28wの一部は、保護ダイオードDiと非重畳となり、ゲートパッド部28p及び配線部28wの一部の下方に第1ソース電極層17およびセルが配置される。
2 n−型半導体層
4 チャネル層
7 トレンチ
10、10’ MOSFET
11 ゲート絶縁膜
13 ゲート電極
14 ボディ領域
15 ソース領域
16 層間絶縁膜
17 第1ソース電極層
18 第1ゲート電極層
19 第1ドレイン電極層
20 素子領域
21 セル
23 第1絶縁膜(窒化膜)
24 UBM
25 第2絶縁膜
27 第2ソース電極層
28 第2ゲート電極層
29 第2ドレイン電極層
28p ゲートパッド部
28w 配線部
28o 重畳領域
28u 非重畳領域
27p ソースパッド部
29p ドレインパッド部
37 ソースバンプ電極
38 ゲートバンプ電極
39 ドレインバンプ電極
200、210 MOSFET
217 第1ソース電極層
218 第1ゲート電極層
227 第2ソース電極層
227p ソースパッド部
228 第2ゲート電極層
228p ゲートパッド部
Claims (3)
- 一導電型半導体基板と、
該半導体基板上に設けられた一導電型半導体層と、
該半導体層表面に設けられ絶縁ゲート型トランジスタのセルが複数配置された素子領域と、
前記基板上に設けられて前記素子領域の一の部分と直接接触せず上方を覆い、該素子領域に接続する第1端子電極層と、
前記基板上に設けられて前記素子領域の他の部分と直接接触せず上方を覆い、該素子領域に接続して制御信号を印加する第2端子電極層と、
前記第1端子電極層下方に設けられ該第1端子電極層と接続する他の第1端子電極層と、
前記第2端子電極層下方の前記素子領域外に設けられ該第2端子電極層および前記素子領域と接続する他の第2端子電極層と、を具備し、
前記第2端子電極層は外部接続手段が固着するパッド部を有し、該パッド部は前記セルが配置された前記素子領域上に配置され、
前記他の第2端子電極層の下方で且つ前記基板の端部に保護ダイオードが配置され、該保護ダイオードの一端は前記他の第1端子電極層に接続し、他端は前記素子領域のゲート電極に接続され、
前記パッド部と前記保護ダイオードとは重ならず、
前記第2端子電極層は前記パッド部から前記他の第2端子電極層まで延在し、前記パッド部よりも線幅の狭い配線部を有し、
前記パッド部と前記保護ダイオードとは前記配線部を介して接続し、
前記配線部の下方には前記セルが位置し、前記配線部の周囲側方には前記第1端子電極層が位置することを特徴とする絶縁ゲート型半導体装置。 - 前記第2端子電極層は、前記他の第2端子電極層より大きいことを特徴とする請求項1に記載の絶縁ゲート型半導体装置。
- 前記第2端子電極層下方に前記他の第1端子電極層の一部が配置されることを特徴とする請求項2に記載の絶縁ゲート型半導体装置。
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JP2008252999A JP5432492B2 (ja) | 2008-09-30 | 2008-09-30 | 絶縁ゲート型半導体装置 |
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JP2008252999A JP5432492B2 (ja) | 2008-09-30 | 2008-09-30 | 絶縁ゲート型半導体装置 |
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JP2010087125A JP2010087125A (ja) | 2010-04-15 |
JP5432492B2 true JP5432492B2 (ja) | 2014-03-05 |
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WO2021225119A1 (ja) * | 2020-05-08 | 2021-11-11 | ローム株式会社 | 半導体装置 |
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JP2004014707A (ja) * | 2002-06-05 | 2004-01-15 | Renesas Technology Corp | 半導体装置 |
JP4557507B2 (ja) * | 2002-06-13 | 2010-10-06 | パナソニック株式会社 | 半導体デバイス及びその製造方法 |
JP2007042817A (ja) * | 2005-08-02 | 2007-02-15 | Sanyo Electric Co Ltd | 絶縁ゲート型半導体装置およびその製造方法 |
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