JP5387407B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5387407B2 JP5387407B2 JP2009524353A JP2009524353A JP5387407B2 JP 5387407 B2 JP5387407 B2 JP 5387407B2 JP 2009524353 A JP2009524353 A JP 2009524353A JP 2009524353 A JP2009524353 A JP 2009524353A JP 5387407 B2 JP5387407 B2 JP 5387407B2
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- Japan
- Prior art keywords
- layer
- electrode
- semiconductor device
- electrode pad
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 11
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Description
41 半導体基板
43 多層配線層
44 配線層
45 層間絶縁層
46 配線接続部
47 電極パッド
48 無機絶縁層
49 有機絶縁層
50 第1バンプ下地金属層
51 第2バンプ下地金属層
52 外部接続用突起電極
55 絶縁部材
71 配線基板
200 半導体装置
[第1の実施の形態]
本発明の第1の実施の形態に係る半導体素子の主面を図4に示す。また、当該図4の、点線A−Aにおける断面を図5に示す。
本発明の第2の実施の形態に係る半導体素子について、図10を参照して説明する。
[第1の実施の形態に係る半導体装置の製造方法]
図4、図7、図8、図9及び図11を参照して、本発明の第1の実施の形態に係る半導体装置200の製造方法について説明する。
図10に示す、本発明の第2の実施の形態に係る半導体素子150は、以下の工程を経て形成される。
Claims (9)
- 第1の領域と、平面視で前記第1の領域とは異なる第2の領域を有する半導体基板と、
前記半導体基板上に形成されたトランジスタと、
前記トランジスタ上に形成され、配線層及び層間絶縁層を有する多層配線層と、
前記第1の領域の前記多層配線層上に形成された電極パッドと、
前記電極パッドを表出して前記配線層上に配設された絶縁層と、
一端が前記電極パッドの表出部に接続され、前記一端とは異なる他端が前記第2の領域の前記絶縁層上に延在して配設され、前記一端と前記他端との間で表出する導電層と、
前記他端に接続して、前記第2の領域の前記導電層上に配設された突起電極と、を備え、
前記電極パッドは、前記半導体基板の主面において、縦方向及び横方向に略同一の間隔にマトリクス状に複数配設され、
前記突起電極は、前記半導体基板の主面において、前記縦方向及び前記横方向に略同一の間隔にマトリクス状に複数配設されており、
前記配線層は、前記第2の領域には形成されていないことを特徴とする半導体装置。 - 請求項1に記載の半導体装置であって、
前記半導体基板は平面視で矩形であり、
前記導電層は、前記一端側から前記他端側にかけて、又は、前記他端側から前記一端側にかけて、前記半導体基板の中心側から前記半導体基板の前記矩形の4つの角のそれぞれの側に向かって延在することを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
全ての前記導電層が、一定の方向に延在していることを特徴とする半導体装置。 - 平面視で矩形の半導体基板と、
前記半導体基板上に形成されたトランジスタと、
前記トランジスタ上に形成され、配線層及び層間絶縁層を有する多層配線層と、
前記多層配線層に配設された電極パッドと、
前記電極パッドを表出して前記配線層上に配設された絶縁層と、
一端が前記電極パッドの表出部に接続され、前記複数の電極パッド毎に前記絶縁層上に延在して配設された導電層と、
前記導電層の前記一端とは異なる他端に配設された突起電極と、を備え、
前記導電層は、前記一端と前記他端との間で表出するとともに、前記一端側から前記他端側にかけて、又は、前記他端側から前記一端側にかけて、前記半導体基板の中心側から前記半導体基板の前記矩形の4つの角のそれぞれの側に向かって延在して複数配設され、
前記電極パッドは、前記半導体基板の主面において、縦方向及び横方向に略同一の間隔にマトリクス状に複数配設され、
前記突起電極は、前記半導体基板の主面において、前記縦方向及び前記横方向に略同一の間隔にマトリクス状に複数配設されていることを特徴とする半導体装置。 - 請求項1乃至4のいずれか1項に記載の半導体装置であって、
前記導電層の幅は、前記導電層の接続している前記電極パッドから前記突起電極に近づくに従って増大することを特徴とする半導体装置。 - 請求項1または3記載の半導体装置であって、
前記電極パッドから、前記電極パッドと前記導電層によって接続された前記突起電極までの距離は、すべて等しいことを特徴とする半導体装置。 - 請求項1または3記載の半導体装置であって、
前記絶縁層は、無機絶縁膜と、前記無機絶縁膜上に形成された有機絶縁膜とから構成されることを特徴とする半導体装置。 - 請求項1または3記載の半導体装置であって、
前記導電層は複数の金属層から構成されることを特徴とする半導体装置。 - 請求項8記載の半導体装置であって、
前記導電層はチタン(Ti)又はクロム(Cr)を含む材料から構成される第1バンプ下地金属層、及び、銅(Cu)あるいはニッケル(Ni)を含む材料から構成される第2バンプ下地金属層からなることを特徴とする半導体装置。
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PCT/JP2007/064601 WO2009013826A1 (ja) | 2007-07-25 | 2007-07-25 | 半導体装置 |
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JP (1) | JP5387407B2 (ja) |
KR (1) | KR101095409B1 (ja) |
CN (1) | CN101755334B (ja) |
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JP4538764B2 (ja) * | 2008-07-24 | 2010-09-08 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
JP5350022B2 (ja) * | 2009-03-04 | 2013-11-27 | パナソニック株式会社 | 半導体装置、及び該半導体装置を備えた実装体 |
US8378485B2 (en) * | 2009-07-13 | 2013-02-19 | Lsi Corporation | Solder interconnect by addition of copper |
JP5378130B2 (ja) | 2009-09-25 | 2013-12-25 | 株式会社東芝 | 半導体発光装置 |
US8624391B2 (en) * | 2009-10-08 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip design with robust corner bumps |
JP2011096918A (ja) * | 2009-10-30 | 2011-05-12 | Oki Semiconductor Co Ltd | 半導体装置および半導体装置の製造方法 |
US9070851B2 (en) | 2010-09-24 | 2015-06-30 | Seoul Semiconductor Co., Ltd. | Wafer-level light emitting diode package and method of fabricating the same |
US9449933B2 (en) * | 2012-03-29 | 2016-09-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Packaging device and method of making the same |
JP5475077B2 (ja) * | 2012-09-07 | 2014-04-16 | 日本特殊陶業株式会社 | 配線基板およびその製造方法 |
US9418877B2 (en) | 2014-05-05 | 2016-08-16 | Qualcomm Incorporated | Integrated device comprising high density interconnects in inorganic layers and redistribution layers in organic layers |
CN205944139U (zh) | 2016-03-30 | 2017-02-08 | 首尔伟傲世有限公司 | 紫外线发光二极管封装件以及包含此的发光二极管模块 |
JP7279624B2 (ja) | 2019-11-27 | 2023-05-23 | 株式会社ソシオネクスト | 半導体装置 |
US11495561B2 (en) * | 2020-05-11 | 2022-11-08 | X Display Company Technology Limited | Multilayer electrical conductors for transfer printing |
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2007
- 2007-07-25 KR KR1020107001067A patent/KR101095409B1/ko active IP Right Grant
- 2007-07-25 CN CN200780100002.6A patent/CN101755334B/zh not_active Expired - Fee Related
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- 2007-07-25 JP JP2009524353A patent/JP5387407B2/ja not_active Expired - Fee Related
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KR20100029247A (ko) | 2010-03-16 |
CN101755334A (zh) | 2010-06-23 |
WO2009013826A1 (ja) | 2009-01-29 |
CN101755334B (zh) | 2011-08-31 |
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