JP5353237B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP5353237B2
JP5353237B2 JP2008509652A JP2008509652A JP5353237B2 JP 5353237 B2 JP5353237 B2 JP 5353237B2 JP 2008509652 A JP2008509652 A JP 2008509652A JP 2008509652 A JP2008509652 A JP 2008509652A JP 5353237 B2 JP5353237 B2 JP 5353237B2
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Prior art keywords
film
conductive pad
insulating film
protective insulating
wiring
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JP2008509652A
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JPWO2007116501A1 (en
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昭幸 ▲高▼橋
孝一 永井
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Fujitsu Semiconductor Ltd
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Fujitsu Semiconductor Ltd
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    • H01L2924/19041—Component type being a capacitor

Abstract

A first conductive pad (60) is subjected to various tests before forming a second conductive pad (70) for an external connection with a size slightly smaller than that of the first conductive pad (60) in a plan view so as to be connected to a first conductive pad (60). The second conductive pad (70) is so formed as to be included in the area in which the first conductive pad (60) is formed in the plan view while covering the inner wall bottom surface, the inner wall side surface of an opening (66a) of a passivation film (66), and the passivation film (66). This realizes a highly reliable FeRAM for surely preventing intrusion of water/hydrogen with a relatively simple construction and maintaining high performance of a ferroelectric capacitor structure (30) having a ferroelectric film (25).

Description

本発明は、下部電極と上部電極との間に強誘電体からなるキャパシタ膜が挟持されてなる強誘電体キャパシタ構造を有する半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device having a ferroelectric capacitor structure in which a capacitor film made of a ferroelectric material is sandwiched between a lower electrode and an upper electrode, and a method for manufacturing the same.

近年、強誘電体の分極反転を利用して情報を強誘電体キャパシタ構造に保持する強誘電体メモリ（ＦｅＲＡＭ）の開発が進められている。強誘電体メモリは、電源を断っても保持された情報が消失しない不揮発メモリであり、高集積度、高速駆動、高耐久性、及び低消費電力の実現が期待できることから特に注目されている。   In recent years, development of a ferroelectric memory (FeRAM) that holds information in a ferroelectric capacitor structure using polarization inversion of the ferroelectric has been advanced. A ferroelectric memory is a non-volatile memory in which retained information is not lost even when the power is turned off, and is attracting particular attention because it can be expected to realize high integration, high speed driving, high durability, and low power consumption.

強誘電体キャパシタ構造を構成する強誘電体膜の材料としては、残留分極量が大きな、例えば１０（μＣ／ｃｍ２）〜３０（μＣ／ｃｍ２）程度のＰＺＴ（Ｐｂ（Ｚｒ，Ｔｉ）Ｏ３）膜、ＳＢＴ（ＳｒＢｉ２Ｔａ２Ｏ９）膜などのペロブスカイト結晶構造を有する強誘電体酸化物が主として用いられている。As a material of the ferroelectric film constituting the ferroelectric capacitor structure, PZT (Pb (Zr, Ti) O having a large remanent polarization, for example, about 10 (μC / cm 2 ) to 30 (μC / cm 2 ). 3 ) Ferroelectric oxides having a perovskite crystal structure such as a film and an SBT (SrBi 2 Ta 2 O 9 ) film are mainly used.

特開２００４−２９６７７５号公報JP 2004-296775 A 特開２００３−９２３５３号公報JP 2003-92353 A 特許第２９１７３６２号公報Japanese Patent No. 2917362

強誘電体キャパシタ構造では、シリコン酸化膜などの水との親和性の高い層間絶縁膜を介して外部から侵入した水分により、キャパシタ膜の強誘電特性が劣化することが知られている。即ち、先ず、外部から侵入した水分が層間絶縁膜やメタル配線成膜時の高温プロセス中で水素と酸素とに分解する。この水素が強誘電体膜中に侵入すると、強誘電体膜の酸素と反応して強誘電体膜に酸素欠陥が形成され結晶性が低下する。また、強誘電体メモリの長期間の使用によっても同様の現象が発生する。その結果、強誘電体膜の残留分極量や誘電率が低下するなどの強誘電体キャパシタ構造の性能劣化が発生する。また、このような水素の浸入により、強誘電体キャパシタ構造に限らず、トランジスタ構造等の性能が劣化することがある。   In the ferroelectric capacitor structure, it is known that the ferroelectric characteristics of the capacitor film deteriorate due to moisture entering from the outside through an interlayer insulating film having a high affinity with water such as a silicon oxide film. That is, first, moisture that has entered from the outside is decomposed into hydrogen and oxygen in a high-temperature process when forming an interlayer insulating film or metal wiring. When this hydrogen penetrates into the ferroelectric film, it reacts with oxygen in the ferroelectric film to form oxygen defects in the ferroelectric film and lower the crystallinity. The same phenomenon occurs even when the ferroelectric memory is used for a long time. As a result, the performance degradation of the ferroelectric capacitor structure occurs, such as the residual polarization amount and the dielectric constant of the ferroelectric film decreasing. In addition, such hydrogen intrusion may degrade the performance of not only the ferroelectric capacitor structure but also the transistor structure.

この点、強誘電体キャパシタ構造の上層にアルミナ等の水素拡散防止膜を形成することにより、水素の浸入を防止する試みがある。この水素拡散防止膜により、ある程度の水素遮断機能は期待できるのであるが、強誘電体キャパシタ構造の高性能を保持するに十分であるとは言えない。   In this regard, there is an attempt to prevent hydrogen from entering by forming a hydrogen diffusion prevention film such as alumina on the upper layer of the ferroelectric capacitor structure. Although this hydrogen diffusion preventing film can be expected to have a certain level of hydrogen blocking function, it cannot be said to be sufficient to maintain the high performance of the ferroelectric capacitor structure.

本発明は、上記の課題に鑑みてなされたものであり、比較的簡易な構成で十分な水・水素の内部侵入を確実に防止し、強誘電体からなるキャパシタ膜を有するキャパシタ構造の高性能を保持する信頼性の高い半導体装置及びその製造方法を提供することを目的とする。   The present invention has been made in view of the above-mentioned problems, and it is possible to reliably prevent sufficient internal penetration of water and hydrogen with a relatively simple configuration, and to achieve high performance of a capacitor structure having a capacitor film made of a ferroelectric substance. An object of the present invention is to provide a highly reliable semiconductor device and a method for manufacturing the same.

本発明の半導体装置は、半導体基板の上方に形成されており、下部電極と上部電極とにより強誘電体からなるキャパシタ膜を挟持してなるキャパシタ構造と、前記キャパシタ構造の上方に形成されており、前記キャパシタ構造と電気的に接続されてなる配線構造と、下方に前記キャパシタ構造の存しない局所的な形成領域で前記配線構造と電気的に接続されており、検査機器のプローブが直接的に当接することで各種の試験が施された第１の導電パッドと、前記第１の導電パッド及び前記配線構造を覆い、前記第１の導電パッドの表面における前記検査の部位のみを露出させる開口を有する第１の保護絶縁膜と、前記第１の保護絶縁膜上から前記開口の内壁面にかけて覆って前記第１の導電パッドと電気的に接続され、前記第１の導電パッドの前記形成領域に整合する位置に形成されており、外部との電気的接続を図る第２の導電パッドと、前記第２の導電パッド及び前記第１の保護絶縁膜を覆い、前記第２の導電パッドの表面における前記外部との電気的接続の部位のみを露出させる開口を有する第２の保護絶縁膜と、前記第２の保護絶縁膜を覆い、前記第２の導電パッドの表面における前記外部との電気的接続の部位を露出させる開口を有する絶縁膜とを含み、前記第１の保護絶縁膜は、第１酸化膜と、前記第１酸化膜上に形成された第１窒化膜とを含み、前記第２の保護絶縁膜は、第２酸化膜と、前記第２酸化膜上に形成された第２窒化膜とを含み、前記第１酸化膜と前記第１窒化膜との間、及び前記第２酸化膜と前記第２窒化膜との間の少なくとも一方にアルミナ膜が形成されている。 A semiconductor device of the present invention is formed above a semiconductor substrate, and is formed above a capacitor structure in which a capacitor film made of a ferroelectric material is sandwiched between a lower electrode and an upper electrode. A wiring structure that is electrically connected to the capacitor structure, and a wiring structure that is electrically connected to the wiring structure in a local formation region where the capacitor structure does not exist below. A first conductive pad that has been subjected to various tests by contact, and an opening that covers the first conductive pad and the wiring structure and exposes only the inspection portion on the surface of the first conductive pad. A first protective insulating film, and covering the first protective insulating film from an inner wall surface of the opening to be electrically connected to the first conductive pad, and the first conductive pad A second conductive pad that is formed at a position that matches the formation region and that is to be electrically connected to the outside, covers the second conductive pad and the first protective insulating film, and includes the second conductive pad. A second protective insulating film having an opening exposing only a portion of electrical connection with the outside on the surface of the pad; and covering the second protective insulating film, and the outside on the surface of the second conductive pad. look including an insulating film having an opening exposing a portion of the electrical connection, the first protective insulating film, a first oxide film, and a first nitride film formed on the first oxide film The second protective insulating film includes a second oxide film and a second nitride film formed on the second oxide film, and the second protective insulating film is between the first oxide film and the first nitride film, And an alumina film is formed on at least one of the second oxide film and the second nitride film. It has been.

本発明の半導体装置の製造方法は、半導体基板の上方に、下部電極と上部電極とにより強誘電体からなるキャパシタ膜を挟持してなるキャパシタ構造を形成する工程と、前記キャパシタ構造の上方に、前記キャパシタ構造と電気的に接続されるように配線構造を形成する工程と、下方に前記キャパシタ構造の存しない局所的な形成領域において、前記配線構造と電気的に接続されるように第１の導電パッドを形成する工程と、前記第１の導電パッド及び前記配線構造を覆うように第１の保護絶縁膜を形成した後、前記第１の保護絶縁膜に、前記第１の導電パッドの表面における検査の部位のみを露出させる開口を形成する工程と、前記開口から、検査機器のプローブを前記第１の導電パッドの表面に直接的に当接することにより、各種の試験を行う工程と、前記第１の保護絶縁膜上から前記開口の内壁面にかけて覆って前記第１の導電パッドと電気的に接続され、前記第１の導電パッドの前記形成領域に整合する位置に、外部との電気的接続を図る第２の導電パッドを形成する工程と、前記第２の導電パッド及び前記第１の保護絶縁膜を覆うように第２の保護絶縁膜を形成した後、前記第２の保護絶縁膜に、前記第２の導電パッドの表面における前記外部との電気的接続の部位のみを露出させる開口を形成する工程と、前記第２の保護絶縁膜を覆うように絶縁膜を形成した後、前記絶縁膜に、前記第２の導電パッドの表面における前記外部との電気的接続の部位を露出させる開口を形成する工程とを含み、前記第１の保護絶縁膜は、第１酸化膜と、前記第１酸化膜上に形成された第１窒化膜とを含み、前記第２の保護絶縁膜は、第２酸化膜と、前記第２酸化膜上に形成された第２窒化膜とを含み、前記第１酸化膜と前記第１窒化膜との間、及び前記第２酸化膜と前記第２窒化膜との間の少なくとも一方にアルミナ膜が形成される。 The method of manufacturing a semiconductor device of the present invention includes a step of forming a capacitor structure formed by sandwiching a capacitor film made of a ferroelectric material between a lower electrode and an upper electrode above a semiconductor substrate, and above the capacitor structure, Forming a wiring structure so as to be electrically connected to the capacitor structure, and a first formation so as to be electrically connected to the wiring structure in a local formation region below the capacitor structure; Forming a conductive pad; and forming a first protective insulating film so as to cover the first conductive pad and the wiring structure, and then forming a surface of the first conductive pad on the first protective insulating film. Forming an opening that exposes only the part to be inspected, and various tests by directly contacting the probe of the inspection device to the surface of the first conductive pad from the opening. And a step of covering from the first protective insulating film to the inner wall surface of the opening to be electrically connected to the first conductive pad and to be aligned with the formation region of the first conductive pad, Forming a second conductive pad for electrical connection to the outside; forming a second protective insulating film so as to cover the second conductive pad and the first protective insulating film; Forming an opening in the surface of the second conductive pad to expose only the portion of the electrical connection with the outside, and an insulating film to cover the second protective insulating film after forming, the insulating film, the second viewing including the step of forming an opening to expose a portion of the electrical connection between the outer the surface of the conductive pad, wherein the first protective insulating film, the A first oxide film and a first oxide film formed on the first oxide film; The second protective insulating film includes a second oxide film and a second nitride film formed on the second oxide film, and includes the first oxide film and the first nitride film. And an alumina film is formed on at least one of the second oxide film and the second nitride film .

本発明によれば、比較的簡易な構成で十分な水・水素の内部侵入を確実に防止し、強誘電体からなるキャパシタ膜を有するキャパシタ構造の高性能を保持する信頼性の高い半導体装置を実現することができる。   According to the present invention, there is provided a highly reliable semiconductor device that reliably prevents internal penetration of sufficient water and hydrogen with a relatively simple configuration and maintains high performance of a capacitor structure having a capacitor film made of a ferroelectric substance. Can be realized.

図１Ａは、第１の実施形態によるプレーナ型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 1A is a schematic cross-sectional view showing a method of manufacturing a planar type FeRAM according to the first embodiment. 図１Ｂは、第１の実施形態によるプレーナ型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 1B is a schematic cross-sectional view illustrating the method for manufacturing the planar FeRAM according to the first embodiment. 図１Ｃは、第１の実施形態によるプレーナ型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 1C is a schematic cross-sectional view illustrating the method for manufacturing the planar FeRAM according to the first embodiment. 図１Ｄは、第１の実施形態によるプレーナ型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 1D is a schematic cross-sectional view illustrating the method for manufacturing the planar FeRAM according to the first embodiment. 図２Ａは、第１の実施形態によるプレーナ型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 2A is a schematic cross-sectional view illustrating the method for manufacturing the planar FeRAM according to the first embodiment. 図２Ｂは、第１の実施形態によるプレーナ型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 2B is a schematic cross-sectional view illustrating the method for manufacturing the planar FeRAM according to the first embodiment. 図２Ｃは、第１の実施形態によるプレーナ型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 2C is a schematic cross-sectional view illustrating the method for manufacturing the planar FeRAM according to the first embodiment. 図２Ｄは、第１の実施形態によるプレーナ型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 2D is a schematic cross-sectional view showing the method of manufacturing the planar type FeRAM according to the first embodiment. 図３Ａは、第１の実施形態によるプレーナ型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 3A is a schematic cross-sectional view showing the method for manufacturing the planar type FeRAM according to the first embodiment. 図３Ｂは、第１の実施形態によるプレーナ型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 3B is a schematic cross-sectional view illustrating the method for manufacturing the planar FeRAM according to the first embodiment. 図４は、第１の実施形態によるプレーナ型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 4 is a schematic cross-sectional view illustrating the method for manufacturing the planar type FeRAM according to the first embodiment. 図５は、第１の実施形態によるプレーナ型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the planar type FeRAM according to the first embodiment. 図６は、第１の実施形態によるプレーナ型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 6 is a schematic cross-sectional view showing the method for manufacturing the planar type FeRAM according to the first embodiment. 図７は、第１の実施形態によるプレーナ型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 7 is a schematic cross-sectional view showing the method for manufacturing the planar type FeRAM according to the first embodiment. 図８は、第１の実施形態によるプレーナ型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 8 is a schematic cross-sectional view illustrating the method for manufacturing the planar type FeRAM according to the first embodiment. 図９は、第１の実施形態によるプレーナ型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 9 is a schematic cross-sectional view illustrating the method for manufacturing the planar type FeRAM according to the first embodiment. 図１０は、第１の実施形態によるプレーナ型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 10 is a schematic cross-sectional view illustrating the method for manufacturing the planar type FeRAM according to the first embodiment. 図１１Ａは、第１の実施形態の変形例１によるプレーナ型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 11A is a schematic cross-sectional view showing a method for manufacturing the planar FeRAM according to the first modification of the first embodiment. 図１１Ｂは、第１の実施形態の変形例１によるプレーナ型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 11B is a schematic cross-sectional view showing the method for manufacturing the planar FeRAM according to the first modification of the first embodiment. 図１１Ｃは、第１の実施形態の変形例１によるプレーナ型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 11C is a schematic cross-sectional view showing the method of manufacturing the planar type FeRAM according to the first modification of the first embodiment. 図１１Ｄは、第１の実施形態の変形例１によるプレーナ型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 11D is a schematic cross-sectional view illustrating the method for manufacturing the planar FeRAM according to the first modification of the first embodiment. 図１２Ａは、第１の実施形態の変形例２によるプレーナ型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 12A is a schematic cross-sectional view showing a method for manufacturing the planar FeRAM according to the second modification of the first embodiment. 図１２Ｂは、第１の実施形態の変形例２によるプレーナ型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 12B is a schematic cross-sectional view showing the method for manufacturing the planar FeRAM according to the second modification of the first embodiment. 図１２Ｃは、第１の実施形態の変形例２によるプレーナ型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 12C is a schematic cross-sectional view illustrating the method for manufacturing the planar FeRAM according to the second modification of the first embodiment. 図１３Ａは、第１の実施形態の変形例３によるプレーナ型のＦｅＲＡＭを示す概略断面図である。FIG. 13A is a schematic cross-sectional view showing a planar type FeRAM according to Modification 3 of the first embodiment. 図１３Ｂは、第１の実施形態の変形例３によるプレーナ型のＦｅＲＡＭを示す概略断面図である。FIG. 13B is a schematic cross-sectional view showing a planar-type FeRAM according to Modification 3 of the first embodiment. 図１４Ａは、第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 14A is a schematic cross-sectional view showing the method for manufacturing the stacked FeRAM according to the second embodiment. 図１４Ｂは、第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 14B is a schematic cross-sectional view showing the method for manufacturing the stacked FeRAM according to the second embodiment. 図１４Ｃは、第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 14C is a schematic cross-sectional view showing the method for manufacturing the stacked FeRAM according to the second embodiment. 図１４Ｄは、第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 14D is a schematic cross-sectional view illustrating the method for manufacturing the stacked FeRAM according to the second embodiment. 図１５Ａは、第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 15A is a schematic cross-sectional view showing the method for manufacturing the stacked FeRAM according to the second embodiment. 図１５Ｂは、第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 15B is a schematic cross-sectional view showing the method for manufacturing the stacked FeRAM according to the second embodiment. 図１５Ｃは、第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 15C is a schematic cross-sectional view showing the method for manufacturing the stacked FeRAM according to the second embodiment. 図１５Ｄは、第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 15D is a schematic cross-sectional view illustrating the method for manufacturing the stacked FeRAM according to the second embodiment. 図１６Ａは、第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 16A is a schematic cross-sectional view showing the method for manufacturing the stacked FeRAM according to the second embodiment. 図１６Ｂは、第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 16B is a schematic cross-sectional view illustrating the method for manufacturing the stacked FeRAM according to the second embodiment. 図１６Ｃは、第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 16C is a schematic cross-sectional view showing the method for manufacturing the stacked FeRAM according to the second embodiment. 図１７Ａは、第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 17A is a schematic cross-sectional view illustrating the method for manufacturing the stacked FeRAM according to the second embodiment. 図１７Ｂは、第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 17B is a schematic cross-sectional view showing the method for manufacturing the stacked FeRAM according to the second embodiment. 図１７Ｃは、第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 17C is a schematic sectional view showing the method for manufacturing the stack type FeRAM according to the second embodiment. 図１８は、第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 18 is a schematic cross-sectional view showing the method for manufacturing the stack type FeRAM according to the second embodiment. 図１９は、第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 19 is a schematic cross-sectional view showing the method for manufacturing the stacked FeRAM according to the second embodiment. 図２０は、第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 20 is a schematic cross-sectional view showing the method for manufacturing the stacked FeRAM according to the second embodiment. 図２１は、第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 21 is a schematic cross-sectional view showing the method for manufacturing the stacked FeRAM according to the second embodiment. 図２２は、第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 22 is a schematic cross-sectional view showing the method for manufacturing the stacked FeRAM according to the second embodiment. 図２３は、第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 23 is a schematic cross-sectional view showing the method for manufacturing the stack type FeRAM according to the second embodiment. 図２４は、第２の実施形態によるスタック型のＦｅＲＡＭの製造方法を示す概略断面図である。FIG. 24 is a schematic cross-sectional view showing the method for manufacturing the stack type FeRAM according to the second embodiment.

−本発明の基本骨子−
ＦｅＲＡＭにおいて、キャパシタ膜の特性劣化は、外部から浸入する水分・水素の影響が大きい。これら水分・水素の浸入経路を調査したところ、導電パッドに生じた亀裂から装置内部に多量に染み込んでいることが判ってきた。この導電パッドの亀裂は、検査機器の探針（プローブ）を用いたＦｅＲＡＭの各種検査に起因して発生する。即ち、当該検査は、装置最上層の緩衝防止膜（ポリイミドやノボラック樹脂等）に形成された開口から露出する導電パッドの表面にプローブを直接的に当接させて行われる。当該検査としては、ＦｅＲＡＭ等の半導体メモリに固有の試験を要する。詳細には、装置の動作が正常に行われるか否かを調べる試験に加え、データの書き込み及び読み出しの良否を判定するためのリテンション試験及び最終的な確認試験を行う。そのため、各試験時におけるプローブによる導電パッドへの複数回の当接により、導電パッドに亀裂等が発生することが多い。-Basic outline of the present invention-
In FeRAM, deterioration of capacitor film characteristics is greatly affected by moisture and hydrogen entering from the outside. As a result of investigating the water and hydrogen infiltration paths, it has been found that a large amount of water penetrates into the inside of the device due to cracks generated in the conductive pads. This crack of the conductive pad occurs due to various inspections of the FeRAM using the probe of the inspection device. That is, the inspection is performed by bringing the probe directly into contact with the surface of the conductive pad exposed from the opening formed in the buffering prevention film (such as polyimide or novolac resin) at the uppermost layer of the apparatus. This inspection requires a test specific to a semiconductor memory such as FeRAM. Specifically, in addition to a test for checking whether or not the operation of the apparatus is normally performed, a retention test and a final confirmation test for determining whether data writing and reading are good or bad are performed. For this reason, a crack or the like often occurs in the conductive pad due to the contact of the probe with the conductive pad multiple times during each test.

このように導電パッドに亀裂が生じた状態で後工程へ進むと、例えば、基板のダイシング時における水分の影響により、導電パッドの亀裂から水分・水素が浸入する。また、パッケージ樹脂を形成する際におけるモールドキュア時に、導電パッドの亀裂から水分・水素が浸入する。これらの水分・水素の浸入により、キャパシタ膜の強誘電特性の著しい劣化を惹起するという深刻な問題がある。 When the process proceeds to a subsequent process in a state where a crack is generated in the conductive pad in this way, for example, moisture and hydrogen enter from the crack of the conductive pad due to the influence of moisture during dicing of the substrate. Further, moisture and hydrogen permeate from the cracks of the conductive pad during mold curing when forming the package resin. There is a serious problem that the penetration of moisture and hydrogen causes remarkable deterioration of the ferroelectric characteristics of the capacitor film.

この亀裂を修復すべく、上記の検査を終了した後に亀裂が生じた導電パッドの表面を導電材料で覆う対処法が考えられる。
この点、特許文献１，２には、検査機器のプローブを用いた検査後に、導電パッドを覆いその上層で延在する再配線を形成し、導電パッドの上方から離間した箇所に、外部接続用の電極を設ける構成が開示されている。しかしながらこの場合、以下に説明するような問題が新たに発生する。In order to repair this crack, a method of covering the surface of the conductive pad where the crack has occurred after the above-described inspection is covered with a conductive material can be considered.
In this regard, in Patent Documents 1 and 2, after the inspection using the probe of the inspection device, a rewiring that covers the conductive pad and extends in the upper layer is formed, and the external connection is provided at a position away from the upper side of the conductive pad. The structure which provides the electrode of this is disclosed. However, in this case, a problem as described below newly occurs.

特許文献１，２では、共に、プローブを用いた針当てが行われる導電パッドと、外部接続用の電極とが離間した構成を採る。従って当然に半導体チップの面積が増加してしまい、近時における微細化の要請に反する結果となる。   Patent Documents 1 and 2 both adopt a configuration in which a conductive pad that is subjected to needle contact using a probe and an electrode for external connection are separated from each other. Therefore, naturally, the area of the semiconductor chip increases, which is contrary to the recent demand for miniaturization.

更にこの場合、ＦｅＲＡＭに固有の問題がある。ＦｅＲＡＭの強誘電体キャパシタ構造は言わば圧電素子であり、強誘電体キャパシタ構造の近傍において圧力印加がなされることにより、強誘電特性の著しい劣化を招く。従ってＦｅＲＡＭの製造時には、強誘電体キャパシタ構造への圧力印加を可及的に抑えることを要する。そのため、強誘電体キャパシタ構造の近傍、即ち強誘電体キャパシタ構造の上方箇所では圧力印加がなされないような工夫が必要となる。この圧力印加の主な態様は、上述の導電パッドへの針当てを行う各種の試験、及び外部接続時の端子の圧着等である。従って、特許文献１，２のように、プローブを用いた針当てが行われる導電パッドと外部接続用の電極とが離間した構成を採れば、配置の関係上、強誘電体キャパシタ構造の上方箇所或いはこれに近い箇所に導電パッド或いは外部接続用の電極を配置せざるを得ない場合があり、強誘電特性の著しい劣化を招くことになる。   Further, in this case, there is a problem inherent to FeRAM. The ferroelectric capacitor structure of FeRAM is a so-called piezoelectric element, and the application of pressure in the vicinity of the ferroelectric capacitor structure causes a significant deterioration of the ferroelectric characteristics. Therefore, when manufacturing the FeRAM, it is necessary to suppress the pressure application to the ferroelectric capacitor structure as much as possible. For this reason, it is necessary to devise such that no pressure is applied in the vicinity of the ferroelectric capacitor structure, that is, in the upper portion of the ferroelectric capacitor structure. The main aspects of this pressure application are various tests for applying the needle to the conductive pad described above, and crimping of terminals at the time of external connection. Therefore, as in Patent Documents 1 and 2, if a configuration is adopted in which the conductive pad on which the probe is applied and the electrode for external connection are separated from each other, the location above the ferroelectric capacitor structure in terms of arrangement Alternatively, there may be a case where a conductive pad or an electrode for external connection must be arranged at a location close to this, which causes a significant deterioration of the ferroelectric characteristics.

この点、特許文献３には、その第２図及び説明箇所に示すように、プローブを用いた針当てが行われて表面に荒れが生じた場合、当該表面に導電材料を堆積する構成が開示されている。しかしながら、そもそも特許文献３では、導電パッドを兼ねる配線層が直下の不純物領域と接続されてなるのみの極めて単純な構成を採る。従って、ＦｅＲＡＭのような優れたメモリである反面、新たな課題を抱えた複雑な素子構成には適用できない。本発明者の鋭意検討により、この技術をＦｅＲＡＭに適用させて亀裂の生じた導電パッド上に導電材料を堆積させても、キャパシタ膜における強誘電特性の劣化を十分に抑えることはできないことが判明した。   In this regard, Patent Document 3 discloses a configuration in which a conductive material is deposited on a surface when the surface of the surface becomes rough as a result of needle contact using a probe, as shown in FIG. Has been. However, in the first place, Patent Document 3 adopts an extremely simple configuration in which a wiring layer also serving as a conductive pad is connected to an impurity region immediately below. Therefore, although it is an excellent memory such as FeRAM, it cannot be applied to a complicated element configuration having a new problem. As a result of intensive studies by the present inventor, it has been found that even if a conductive material is deposited on a cracked conductive pad by applying this technique to FeRAM, the deterioration of the ferroelectric characteristics in the capacitor film cannot be sufficiently suppressed. did.

ＦｅＲＡＭにおいては、上記のような導電パッドの亀裂部位のみならず、当該導電パッドの周辺も水分含有量の最も多い部位の一つである。即ち導電パッドは、外部との電気的接続を図るために表面の一部がパシベーション膜に形成された開口から露出するように形成されており、この開口における絶縁部材から水分・水素が容易に内部へ浸入し、強誘電体膜の劣化を惹起する。 In FeRAM, not only the cracked portion of the conductive pad as described above but also the periphery of the conductive pad is one of the portions with the highest moisture content. That is, the conductive pad is formed so that a part of the surface is exposed from the opening formed in the passivation film in order to make electrical connection with the outside, and moisture and hydrogen can be easily contained from the insulating member in this opening. Invade the ferroelectric film and cause deterioration of the ferroelectric film.

本発明者は、水分・水素の内部侵入を可及的に抑止すべく、導電パッドの亀裂の問題に加えて、導電パッドの周辺に存する絶縁部材の問題にも着目し、以下で説明する本発明の基本構成に想到した。   In order to suppress moisture and hydrogen from entering inside as much as possible, the inventor pays attention not only to the problem of cracking of the conductive pad but also to the problem of the insulating member existing around the conductive pad. The basic configuration of the invention has been conceived.

本発明では、検査機器のプローブが直接的に当接することで各種の試験が施される導電パッド（第１の導電パッド）を形成し、第１の導電パッド及び配線構造を覆うようにパッシベーション膜を形成した後、パッシベーション膜に、第１の導電パッドの表面における検査の部位のみを露出させる開口を形成する。その後、この開口から第１の導電パッドの表面に各種試験を施す。そして、各種試験を施した後、亀裂等の生じた第１の導電パッドに生じた亀裂等を保護すべく、第１の導電パッドの表面を覆うように、第２の導電パッドを形成する。   In the present invention, a conductive pad (first conductive pad) to be subjected to various tests is formed by directly contacting a probe of an inspection device, and a passivation film is formed so as to cover the first conductive pad and the wiring structure. Then, an opening is formed in the passivation film to expose only the inspection site on the surface of the first conductive pad. Thereafter, various tests are performed on the surface of the first conductive pad from this opening. Then, after performing various tests, a second conductive pad is formed so as to cover the surface of the first conductive pad in order to protect the crack or the like generated in the first conductive pad in which a crack or the like has occurred.

ここで、上記の考察から、半導体メモリの微細化の要請と、圧電素子である強誘電体キャパシタ構造を擁するＦｅＲＡＭに固有の要請とを共に満たすには、先ず、第１の導電パッドを強誘電体キャパシタ構造の上方箇所から離間させた局所的な領域に形成することが必須である。そして、第２の導電パッドが例えば様々なレイアウト上の制約を受けても強誘電体キャパシタ構造の上方箇所に位置しないようにするには、第２の導電パッドを平面視で第１の導電パッドと整合する位置に形成することが最も確実な手法である。この場合、更に確実を期すために、平面視で第１の導電パッドの形成領域に包含される形状となるように第２の導電パッドを形成すれば良い。   Here, from the above consideration, in order to satisfy both the demand for miniaturization of the semiconductor memory and the demand specific to the FeRAM having the ferroelectric capacitor structure which is a piezoelectric element, first, the first conductive pad is made ferroelectric. It is essential to form it in a local region separated from the upper part of the body capacitor structure. In order to prevent the second conductive pad from being positioned at an upper portion of the ferroelectric capacitor structure even if, for example, various layout restrictions are imposed, the second conductive pad is viewed in a plan view. It is the most reliable method to form it at a position that matches. In this case, in order to further ensure, the second conductive pad may be formed so as to have a shape included in the first conductive pad formation region in plan view.

更に、第１の導電パッドの周辺に存する絶縁部材からの水分・水素の浸入も防止すべく、パシベーション膜の開口に整合した位置で、パシベーション膜上から開口の内壁面にかけて覆い、第１の導電パッドと電気的に接続されるように第２の導電パッドをパターン形成する。パシベーション膜の開口の内壁側面が最も顕著な水分・水素の浸入経路となることから、この内壁底面（即ち第１の導電パッドの表面）及び内壁側面からパシベーション膜上にかけて覆うように第２の導電パッドを形成することにより、当該浸入経路が閉ざされてキャパシタ膜の強誘電特性を十分に保持することができる。   Furthermore, in order to prevent moisture and hydrogen from entering the insulating member around the first conductive pad, the first conductive pad is covered from the passivation film to the inner wall surface of the opening at a position aligned with the opening of the passivation film. A second conductive pad is patterned so as to be electrically connected to the pad. Since the inner wall side surface of the opening of the passivation film is the most prominent moisture / hydrogen infiltration path, the second conductive layer is covered from the inner wall bottom surface (that is, the surface of the first conductive pad) and the inner wall side surface to the passivation film. By forming the pad, the penetration path is closed and the ferroelectric characteristics of the capacitor film can be sufficiently retained.

−本発明を適用した具体的な諸実施形態−
以下、本発明を適用した具体的な諸実施形態について、図面を参照しながら詳細に説明する。以下の諸実施形態では、本発明をＦｅＲＡＭに適用した場合について例示するが、キャパシタ構造に通常の誘電体膜を用いた半導体メモリにも適用可能である。-Specific embodiments to which the present invention is applied-
Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the following embodiments, the case where the present invention is applied to FeRAM will be exemplified, but the present invention can also be applied to a semiconductor memory using a normal dielectric film as a capacitor structure.

（第１の実施形態）
本実施形態では、強誘電体キャパシタ構造の下部電極上及び上部電極上にそれぞれ導電プラグが形成されて導通がとられる構成の、いわゆるプレーナ型のＦｅＲＡＭを例示する。
図１Ａ〜図１０は、第１の実施形態によるプレーナ型のＦｅＲＡＭの構成をその製造方法と共に工程順に示す概略断面図である。(First embodiment)
In the present embodiment, a so-called planar type FeRAM having a configuration in which conductive plugs are respectively formed on the lower electrode and the upper electrode of the ferroelectric capacitor structure to establish conduction is illustrated.
FIG. 1A to FIG. 10 are schematic cross-sectional views showing the structure of the planar type FeRAM according to the first embodiment along with its manufacturing method in the order of steps.

先ず、図１Ａに示すように、シリコン半導体基板１０上に選択トランジスタとして機能するＭＯＳトランジスタ２０を形成する。
詳細には、シリコン半導体基板１０の表層に例えばＳＴＩ（Shallow Trench
Isolation）法により素子分離構造１１を形成し、素子活性領域を確定する。
次に、素子活性領域に不純物、ここではホウ素（Ｂ）を例えばドーズ量３．０×１０１３／ｃｍ２、加速エネルギー３００ｋｅＶの条件でイオン注入し、ウェル１２を形成する。First, as shown in FIG. 1A, a MOS transistor 20 that functions as a selection transistor is formed on a silicon semiconductor substrate 10.
More specifically, for example, on the surface layer of the silicon semiconductor substrate 10, for example, STI (Shallow Trench).
An element isolation structure 11 is formed by an isolation method, and an element active region is determined.
Next, an impurity, here boron (B), is ion-implanted into the element active region under conditions of a dose amount of 3.0 × 10 13 / cm 2 and an acceleration energy of 300 keV, for example, to form the well 12.

次に、素子活性領域に熱酸化等により膜厚３．０ｎｍ程度の薄いゲート絶縁膜１３を形成し、ゲート絶縁膜１３上にＣＶＤ法により膜厚１８０ｎｍ程度の多結晶シリコン膜及び膜厚２９ｎｍ程度の例えばシリコン窒化膜を堆積し、シリコン窒化膜、多結晶シリコン膜、及びゲート絶縁膜１３をリソグラフィー及びそれに続くドライエッチングにより電極形状に加工することにより、ゲート絶縁膜１３上にゲート電極１４をパターン形成する。このとき同時に、ゲート電極１４上にはシリコン窒化膜からなるキャップ膜１５がパターン形成される。   Next, a thin gate insulating film 13 having a thickness of about 3.0 nm is formed in the element active region by thermal oxidation or the like, and a polycrystalline silicon film having a thickness of about 180 nm and a thickness of about 29 nm are formed on the gate insulating film 13 by a CVD method. For example, a silicon nitride film is deposited, and the gate electrode 14 is patterned on the gate insulating film 13 by processing the silicon nitride film, the polycrystalline silicon film, and the gate insulating film 13 into an electrode shape by lithography and subsequent dry etching. Form. At the same time, a cap film 15 made of a silicon nitride film is patterned on the gate electrode 14.

次に、キャップ膜１５をマスクとして素子活性領域に不純物、ここでは砒素（Ａｓ）を例えばドーズ量５．０×１０１４／ｃｍ２、加速エネルギー１０ｋｅＶの条件でイオン注入し、いわゆるＬＤＤ領域１６を形成する。Next, using the cap film 15 as a mask, an impurity, for example, arsenic (As) here is ion-implanted into the element active region under the conditions of a dose amount of 5.0 × 10 14 / cm 2 and an acceleration energy of 10 keV to form a so-called LDD region 16. Form.

次に、全面に例えばシリコン酸化膜をＣＶＤ法により堆積し、このシリコン酸化膜をいわゆるエッチバックすることにより、ゲート電極１４及びキャップ膜１５の側面のみにシリコン酸化膜を残してサイドウォール絶縁膜１７を形成する。   Next, for example, a silicon oxide film is deposited on the entire surface by the CVD method, and this silicon oxide film is so-called etched back, thereby leaving the silicon oxide film only on the side surfaces of the gate electrode 14 and the cap film 15 to form the sidewall insulating film 17. Form.

次に、キャップ膜１５及びサイドウォール絶縁膜１７をマスクとして素子活性領域に不純物、ここではリン（Ｐ）をＬＤＤ領域１６よりも高不純物濃度となる条件でイオン注入し、ＬＤＤ領域１６と重畳されるソース／ドレイン領域１８を形成して、ＭＯＳトランジスタ２０を完成させる。なお、図１Ｂ以降では、シリコン半導体基板１０、ウェル１２、素子分離構造１１、ＬＤＤ領域１６、及びソース／ドレイン領域１８の図示を省略する。   Next, using the cap film 15 and the sidewall insulating film 17 as a mask, an impurity, in this case, phosphorus (P) is ion-implanted under a condition that the impurity concentration is higher than that of the LDD region 16 and overlapped with the LDD region 16. A source / drain region 18 is formed to complete the MOS transistor 20. In FIG. 1B and subsequent figures, illustration of the silicon semiconductor substrate 10, the well 12, the element isolation structure 11, the LDD region 16, and the source / drain region 18 is omitted.

続いて、図１Ｂに示すように、ＭＯＳトランジスタ１０の保護膜２１及び第１の層間絶縁膜２２を形成する。
詳細には、ＭＯＳトランジスタ２０を覆うように、保護膜２１及び層間絶縁膜２２を順次堆積する。ここで、保護膜２１としては、シリコン酸化膜を材料とし、ＣＶＤ法により膜厚２０ｎｍ程度に堆積する。層間絶縁膜２２としては、例えばプラズマＳｉＯＮ膜(膜厚２００ｎｍ程度)、プラズマＳｉＮ膜(膜厚８０ｎｍ程度)及びプラズマＴＥＯＳ−ＮＳＧ膜(膜厚６００ｎｍ程度)を順次成膜した積層構造を形成し、積層後、ＣＭＰにより層間絶縁膜２２の表層を例えば２００ｎｍ程度研磨して平坦化する。Subsequently, as shown in FIG. 1B, a protective film 21 and a first interlayer insulating film 22 of the MOS transistor 10 are formed.
Specifically, a protective film 21 and an interlayer insulating film 22 are sequentially deposited so as to cover the MOS transistor 20. Here, as the protective film 21, a silicon oxide film is used as a material, and is deposited to a film thickness of about 20 nm by a CVD method. As the interlayer insulating film 22, for example, a stacked structure in which a plasma SiON film (film thickness of about 200 nm), a plasma SiN film (film thickness of about 80 nm) and a plasma TEOS-NSG film (film thickness of about 600 nm) are sequentially formed is formed. After lamination, the surface layer of the interlayer insulating film 22 is planarized by polishing, for example, about 200 nm by CMP.

続いて、図１Ｃに示すように、層間絶縁膜２２の上層膜２３ａ及び後述する強誘電体キャパシタ構造３０の強誘電体特性の劣化を防止するための水素拡散防止膜２３ｂを順次形成する。   Subsequently, as shown in FIG. 1C, an upper layer film 23a of the interlayer insulating film 22 and a hydrogen diffusion preventing film 23b for preventing deterioration of ferroelectric characteristics of a ferroelectric capacitor structure 30 described later are sequentially formed.

詳細には、先ず、層間絶縁膜２２上にプラズマＴＥＯＳ−ＮＳＧ膜を膜厚１００ｎｍ程度に堆積して、上層膜２３ａを形成する。その後、例えばＮ２ガスを３０リットル／分の流量で供給しながら６５０℃で３０分間程度の脱水処理をＴＥＯＳ−ＮＳＧ膜に施す。Specifically, first, a plasma TEOS-NSG film is deposited on the interlayer insulating film 22 to a thickness of about 100 nm to form an upper layer film 23a. After that, for example, a TEOS-NSG film is subjected to dehydration treatment at 650 ° C. for about 30 minutes while supplying N 2 gas at a flow rate of 30 liters / minute.

次に、後述する強誘電体キャパシタ構造３０の強誘電体膜２５の受けるダメージ（強誘電体膜２５に対する水分・水素の浸入等）を抑制するためのものであり、金属酸化膜、例えばアルミナ（Ａｌ２Ｏ３）を材料として例えばスパッタ法により膜厚２０ｎｍ程度に堆積し、水素拡散防止膜２３ｂを形成する。Next, in order to suppress damage to the ferroelectric film 25 of the ferroelectric capacitor structure 30 to be described later (moisture and hydrogen permeation into the ferroelectric film 25, etc.), a metal oxide film such as alumina ( Al 2 O 3 ) is used as a material, for example, deposited to a film thickness of about 20 nm by a sputtering method to form a hydrogen diffusion preventing film 23b.

続いて、図１Ｄに示すように、下部電極層２４、強誘電体膜２５及び上部電極層２６を順次形成する。
詳細には、先ずスパッタ法により例えば膜厚が２０ｎｍ程度のＴｉ膜及び膜厚が１５０ｎｍ程度のＰｔ膜を順次堆積させ、Ｔｉ膜及びＰｔ膜の積層構造に下部電極層２４を形成する。Subsequently, as shown in FIG. 1D, a lower electrode layer 24, a ferroelectric film 25, and an upper electrode layer 26 are sequentially formed.
Specifically, first, for example, a Ti film having a thickness of about 20 nm and a Pt film having a thickness of about 150 nm are sequentially deposited by sputtering to form the lower electrode layer 24 in a laminated structure of the Ti film and the Pt film.

次に、ＲＦスパッタ法により、下部電極層２４上に強誘電体である例えばＰＺＴからなる強誘電体膜２５を膜厚２００ｎｍ程度に堆積する。そして、強誘電体膜２５にＲＴＡ処理を施して当該強誘電体膜２５を結晶化する。
なお、強誘電体膜２５の材料としては、ＰＺＴの代わりに、Ｐｂ１−ｘＬａｘＺｒ１−ｙＴｉｙＯ３（０＜ｘ＜１，０＜ｙ＜１）、ＳｒＢｉ２（ＴａｘＮｂ１−ｘ）２Ｏ９（０＜ｘ＜１）、Ｂｉ４Ｔｉ２Ｏ１２等を用いても良い。Next, a ferroelectric film 25 made of a ferroelectric material such as PZT is deposited on the lower electrode layer 24 to a thickness of about 200 nm by RF sputtering. Then, the ferroelectric film 25 is subjected to RTA treatment to crystallize the ferroelectric film 25.
As the material of the ferroelectric film 25, instead of PZT, Pb 1-x La x Zr 1-y Ti y O 3 (0 <x <1,0 <y <1), SrBi 2 (Ta x nb 1-x) 2 O 9 (0 <x <1), may be used Bi 4 Ti 2 O 12 and the like.

次に、反応性スパッタ法により、強誘電体膜２５上に例えば導電性酸化物であるＩｒＯ２を材料とする上部電極層２６を膜厚２００ｎｍ程度に堆積する。
なお、上部電極層２６の材料として、ＩｒＯ２の代わりにＩｒ、Ｒｕ、ＲｕＯ２、ＳｒＲｕＯ３、その他の導電性酸化物やこれらの積層構造としても良い。Next, the upper electrode layer 26 made of, for example, IrO 2 which is a conductive oxide is deposited on the ferroelectric film 25 to a thickness of about 200 nm by the reactive sputtering method.
Note that the material of the upper electrode layer 26 may be Ir, Ru, RuO 2 , SrRuO 3 , other conductive oxides, or a stacked structure thereof instead of IrO 2 .

続いて、図２Ａに示すように、上部電極３１をパターン形成する。
詳細には、上部電極層２６をリソグラフィー及びそれに続くドライエッチングにより複数の電極形状に加工して、上部電極３１をパターン形成する。Subsequently, as shown in FIG. 2A, the upper electrode 31 is patterned.
Specifically, the upper electrode layer 26 is processed into a plurality of electrode shapes by lithography and subsequent dry etching, and the upper electrode 31 is patterned.

続いて、図２Ｂに示すように、強誘電体膜２５及び下部電極層２４を加工して強誘電体キャパシタ構造３０を形成する。
詳細には、先ず強誘電体膜２５を上部電極３１に整合させて若干上部電極３１よりも大きいサイズとなるように、リソグラフィー及びそれに続くドライエッチングにより加工する。Subsequently, as shown in FIG. 2B, the ferroelectric film 25 and the lower electrode layer 24 are processed to form a ferroelectric capacitor structure 30.
Specifically, first, the ferroelectric film 25 is processed by lithography and subsequent dry etching so that the ferroelectric film 25 is aligned with the upper electrode 31 and becomes slightly larger than the upper electrode 31.

次に、下部電極層２４を、加工された強誘電体膜２５に整合させて若干強誘電体膜２５よりも大きいサイズとなるように、リソグラフィー及びそれに続くドライエッチングにより加工し、下部電極３２をパターン形成する。これにより、下部電極３２上に強誘電体膜２５、上部電極３１が順次積層され、強誘電体膜２５を介して下部電極３２と上部電極３１とが容量結合する強誘電体キャパシタ構造３０を完成させる。   Next, the lower electrode layer 24 is processed by lithography and subsequent dry etching so that the lower electrode layer 24 is aligned with the processed ferroelectric film 25 and has a slightly larger size than the ferroelectric film 25, and the lower electrode 32 is processed. Form a pattern. Thus, the ferroelectric film 25 and the upper electrode 31 are sequentially stacked on the lower electrode 32, and the ferroelectric capacitor structure 30 in which the lower electrode 32 and the upper electrode 31 are capacitively coupled through the ferroelectric film 25 is completed. Let

続いて、図２Ｃに示すように、層間絶縁膜３３を成膜する。
詳細には、強誘電体キャパシタ構造３０を覆うように、層間絶縁膜３３を形成する。ここで、層間絶縁膜３３としては、例えばプラズマＴＥＯＳ−ＮＳＧ膜を膜厚１５００ｎｍ程度に堆積した後、ＣＭＰにより膜厚が１０００ｎｍ程度となるまで研磨する。ＣＭＰの後に、層間絶縁膜３３の表面の窒化を目的として、例えばＮ２Ｏのプラズマアニール処理（例えば３５０℃で２分間）を施す。Subsequently, as shown in FIG. 2C, an interlayer insulating film 33 is formed.
Specifically, the interlayer insulating film 33 is formed so as to cover the ferroelectric capacitor structure 30. Here, as the interlayer insulating film 33, for example, a plasma TEOS-NSG film is deposited to a thickness of about 1500 nm, and then polished by CMP until the thickness becomes about 1000 nm. After CMP, for example, N 2 O plasma annealing (for example, at 350 ° C. for 2 minutes) is performed for the purpose of nitriding the surface of the interlayer insulating film 33.

続いて、図２Ｄに示すように、強誘電体キャパシタ構造３０のプラグ３４，３５及びトランジスタ構造２０のソース／ドレイン領域１８と接続されるプラグ３６を形成する。
先ず、強誘電体キャパシタ構造３０へのビア孔３４ａ，３５ａを形成する。
詳細には、リソグラフィー及びそれに続くドライエッチングとして、上部電極３１の表面の一部が露出するまで層間絶縁膜３３に施す加工と、下部電極３２の表面の一部が露出するまで層間絶縁膜３３に施す加工とを同時に実行し、それぞれの部位に例えば約０．５μｍ径のビア孔３４ａ，３５ａを同時形成する。これらビア孔３４ａ，３５ａの形成時には、上部電極３１及び下部電極３２がそれぞれエッチングストッパーとなる。Subsequently, as shown in FIG. 2D, plugs 34 and 35 of the ferroelectric capacitor structure 30 and plugs 36 connected to the source / drain regions 18 of the transistor structure 20 are formed.
First, via holes 34a and 35a to the ferroelectric capacitor structure 30 are formed.
Specifically, as lithography and subsequent dry etching, processing performed on the interlayer insulating film 33 until a part of the surface of the upper electrode 31 is exposed, and on the interlayer insulating film 33 until a part of the surface of the lower electrode 32 is exposed. For example, via holes 34a and 35a having a diameter of about 0.5 μm are simultaneously formed in the respective portions. When these via holes 34a and 35a are formed, the upper electrode 31 and the lower electrode 32 each serve as an etching stopper.

次に、強誘電体キャパシタ構造３０の形成後の諸工程により強誘電体キャパシタ構造３０の受けたダメージを回復するためのアニール処理を行う。ここでは、処理温度５００℃、酸素雰囲気で６０分間のアニール処理を実行する。   Next, an annealing process is performed to recover the damage received by the ferroelectric capacitor structure 30 through various steps after the formation of the ferroelectric capacitor structure 30. Here, an annealing process is performed for 60 minutes in a processing temperature of 500 ° C. and an oxygen atmosphere.

次に、トランジスタ構造１０のソース／ドレイン領域１８へのビア孔３６ａを形成する。
詳細には、ソース／ドレイン領域１８をエッチングストッパーとして、当該ソース／ドレイン領域１８の表面の一部が露出するまで第２の層間絶縁膜３３、水素拡散防止２３ｂ、上層膜２３ａ、層間絶縁膜２２、及び保護膜２１をリソグラフィー及びそれに続くドライエッチングにより加工し、例えば約０．３μｍ径のビア孔３６ａを形成する。Next, a via hole 36 a to the source / drain region 18 of the transistor structure 10 is formed.
Specifically, using the source / drain region 18 as an etching stopper, the second interlayer insulating film 33, the hydrogen diffusion preventing 23b, the upper layer film 23a, and the interlayer insulating film 22 until a part of the surface of the source / drain region 18 is exposed. The protective film 21 is processed by lithography and subsequent dry etching to form a via hole 36a having a diameter of about 0.3 μm, for example.

次に、プラグ３４，３５，３６を形成する。
先ず、通常の酸化膜のエッチング換算で数１０ｎｍ、ここでは１０ｎｍ程度に相当するＲＦ前処理を行った後、ビア孔３４ａ，３５ａ，３６ａの各壁面を覆うように、スパッタ法により例えばＴｉＮ膜を膜厚７５ｎｍ程度に堆積して、下地膜（グルー膜）４１を形成する。そして、ＣＶＤ法によりグルー膜４１を介してビア孔３４ａ，３５ａ，３６ａを埋め込むように例えばＷ膜を形成する。その後、ＣＭＰにより第２の層間絶縁膜３３をストッパーとしてＷ膜及びグルー膜４１を研磨し、ビア孔３４ａ，３５ａ，３６ａ内をグルー膜４１を介してＷで埋め込むプラグ３４，３５，３６を形成する。Next, plugs 34, 35, and 36 are formed.
First, after performing RF pretreatment corresponding to several tens of nm in terms of etching of a normal oxide film, here about 10 nm, a TiN film, for example, is formed by sputtering so as to cover the wall surfaces of the via holes 34a, 35a, 36a. A base film (glue film) 41 is formed by depositing to a thickness of about 75 nm. Then, for example, a W film is formed so as to fill the via holes 34a, 35a, 36a via the glue film 41 by the CVD method. Thereafter, the W film and the glue film 41 are polished by CMP using the second interlayer insulating film 33 as a stopper to form plugs 34, 35, and 36 that fill the via holes 34 a, 35 a, and 36 a with W via the glue film 41. To do.

続いて、図３Ａに示すように、プラグ３４，３５，３６とそれぞれ接続される第１の配線４５を形成する。
詳細には、先ず、全面に例えばＰＶＤ法によりバリアメタル膜４２、配線膜４３及びバリアメタル膜４４を堆積する。バリアメタル膜４２としては、スパッタ法により例えばＴｉＮ膜を膜厚１５０ｎｍ程度に成膜する。配線膜４３としては、例えばＡｌ合金膜（ここではＡｌ−Ｃｕ膜）を膜厚５５０ｎｍ程度に成膜する。バリアメタル膜４４としては、スパッタ法により例えばＴｉ膜（膜厚５ｎｍ程度）及びＴｉＮ（膜厚１５０ｎｍ程度）を順次成膜する。ここで、配線膜４３の構造は、同一ルールのＦｅＲＡＭ以外のロジック部と同じ構造とされているため、配線の加工や信頼性上の問題はない。Subsequently, as shown in FIG. 3A, first wirings 45 connected to the plugs 34, 35, and 36, respectively, are formed.
Specifically, first, a barrier metal film 42, a wiring film 43, and a barrier metal film 44 are deposited on the entire surface by, eg, PVD. As the barrier metal film 42, for example, a TiN film is formed with a film thickness of about 150 nm by sputtering. As the wiring film 43, for example, an Al alloy film (here, an Al—Cu film) is formed to a film thickness of about 550 nm. As the barrier metal film 44, for example, a Ti film (film thickness of about 5 nm) and TiN (film thickness of about 150 nm) are sequentially formed by sputtering. Here, since the structure of the wiring film 43 is the same as that of the logic part other than the FeRAM having the same rule, there is no problem in processing of the wiring and reliability.

次に、反射防止膜として例えばＳｉＯＮ膜または反射防止膜（不図示）を成膜した後、リソグラフィー及びそれに続くドライエッチングにより反射防止膜、バリアメタル膜４４、配線膜４３及びバリアメタル膜４２を配線形状に加工し、第１の配線４５をパターン形成する。ここで、第１の配線４５と同一構造の耐湿リング４５ａも第１の配線４５と同時に形成するが、図示の都合上、図４以降に示す。なお、配線膜４３としてＡｌ合金膜を形成する代わりに、いわゆるダマシン法等を利用してＣｕ膜（又はＣｕ合金膜）を形成し、第１の配線４５としてＣｕ配線を形成しても良い。   Next, after forming, for example, a SiON film or an antireflection film (not shown) as an antireflection film, the antireflection film, the barrier metal film 44, the wiring film 43, and the barrier metal film 42 are wired by lithography and subsequent dry etching. The first wiring 45 is patterned by processing into a shape. Here, the moisture-resistant ring 45a having the same structure as that of the first wiring 45 is also formed at the same time as the first wiring 45. However, for the sake of illustration, FIG. Instead of forming an Al alloy film as the wiring film 43, a Cu film (or Cu alloy film) may be formed using a so-called damascene method or the like, and a Cu wiring may be formed as the first wiring 45.

続いて、図３Ｂに示すように、強誘電体キャパシタ構造３０の強誘電体特性劣化を防止するための水素拡散防止膜４６を形成する。
詳細には、第１の配線４５を覆うように、第２の層間絶縁膜３３上に保護膜４６を成膜する。保護膜４６は、強誘電体キャパシタ構造３０を形成した後の多層工程により当該強誘電体キャパシタ３０の強誘電体膜２５の受けるダメージ（強誘電体膜２５に対する水分・水素の浸入等）を抑制するためのものであり、金属酸化膜、例えばアルミナ（Ａｌ２Ｏ３）を材料として例えばスパッタ法により膜厚２０ｎｍ程度に形成する。Subsequently, as shown in FIG. 3B, a hydrogen diffusion preventing film 46 for preventing deterioration of the ferroelectric characteristics of the ferroelectric capacitor structure 30 is formed.
Specifically, a protective film 46 is formed on the second interlayer insulating film 33 so as to cover the first wiring 45. The protective film 46 suppresses damage received by the ferroelectric film 25 of the ferroelectric capacitor 30 (moisture / hydrogen intrusion into the ferroelectric film 25, etc.) due to the multilayer process after the ferroelectric capacitor structure 30 is formed. For example, a metal oxide film such as alumina (Al 2 O 3 ) is used as a material to form a film having a thickness of about 20 nm by sputtering.

続いて、図４に示すように、第１の配線４５とプラグ４８を介して接続される第２の配線５３を形成する。
詳細には、先ず、水素拡散防止膜４６を介して第１の配線４５（及び耐湿リング４５ａ）を覆うように層間絶縁膜４７及びその上層膜４７ａを形成する。Subsequently, as shown in FIG. 4, a second wiring 53 connected to the first wiring 45 through the plug 48 is formed.
Specifically, first, the interlayer insulating film 47 and the upper layer film 47a are formed so as to cover the first wiring 45 (and the moisture-resistant ring 45a) through the hydrogen diffusion preventing film 46.

層間絶縁膜４７としては、プラズマＴＥＯＳ−ＮＳＧ膜を膜厚２６００ｎｍ程度に堆積した後、その表層をＣＭＰ等により除去して表面を平坦化して形成する。そして、層間絶縁膜４７の表面の窒化を目的として、例えばＮ２Ｏのプラズマアニール処理（例えば３５０℃で４分間）を施す。The interlayer insulating film 47 is formed by depositing a plasma TEOS-NSG film to a thickness of about 2600 nm and then removing the surface layer by CMP or the like to planarize the surface. Then, for the purpose of nitriding the surface of the interlayer insulating film 47, for example, N 2 O plasma annealing (for example, at 350 ° C. for 4 minutes) is performed.

上層膜４７ａとしては、プラズマＴＥＯＳ−ＮＳＧ膜を膜厚２６００ｎｍ程度に堆積して形成する。そして、上層膜４７ａの表面の窒化を目的として、例えばＮ２Ｏのプラズマアニール処理（例えば３５０℃で２分間）を施す。As the upper layer film 47a, a plasma TEOS-NSG film is deposited to a thickness of about 2600 nm. Then, for the purpose of nitriding the surface of the upper layer film 47a, for example, N 2 O plasma annealing (for example, at 350 ° C. for 2 minutes) is performed.

次に、配線４５と接続されるプラグ４８を形成する。
第１の配線４５の表面の一部が露出するまで、上層膜４７ａ、層間絶縁膜４７、及び水素拡散防止膜４６をリソグラフィー及びそれに続くドライエッチングにより加工して、例えば約０．２５μｍ径のビア孔４８ａを形成する。次に、このビア孔４８ａの壁面を覆うように下地膜（グルー膜）４９を形成した後、ＣＶＤ法によりグルー膜４９を介してビア孔４８ａを埋め込むようにＷ膜を形成する。そして、上層膜４７ａをストッパーとして例えばＷ膜及びグルー膜４９を研磨し、ビア孔４８ａ内をグルー膜４９を介してＷで埋め込むプラグ４８を形成する。Next, a plug 48 connected to the wiring 45 is formed.
The upper layer film 47a, the interlayer insulating film 47, and the hydrogen diffusion prevention film 46 are processed by lithography and subsequent dry etching until a part of the surface of the first wiring 45 is exposed, for example, a via having a diameter of about 0.25 μm. Hole 48a is formed. Next, after forming a base film (glue film) 49 so as to cover the wall surface of the via hole 48a, a W film is formed by the CVD method so as to fill the via hole 48a through the glue film 49. Then, for example, the W film and the glue film 49 are polished using the upper layer film 47 a as a stopper to form a plug 48 that fills the via hole 48 a with W via the glue film 49.

次に、プラグ４８とそれぞれ接続される第２の配線５３を形成する。
先ず、全面に例えばＰＶＤ法により配線膜５１及びバリアメタル膜５２を堆積する。配線膜５１としては、例えばＡｌ合金膜（ここではＡｌ−Ｃｕ膜）を膜厚５５０ｎｍ程度に成膜する。バリアメタル膜５２としては、スパッタ法により例えばＴｉ膜（膜厚５ｎｍ程度）及びＴｉＮ（膜厚１５０ｎｍ程度）を順次成膜する。ここで、配線膜５１の構造は、同一ルールのＦｅＲＡＭ以外のロジック部と同じ構造とされているため、配線の加工や信頼性上の問題はない。Next, the second wiring 53 connected to the plug 48 is formed.
First, the wiring film 51 and the barrier metal film 52 are deposited on the entire surface by, for example, the PVD method. As the wiring film 51, for example, an Al alloy film (here, an Al—Cu film) is formed to a film thickness of about 550 nm. As the barrier metal film 52, for example, a Ti film (film thickness of about 5 nm) and TiN (film thickness of about 150 nm) are sequentially formed by sputtering. Here, since the structure of the wiring film 51 is the same as that of the logic part other than the FeRAM having the same rule, there is no problem in processing of the wiring and reliability.

次に、反射防止膜として例えばＳｉＯＮ膜または反射防止膜（不図示）を成膜した後、リソグラフィー及びそれに続くドライエッチングにより反射防止膜、バリアメタル膜５２及び配線膜５１を配線形状に加工し、第２の配線５３をパターン形成する。このとき、第２の配線５３と同一構造に、耐湿リング４５ａとプラグ４７を介して接続されてなる耐湿リング５３ａを形成する。なお、配線膜５１としてＡｌ合金膜を形成する代わりに、いわゆるダマシン法等を利用してＣｕ膜（又はＣｕ合金膜）を形成し、第２の配線５３としてＣｕ配線を形成しても良い。   Next, after forming, for example, a SiON film or an antireflection film (not shown) as an antireflection film, the antireflection film, the barrier metal film 52 and the wiring film 51 are processed into a wiring shape by lithography and subsequent dry etching, A pattern of the second wiring 53 is formed. At this time, the moisture-resistant ring 53 a connected to the moisture-resistant ring 45 a and the plug 47 is formed in the same structure as the second wiring 53. Instead of forming an Al alloy film as the wiring film 51, a Cu film (or Cu alloy film) may be formed using a so-called damascene method or the like, and a Cu wiring may be formed as the second wiring 53.

続いて、図５に示すように、第２の配線５３とプラグ５５により接続される第３の配線６３及び第１の導電パッド６０を形成する。
詳細には、先ず、配線５３（及び耐湿リング５３ａ）を覆うように層間絶縁膜５４及びその上層膜５４ａを形成する。Subsequently, as shown in FIG. 5, the third wiring 63 and the first conductive pad 60 connected to the second wiring 53 and the plug 55 are formed.
Specifically, first, the interlayer insulating film 54 and the upper layer film 54a are formed so as to cover the wiring 53 (and the moisture-resistant ring 53a).

層間絶縁膜５４としては、プラズマＴＥＯＳ−ＮＳＧ膜を膜厚２２００ｎｍ程度に堆積した後、その表層をＣＭＰ等により除去して表面を平坦化して形成する。そして、層間絶縁膜５４の表面の窒化を目的として、例えばＮ２Ｏのプラズマアニール処理（例えば３５０℃で４分間）を施す。The interlayer insulating film 54 is formed by depositing a plasma TEOS-NSG film to a thickness of about 2200 nm and then removing the surface layer by CMP or the like to planarize the surface. Then, for example, N 2 O plasma annealing (for example, at 350 ° C. for 4 minutes) is performed for the purpose of nitriding the surface of the interlayer insulating film 54.

上層膜５４ａとしては、プラズマＴＥＯＳ−ＮＳＧ膜を膜厚２６００ｎｍ程度に堆積して形成する。そして、上層膜５４ａの表面の窒化を目的として、例えばＮ２Ｏのプラズマアニール処理（例えば３５０℃で２分間）を施す。As the upper layer film 54a, a plasma TEOS-NSG film is deposited to a thickness of about 2600 nm. Then, for the purpose of nitriding the surface of the upper layer film 54a, for example, plasma annealing of N 2 O (for example, at 350 ° C. for 2 minutes) is performed.

次に、第２の配線５３と接続されるプラグ５５を形成する。
第２の配線５３の表面の一部が露出するまで、上層膜５４ａ及び層間絶縁膜５４をリソグラフィー及びそれに続くドライエッチングにより加工して、ビア孔５５ａを形成する。次に、このビア孔５５ａの壁面を覆うように下地膜（グルー膜）５６を形成した後、ＣＶＤ法によりグルー膜５６を介してビア孔５５ａを埋め込むようにＷ膜を形成する。そして、上層膜５４ａをストッパーとして例えばＷ膜及びグルー膜５６を研磨し、ビア孔５５ａ内をグルー膜５６を介してＷで埋め込むプラグ５５を形成する。Next, a plug 55 connected to the second wiring 53 is formed.
The upper layer film 54a and the interlayer insulating film 54 are processed by lithography and subsequent dry etching until a part of the surface of the second wiring 53 is exposed, thereby forming a via hole 55a. Next, after forming a base film (glue film) 56 so as to cover the wall surface of the via hole 55a, a W film is formed by the CVD method so as to fill the via hole 55a through the glue film 56. Then, for example, the W film and the glue film 56 are polished using the upper layer film 54 a as a stopper to form a plug 55 that fills the via hole 55 a with W via the glue film 56.

次に、プラグ５５とそれぞれ接続される第３の配線６３及び第１の導電パッド６０を形成する。
先ず、全面に例えばＰＶＤ法により配線膜６１及びバリアメタル膜６２を堆積する。配線膜６１としては、例えばＡｌ合金膜（ここではＡｌ−Ｃｕ膜）を膜厚５００ｎｍ程度に成膜する。バリアメタル膜６２としては、スパッタ法により例えばＴｉＮを膜厚１５０ｎｍ程度に成膜する。ここで、配線膜６１の構造は、同一ルールのＦｅＲＡＭ以外のロジック部と同じ構造とされているため、配線の加工や信頼性上の問題はない。Next, a third wiring 63 and a first conductive pad 60 connected to the plug 55 are formed.
First, a wiring film 61 and a barrier metal film 62 are deposited on the entire surface by, eg, PVD. As the wiring film 61, for example, an Al alloy film (here, an Al—Cu film) is formed to a thickness of about 500 nm. As the barrier metal film 62, for example, TiN is formed to a film thickness of about 150 nm by sputtering. Here, since the structure of the wiring film 61 is the same as that of the logic part other than the FeRAM of the same rule, there is no problem in processing of the wiring or reliability.

次に、反射防止膜として例えばＳｉＯＮ膜または反射防止膜（不図示）を成膜した後、リソグラフィー及びそれに続くドライエッチングにより反射防止膜、バリアメタル膜６２及び配線膜６１を配線形状に加工し、第３の配線６３をパターン形成する。このとき、第３の配線６３と同一構造に、耐湿リング５３ａとプラグ５５を介して接続されてなる耐湿リング６３ａを形成する。   Next, after forming, for example, a SiON film or an antireflection film (not shown) as an antireflection film, the antireflection film, the barrier metal film 62, and the wiring film 61 are processed into a wiring shape by lithography and subsequent dry etching, A pattern of the third wiring 63 is formed. At this time, the moisture-resistant ring 63 a formed by connecting the moisture-resistant ring 53 a and the plug 55 to the same structure as the third wiring 63 is formed.

ここで、第３の配線６３と同時に、当該第３の配線６３と同一構造であり第２の配線５３とプラグ５５を介して接続されてなる第１の導電パッド６０をパターン形成する。この第１の導電パッド６０は、後述の検査工程における各種試験（プローブによる針当て）が施される検査用パッドであり、ここでは略矩形状に形成されている。ところで、ＦｅＲＡＭの強誘電体キャパシタ構造は言わば圧電素子であり、強誘電体キャパシタ構造の近傍において圧力印加がなされることにより、強誘電特性の著しい劣化を招く。検査工程では針当てにより第１の導電パッド６０に圧力が印加されることは避けられない。そこで本実施形態では、当該劣化を防止するために、強誘電体キャパシタ構造３０の上方位置からできるだけ離間させた位置に第１の導電パッド６０を設ける。   Here, simultaneously with the third wiring 63, the first conductive pad 60 having the same structure as the third wiring 63 and connected to the second wiring 53 via the plug 55 is patterned. The first conductive pad 60 is an inspection pad to be subjected to various tests (needle contact by a probe) in an inspection process described later, and is formed in a substantially rectangular shape here. By the way, the ferroelectric capacitor structure of FeRAM is a so-called piezoelectric element, and when a pressure is applied in the vicinity of the ferroelectric capacitor structure, the ferroelectric characteristics are significantly deteriorated. In the inspection process, it is inevitable that pressure is applied to the first conductive pad 60 by needle contact. Therefore, in this embodiment, in order to prevent the deterioration, the first conductive pad 60 is provided at a position as far as possible from the upper position of the ferroelectric capacitor structure 30.

続いて、図６に示すように、第３の配線６３（耐湿リング６３を含む）及び第１の導電パッド６０を覆うパシベーション膜６６を形成する。
詳細には、先ず、ＣＶＤ法等によりプラズマＴＥＯＳ−ＮＳＧ膜を膜厚１００ｎｍ程度に堆積し、下層絶縁膜６４を形成する。そして、下層絶縁膜６４の表面の窒化を目的として、例えばＮ２Ｏのプラズマアニール処理（例えば３５０℃で２分間）を施す。Subsequently, as shown in FIG. 6, a passivation film 66 that covers the third wiring 63 (including the moisture-resistant ring 63) and the first conductive pad 60 is formed.
Specifically, first, a plasma TEOS-NSG film is deposited to a thickness of about 100 nm by a CVD method or the like to form a lower insulating film 64. Then, for example, N 2 O plasma annealing (for example, at 350 ° C. for 2 minutes) is performed for the purpose of nitriding the surface of the lower insulating film 64.

次に、下層絶縁膜６４上に、ＣＶＤ法等によりプラズマＳｉＮ膜を膜厚３５０ｎｍ程度に堆積し、上層絶縁膜６５を形成する。このとき、下層絶縁膜６４上に上層絶縁膜６５が積層されてなる２層構造のパシベーション膜６６が形成される。本実施形態では、パシベーション膜６６が本発明の保護絶縁膜となる。なお、図示の例では、下層絶縁膜６４及び上層絶縁膜６５の各表面を平坦に示しているが、実際には当該表面は第３の配線６３の影響を受けて若干凹凸状となる。   Next, a plasma SiN film is deposited to a thickness of about 350 nm on the lower insulating film 64 by a CVD method or the like to form an upper insulating film 65. At this time, a passivation film 66 having a two-layer structure in which an upper insulating film 65 is laminated on the lower insulating film 64 is formed. In the present embodiment, the passivation film 66 is the protective insulating film of the present invention. In the illustrated example, the surfaces of the lower insulating film 64 and the upper insulating film 65 are shown flat, but in actuality, the surfaces are slightly uneven due to the influence of the third wiring 63.

続いて、図７に示すように、パシベーション膜６６に開口６６ａを形成する。
詳細には、リソグラフィー及びドライエッチングによりパシベーション膜６６を加工し、第１の導電パッド６０の表面の一部を露出させる開口６６ａを形成する。なお、図７〜図１０では、第１の導電パッド６０及びその周囲の様子を示す平面図を添付する。Subsequently, as shown in FIG. 7, an opening 66 a is formed in the passivation film 66.
Specifically, the passivation film 66 is processed by lithography and dry etching to form an opening 66 a that exposes a part of the surface of the first conductive pad 60. In FIGS. 7 to 10, plan views showing the first conductive pad 60 and the surrounding state are attached.

続いて、図８に示すように、不図示の検査機器を用い、当該検査機器の探針（プローブ）５８を開口６６ａから露出する第１の導電パッド６０に当接（針当て）させて、各種の試験を行う。検査内容としては、装置の動作が正常に行われるか否かを調べる試験（ＰＴ１）、データの書き込み及び読み出しの良否を判定するリテンション試験（ＰＴ２，ＰＴ３）、最終的な確認試験（ＰＴ４）を順次行う。   Subsequently, as shown in FIG. 8, using an inspection device (not shown), the probe (probe) 58 of the inspection device is brought into contact (needle contact) with the first conductive pad 60 exposed from the opening 66a. Perform various tests. As inspection contents, a test (PT1) for checking whether the operation of the apparatus is normally performed, a retention test (PT2, PT3) for determining whether data is written and read, and a final confirmation test (PT4). Do it sequentially.

ＦｅＲＡＭの場合、上記のＰＴ１〜ＰＴ４の各試験が必要であり、各試験時におけるプローブによる第１の導電パッド６０の表面への複数回の当接により、第１の導電パッド６０に亀裂５９等が発生することが多い。   In the case of FeRAM, each of the above-described PT1 to PT4 is required, and the first conductive pad 60 is cracked 59 or the like by a plurality of contact with the surface of the first conductive pad 60 by the probe during each test. Often occurs.

続いて、図９に示すように、第１の導電パッド６０と直接的に接続される第２の導電パッド７０を形成する。
詳細には、開口６６ａの内壁面を覆うように、例えばＰＶＤ法により、パシベーション膜６６上にＡｌ合金膜（ここではＡｌ−Ｃｕ膜：膜厚５００ｎｍ程度）及びＴｉＮ膜（膜厚１５０ｎｍ程度）を積層する。そして、これらＴｉＮ膜及びＡｌ合金膜をリソグラフィー及びそれに続くドライエッチングによりパターニングする。この場合、平面視で第１の導電パッド６０よりも若干サイズが小さくなる程度に、第１の導電パッド６０と同様の略矩形状となるように、当該パターニングを実行する。これにより、パシベーション膜６６の開口６６ａの内壁底面（即ち第１の導電パッド６０の表面）及び内壁側面からパシベーション膜６６上にかけて覆い、平面視で第１の導電パッド６０の形成領域に包含される第２の導電パッド７０が形成される。この第２の導電パッド７０は、ボンディングワイヤ等が接続される外部接続用パッドである。Subsequently, as shown in FIG. 9, a second conductive pad 70 that is directly connected to the first conductive pad 60 is formed.
Specifically, an Al alloy film (here, Al—Cu film: about 500 nm thick) and a TiN film (about 150 nm thick) are formed on the passivation film 66 by, for example, PVD so as to cover the inner wall surface of the opening 66a. Laminate. Then, these TiN film and Al alloy film are patterned by lithography and subsequent dry etching. In this case, the patterning is performed so as to have a substantially rectangular shape similar to that of the first conductive pad 60 so that the size is slightly smaller than that of the first conductive pad 60 in plan view. Thus, the inner wall bottom surface (that is, the surface of the first conductive pad 60) and the inner wall side surface of the opening 66a of the passivation film 66 are covered from the side of the passivation film 66 to be included in the formation region of the first conductive pad 60 in plan view. A second conductive pad 70 is formed. The second conductive pad 70 is an external connection pad to which a bonding wire or the like is connected.

続いて、図１０に示すように、緩衝防止膜７１を形成する。   Subsequently, as shown in FIG. 10, a buffering prevention film 71 is formed.

詳細には、例えば感光性ポリイミドを膜厚３μｍ程度に塗布し、パシベーション膜６６上を覆って保護し、第２の導電パッド７０の表面の一部のみを露出させる開口７１ａを有する緩衝防止膜７１を形成する。ここで、非感光性ポリイミドを用いる場合には、非感光性ポリイミド上にレジストパターンを形成し、専用現像液で非感光性ポリイミドを溶解する。その後、例えば横型炉で緩衝防止膜７１に例えば３１０℃でＮ２ガスを１００リットル／分の流量で４０分間の熱処理を施し、ポリイミドを硬化させる。なお、緩衝防止膜７１の材料として、ポリイミドの代わりに例えばノボラック樹脂を用いても良い。More specifically, for example, a photosensitive polyimide is applied to a film thickness of about 3 μm, covers and protects the passivation film 66, and has a buffering prevention film 71 having an opening 71 a that exposes only a part of the surface of the second conductive pad 70. Form. Here, when non-photosensitive polyimide is used, a resist pattern is formed on the non-photosensitive polyimide, and the non-photosensitive polyimide is dissolved with a dedicated developer. Thereafter, for example, in a horizontal furnace, the buffer film 71 is heat-treated at 310 ° C. at a flow rate of N 2 gas of 100 liters / minute for 40 minutes to cure the polyimide. For example, a novolac resin may be used as the material of the buffer preventing film 71 instead of polyimide.

しかる後、諸々の後工程を実行する。例えば、シリコン半導体基板１０の背面研磨、基板のダイシング、ワイヤ・ボンディング等による、開口７１ａから露出する第２の導電パッド７０の表面への外部接続、パッケージ化、及びパッケージ最終検査等を経て、本実施形態によるＦｅＲＡＭを完成させる。   Thereafter, various post processes are executed. For example, after the backside polishing of the silicon semiconductor substrate 10, substrate dicing, wire bonding, etc., the external connection to the surface of the second conductive pad 70 exposed from the opening 71 a, packaging, and final package inspection, etc. The FeRAM according to the embodiment is completed.

本実施形態では、第１の導電パッド６０の表面に針当てして各種試験を行う検査工程の後に、当該検査により亀裂５９等が生じた第１の導電パッド６０の表面を覆う第２の導電パッド７０を形成する。この第２の導電パッド７０は、第１の導電パッド６０に整合した位置で当該第１の導電パッド６０に包含されるサイズに形成される。即ち、第２の導電パッド７０は、第１の導電パッド６０と同様に、強誘電体キャパシタ構造３０と可及的に離間しており、第２の導電パッド７０の下方には強誘電体キャパシタ構造３０が存しないため、第２の導電パッド７０に外部との接続時に圧力が印加されても強誘電体キャパシタ構造３０に悪影響を与えることはない。   In the present embodiment, the second conductive covering the surface of the first conductive pad 60 in which the crack 59 or the like is generated by the inspection after the inspection process in which various tests are performed by applying a needle to the surface of the first conductive pad 60. A pad 70 is formed. The second conductive pad 70 is formed in a size included in the first conductive pad 60 at a position aligned with the first conductive pad 60. That is, the second conductive pad 70 is separated from the ferroelectric capacitor structure 30 as much as possible, like the first conductive pad 60, and the ferroelectric capacitor is located below the second conductive pad 70. Since the structure 30 does not exist, even if a pressure is applied to the second conductive pad 70 when connected to the outside, the ferroelectric capacitor structure 30 is not adversely affected.

更に、第２の導電パッド７０は、パシベーション膜６６の開口６６ａの内壁底面及び内壁側面からパシベーション膜６６上にかけて覆うように形成される。パシベーション膜６６の開口の内壁側面が最も顕著な水分・水素の浸入経路となることから、この内壁底面（即ち第１の導電パッド６０の表面）及び内壁側面からパシベーション膜６６上にかけて覆うように第２の導電パッド７０を形成することにより、例えば上記の後工程におけるダイシング及びパッケージ化の際にも、当該浸入経路が可及的に閉ざされている。従って、強誘電体膜２５への水分・水素の浸入が可及的に抑止され、強誘電体膜２５の高い強誘電特性が十分に保持される。   Further, the second conductive pad 70 is formed so as to cover the inner wall bottom surface and the inner wall side surface of the opening 66 a of the passivation film 66 over the passivation film 66. Since the inner wall side surface of the opening of the passivation film 66 is the most remarkable moisture / hydrogen infiltration path, the inner wall side surface (that is, the surface of the first conductive pad 60) and the inner wall side surface are covered to cover the passivation film 66. By forming the second conductive pad 70, the intrusion path is closed as much as possible, for example, in the dicing and packaging in the post-process described above. Therefore, the penetration of moisture and hydrogen into the ferroelectric film 25 is suppressed as much as possible, and the high ferroelectric characteristics of the ferroelectric film 25 are sufficiently maintained.

以上説明したように、本実施形態によれば、比較的簡易な構成で十分な水・水素の内部侵入を確実に防止し、強誘電体膜２５を有する強誘電体キャパシタ構造３０の高性能を保持する信頼性の高いＦｅＲＡＭを実現することができる。   As described above, according to the present embodiment, sufficient internal penetration of water and hydrogen can be reliably prevented with a relatively simple configuration, and the high performance of the ferroelectric capacitor structure 30 having the ferroelectric film 25 can be improved. A highly reliable FeRAM can be realized.

（変形例）
以下、第１の実施形態の緒変形例について説明する。これらの変形例では、第１の実施形態と同様にプレーナ型のＦｅＲＡＭを開示するが、第２の導電パッドの形態が若干異なる点で相違する。以下、第１の実施形態で開示した構成部材等と同様のものについては同符号を付して詳しい説明を省略する。(Modification)
Hereinafter, modifications of the first embodiment will be described. In these modified examples, a planar type FeRAM is disclosed as in the first embodiment, but the second conductive pad is different in a slightly different form. Hereinafter, the same components as those disclosed in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

［変形例１］
図１１Ａ〜図１１Ｄは、第１の実施形態の変形例１によるプレーナ型のＦｅＲＡＭの構成をその製造方法（主要工程のみ）と共に工程順に示す概略断面図である。なお、図１１Ａ〜図１１Ｄでは、第１及び第２の導電パッド及びその周辺のみを示す。[Modification 1]
FIG. 11A to FIG. 11D are schematic cross-sectional views showing the structure of the planar type FeRAM according to the first modification of the first embodiment along with its manufacturing method (only main steps) in the order of steps. 11A to 11D show only the first and second conductive pads and the periphery thereof.

先ず、第１の実施形態と同様に、図１Ａ〜図１Ｄ，図２Ａ〜図２Ｄ，図３Ａ，図３Ｂ及び図４〜図６の各工程を経て、第３の配線６３（耐湿リング６３を含む）及び第１の導電パッド６０を覆う下層絶縁膜６４及び上層絶縁膜６５を積層形成する。   First, similarly to the first embodiment, the third wiring 63 (the moisture-resistant ring 63 is formed) through the steps of FIGS. 1A to 1D, 2A to 2D, 3A, 3B and 4 to 6. And a lower insulating film 64 and an upper insulating film 65 that cover the first conductive pad 60 are stacked.

続いて、図１１Ａに示すように、パシベーション膜６６上に緩衝防止膜７１を塗布形成する。
詳細には、例えば感光性ポリイミドを膜厚３μｍ程度に塗布し、上層絶縁膜６５上を覆うように緩衝防止膜７１を形成する。このとき、パシベーション膜６６（下層絶縁膜６４及び上層絶縁膜６５）、及び緩衝防止膜７１が順次積層されてなる３層構造の保護絶縁膜が形成される。ここで、非感光性ポリイミドを用いる場合には、非感光性ポリイミド上にレジストパターンを形成し、専用現像液で非感光性ポリイミドを溶解する。その後、例えば横型炉で緩衝防止膜７１に例えば３１０℃でＮ２ガスを１００リットル／分の流量で４０分間の熱処理を施し、ポリイミドを硬化させる。なお、緩衝防止膜７１の材料として、ポリイミドの代わりに例えばノボラック樹脂を用いても良い。Subsequently, as shown in FIG. 11A, a buffer preventing film 71 is applied and formed on the passivation film 66.
Specifically, for example, photosensitive polyimide is applied to a film thickness of about 3 μm, and the buffer preventing film 71 is formed so as to cover the upper insulating film 65. At this time, a protective insulating film having a three-layer structure in which the passivation film 66 (the lower insulating film 64 and the upper insulating film 65) and the buffer preventing film 71 are sequentially stacked is formed. Here, when non-photosensitive polyimide is used, a resist pattern is formed on the non-photosensitive polyimide, and the non-photosensitive polyimide is dissolved with a dedicated developer. Thereafter, for example, in a horizontal furnace, the buffer film 71 is heat-treated at 310 ° C. at a flow rate of N 2 gas of 100 liters / minute for 40 minutes to cure the polyimide. For example, a novolac resin may be used as the material of the buffer preventing film 71 instead of polyimide.

続いて、図１１Ｂに示すように、緩衝防止膜７１及びパシベーション膜６６に開口７２を形成する。
詳細には、リソグラフィー及びドライエッチングにより緩衝防止膜７１及びパシベーション膜６６を加工し、第１の導電パッド６０の表面の一部を露出させる開口７２を形成する。Subsequently, as shown in FIG. 11B, an opening 72 is formed in the buffering prevention film 71 and the passivation film 66.
Specifically, the buffer film 71 and the passivation film 66 are processed by lithography and dry etching to form an opening 72 that exposes a part of the surface of the first conductive pad 60.

続いて、図１１Ｃに示すように、不図示の検査機器を用い、当該検査機器の探針（プローブ）５８を開口７２から露出する第１の導電パッド６０に当接（針当て）させて、各種の試験を行う。検査内容としては、装置の動作が正常に行われるか否かを調べる試験（ＰＴ１）、データの書き込み及び読み出しの良否を判定するリテンション試験（ＰＴ２，ＰＴ３）、最終的な確認試験（ＰＴ４）を順次行う。   Subsequently, as shown in FIG. 11C, using an inspection device (not shown), the probe (probe) 58 of the inspection device is brought into contact (needle contact) with the first conductive pad 60 exposed from the opening 72, Perform various tests. As inspection contents, a test (PT1) for checking whether the operation of the apparatus is normally performed, a retention test (PT2, PT3) for determining whether data is written and read, and a final confirmation test (PT4). Do it sequentially.

ＦｅＲＡＭの場合、上記のＰＴ１〜ＰＴ４の各試験が必要であり、各試験時におけるプローブによる第１の導電パッド６０の表面への複数回の当接により、第１の導電パッド６０に亀裂５９等が発生することが多い。   In the case of FeRAM, each of the above-described PT1 to PT4 is required, and the first conductive pad 60 is cracked 59 or the like by a plurality of contact with the surface of the first conductive pad 60 by the probe during each test. Often occurs.

続いて、図１１Ｄに示すように、第１の導電パッド６０と直接的に接続される第２の導電パッド７３を形成する。
詳細には、開口７２の内壁面を覆うように、例えばＰＶＤ法により、緩衝防止膜７１上にＡｌ合金膜（ここではＡｌ−Ｃｕ膜：膜厚５００ｎｍ程度）及びＴｉＮ膜（膜厚１５０ｎｍ程度）を積層する。そして、これらＴｉＮ膜及びＡｌ合金膜をリソグラフィー及びそれに続くドライエッチングによりパターニングする。この場合、平面視で第１の導電パッド６０よりも若干サイズが小さくなる程度に、第１の導電パッド６０と同様の略矩形状となるように、当該パターニングを実行する。これにより、緩衝防止膜７１及びパシベーション膜６６の開口７２の内壁底面（即ち第１の導電パッド６０の表面）及び内壁側面から緩衝防止膜７１上にかけて覆い、平面視で第１の導電パッド６０の形成領域に包含される第２の導電パッド７３が形成される。この第２の導電パッド７３は、ボンディングワイヤ等が接続される外部接続用パッドである。Subsequently, as shown in FIG. 11D, a second conductive pad 73 that is directly connected to the first conductive pad 60 is formed.
Specifically, an Al alloy film (here, Al—Cu film: about 500 nm thick) and a TiN film (about 150 nm thick) are formed on the buffer prevention film 71 by, for example, PVD so as to cover the inner wall surface of the opening 72. Are stacked. Then, these TiN film and Al alloy film are patterned by lithography and subsequent dry etching. In this case, the patterning is performed so as to have a substantially rectangular shape similar to that of the first conductive pad 60 so that the size is slightly smaller than that of the first conductive pad 60 in plan view. Thereby, the buffer film 71 covers the buffer film 71 from the inner wall bottom surface (that is, the surface of the first conductive pad 60) and the inner wall side surface of the opening 72 of the buffer film 71 and the passivation film 66, and covers the buffer film 71 in plan view. A second conductive pad 73 included in the formation region is formed. The second conductive pad 73 is an external connection pad to which a bonding wire or the like is connected.

しかる後、諸々の後工程を実行する。例えば、シリコン半導体基板１０の背面研磨、基板のダイシング、ワイヤ・ボンディング等による、開口７２から露出する第２の導電パッド７３の表面への外部接続、パッケージ化、及びパッケージ最終検査等を経て、本例によるＦｅＲＡＭを完成させる。   Thereafter, various post processes are executed. For example, the external connection to the surface of the second conductive pad 73 exposed from the opening 72, packaging, and final inspection of the package by polishing the back surface of the silicon semiconductor substrate 10, dicing the substrate, wire bonding, etc. An example FeRAM is completed.

本例では、第１の導電パッド６０の表面に針当てして各種試験を行う検査工程の後に、当該検査により亀裂５９等が生じた第１の導電パッド６０の表面を覆う第２の導電パッド７３を形成する。この第２の導電パッド７３は、第１の導電パッド６０に整合した位置で当該第１の導電パッド６０に包含されるサイズに形成される。即ち、第２の導電パッド７３は、第１の導電パッド６０と同様に、強誘電体キャパシタ構造３０と可及的に離間しており、第２の導電パッド７３の下方には強誘電体キャパシタ構造３０が存しないため、第２の導電パッド７３に外部との接続時に圧力が印加されても強誘電体キャパシタ構造３０に悪影響を与えることはない。   In this example, the second conductive pad covering the surface of the first conductive pad 60 in which a crack 59 or the like is generated by the inspection after an inspection process in which various tests are performed by applying a needle to the surface of the first conductive pad 60. 73 is formed. The second conductive pad 73 is formed in a size included in the first conductive pad 60 at a position aligned with the first conductive pad 60. That is, the second conductive pad 73 is separated from the ferroelectric capacitor structure 30 as much as possible, like the first conductive pad 60, and the ferroelectric capacitor is located below the second conductive pad 73. Since the structure 30 does not exist, even if a pressure is applied to the second conductive pad 73 when connected to the outside, the ferroelectric capacitor structure 30 is not adversely affected.

更に、第２の導電パッド７３は、緩衝防止膜７１及びパシベーション膜６６の開口７２の内壁底面及び内壁側面から緩衝防止膜７１上にかけて覆うように形成される。パシベーション膜６６の開口の内壁側面が最も顕著な水分・水素の浸入経路となることから、開口７２の内壁底面（即ち第１の導電パッド６０の表面）及び内壁側面から緩衝防止膜７１上にかけて覆うように第２の導電パッド７３を形成することにより、例えば上記の後工程におけるダイシング及びパッケージ化の際にも、当該浸入経路が可及的に閉ざされている。従って、強誘電体膜２５への水分・水素の浸入が可及的に抑止され、強誘電体膜２５の高い強誘電特性が十分に保持される。   Further, the second conductive pad 73 is formed so as to cover from the inner wall bottom surface and inner wall side surface of the opening 72 of the buffer preventing film 71 and the passivation film 66 to the buffer preventing film 71. Since the inner wall side surface of the opening of the passivation film 66 becomes the most remarkable moisture / hydrogen intrusion path, it covers the inner wall bottom surface of the opening 72 (that is, the surface of the first conductive pad 60) and the inner wall side surface over the buffering prevention film 71. By forming the second conductive pad 73 as described above, the intrusion path is closed as much as possible, for example, in the dicing and packaging in the post-process described above. Therefore, the penetration of moisture and hydrogen into the ferroelectric film 25 is suppressed as much as possible, and the high ferroelectric characteristics of the ferroelectric film 25 are sufficiently maintained.

以上説明したように、本実施形態によれば、比較的簡易な構成で十分な水・水素の内部侵入を確実に防止し、強誘電体膜２５を有する強誘電体キャパシタ構造３０の高性能を保持する信頼性の高いＦｅＲＡＭを実現することができる。   As described above, according to the present embodiment, sufficient internal penetration of water and hydrogen can be reliably prevented with a relatively simple configuration, and the high performance of the ferroelectric capacitor structure 30 having the ferroelectric film 25 can be improved. A highly reliable FeRAM can be realized.

［変形例２］
図１２Ａ〜図１２Ｃは、第１の実施形態の変形例２によるプレーナ型のＦｅＲＡＭの構成をその製造方法（主要工程のみ）と共に工程順に示す概略断面図である。なお、図１２Ａ〜図１２Ｃでは、第１及び第２の導電パッド及びその周辺のみを示す。[Modification 2]
12A to 12C are schematic cross-sectional views showing the structure of the planar type FeRAM according to the second modification of the first embodiment together with its manufacturing method (only main steps) in the order of steps. 12A to 12C show only the first and second conductive pads and the periphery thereof.

先ず、第１の実施形態と同様に、図１Ａ〜図１Ｄ，図２Ａ〜図２Ｄ，図３Ａ，図３Ｂ及び図４〜図９の各工程を経て、第１の導電パッド６０と直接的に接続される第２の導電パッド７０を形成する。なお本例では、パシベーション膜６６を第１のパシベーション膜６６と称する。   First, similarly to the first embodiment, the first conductive pad 60 and the first conductive pad 60 are directly passed through the steps of FIGS. 1A to 1D, 2A to 2D, 3A, 3B, and 4 to 9. A second conductive pad 70 to be connected is formed. In this example, the passivation film 66 is referred to as a first passivation film 66.

続いて、図１２Ａに示すように、第２の導電パッド７０を覆うように第１のパシベーション膜６６上に第２のパシベーション膜７６を形成する。
詳細には、先ず、第２の導電パッド７０を覆うように第１のパシベーション膜６６上に、ＣＶＤ法等によりプラズマＴＥＯＳ−ＮＳＧ膜を膜厚１００ｎｍ程度に堆積し、下層絶縁膜７４を形成する。そして、下層絶縁膜７４の表面の窒化を目的として、例えばＮ２Ｏのプラズマアニール処理（例えば３５０℃で２分間）を施す。Subsequently, as shown in FIG. 12A, a second passivation film 76 is formed on the first passivation film 66 so as to cover the second conductive pad 70.
More specifically, first, a plasma TEOS-NSG film is deposited to a thickness of about 100 nm on the first passivation film 66 so as to cover the second conductive pad 70 by a CVD method or the like, thereby forming a lower insulating film 74. . Then, for example, N 2 O plasma annealing (for example, at 350 ° C. for 2 minutes) is performed for the purpose of nitriding the surface of the lower insulating film 74.

次に、下層絶縁膜７４上に、ＣＶＤ法等によりプラズマＳｉＮ膜を膜厚３５０ｎｍ程度に堆積し、上層絶縁膜７５を形成する。このとき、下層絶縁膜７４上に上層絶縁膜７５が積層されてなる２層構造の第２のパシベーション膜７６が形成される。   Next, a plasma SiN film is deposited on the lower insulating film 74 by a CVD method or the like to a thickness of about 350 nm to form an upper insulating film 75. At this time, a second passivation film 76 having a two-layer structure in which an upper insulating film 75 is laminated on the lower insulating film 74 is formed.

続いて、図１２Ｂに示すように、第２のパシベーション膜７６に開口７６ａを形成する。
詳細には、リソグラフィー及びドライエッチングにより第２のパシベーション膜７６を加工し、第２の導電パッド７０の表面の一部を露出させる開口７６ａを形成する。Subsequently, as shown in FIG. 12B, an opening 76 a is formed in the second passivation film 76.
Specifically, the second passivation film 76 is processed by lithography and dry etching to form an opening 76 a that exposes a part of the surface of the second conductive pad 70.

続いて、図１２Ｃに示すように、緩衝防止膜７１を形成する。   Subsequently, as shown in FIG. 12C, a buffer preventing film 71 is formed.

詳細には、例えば感光性ポリイミドを膜厚３μｍ程度に塗布し、第２のパシベーション膜７６上を覆って保護し、第２の導電パッド７０の表面の一部のみを露出させる開口７１ａを有する緩衝防止膜７１を形成する。ここで、非感光性ポリイミドを用いる場合には、非感光性ポリイミド上にレジストパターンを形成し、専用現像液で非感光性ポリイミドを溶解する。その後、例えば横型炉で緩衝防止膜７１に例えば３１０℃でＮ２ガスを１００リットル／分の流量で４０分間の熱処理を施し、ポリイミドを硬化させる。なお、緩衝防止膜７１の材料として、ポリイミドの代わりに例えばノボラック樹脂を用いても良い。Specifically, for example, a photosensitive polyimide is applied to a film thickness of about 3 μm, covers and protects the second passivation film 76, and has a buffer having an opening 71 a that exposes only a part of the surface of the second conductive pad 70. A prevention film 71 is formed. Here, when non-photosensitive polyimide is used, a resist pattern is formed on the non-photosensitive polyimide, and the non-photosensitive polyimide is dissolved with a dedicated developer. Thereafter, for example, in a horizontal furnace, the buffer film 71 is heat-treated at 310 ° C. at a flow rate of N 2 gas of 100 liters / minute for 40 minutes to cure the polyimide. For example, a novolac resin may be used as the material of the buffer preventing film 71 instead of polyimide.

しかる後、諸々の後工程を実行する。例えば、シリコン半導体基板１０の背面研磨、基板のダイシング、ワイヤ・ボンディング等による、開口７２から露出する第２の導電パッド７０の表面への外部接続、パッケージ化、及びパッケージ最終検査等を経て、本例によるＦｅＲＡＭを完成させる。   Thereafter, various post processes are executed. For example, the external connection to the surface of the second conductive pad 70 exposed from the opening 72 by packaging the back surface of the silicon semiconductor substrate 10, substrate dicing, wire bonding, etc., packaging, final inspection of the package, etc. An example FeRAM is completed.

本例では、第１の導電パッド６０の表面に針当てして各種試験を行う検査工程の後に、当該検査により亀裂５９等が生じた第１の導電パッド６０の表面を覆う第２の導電パッド７０を形成する。この第２の導電パッド７３は、第１の導電パッド６０に整合した位置で当該第１の導電パッド６０に包含されるサイズに形成される。即ち、第２の導電パッド７０は、第１の導電パッド６０と同様に、強誘電体キャパシタ構造３０と可及的に離間しており、第２の導電パッド７０の下方には強誘電体キャパシタ構造３０が存しないため、第２の導電パッド７０に外部との接続時に圧力が印加されても強誘電体キャパシタ構造３０に悪影響を与えることはない。   In this example, the second conductive pad covering the surface of the first conductive pad 60 in which a crack 59 or the like is generated by the inspection after an inspection process in which various tests are performed by applying a needle to the surface of the first conductive pad 60. 70 is formed. The second conductive pad 73 is formed in a size included in the first conductive pad 60 at a position aligned with the first conductive pad 60. That is, the second conductive pad 70 is separated from the ferroelectric capacitor structure 30 as much as possible, like the first conductive pad 60, and the ferroelectric capacitor is located below the second conductive pad 70. Since the structure 30 does not exist, even if a pressure is applied to the second conductive pad 70 when connected to the outside, the ferroelectric capacitor structure 30 is not adversely affected.

更に、第２の導電パッド７０は、第１のパシベーション膜６６の開口６６ａの内壁底面及び内壁側面から第１のパシベーション膜６６上にかけて覆うように形成される。第１のパシベーション膜６６の開口の内壁側面が最も顕著な水分・水素の浸入経路となることから、開口６６ａの内壁底面（即ち第１の導電パッド６０の表面）及び内壁側面から第１のパシベーション膜６６上にかけて覆うように第２の導電パッド７０を形成することにより、例えば上記の後工程におけるダイシング及びパッケージ化の際にも、当該浸入経路が可及的に閉ざされている。更に本例では、第２の導電パッド７０を形成した後に再度パシベーション膜として第２のパシベーション膜７６を形成することにより、更に確実に当該浸入経路が閉ざされる。従って、強誘電体膜２５への水分・水素の浸入が可及的に抑止され、強誘電体膜２５の高い強誘電特性が十分に保持される。   Further, the second conductive pad 70 is formed so as to cover the inner wall bottom surface and the inner wall side surface of the opening 66 a of the first passivation film 66 over the first passivation film 66. Since the inner wall side surface of the opening of the first passivation film 66 becomes the most remarkable moisture / hydrogen infiltration path, the first passivation is performed from the inner wall bottom surface of the opening 66a (that is, the surface of the first conductive pad 60) and the inner wall side surface. By forming the second conductive pad 70 so as to cover the film 66, the intrusion path is closed as much as possible, for example, in the dicing and packaging in the post-process described above. Furthermore, in this example, after the second conductive pad 70 is formed, the second passivation film 76 is formed again as a passivation film, so that the entry path is more reliably closed. Therefore, the penetration of moisture and hydrogen into the ferroelectric film 25 is suppressed as much as possible, and the high ferroelectric characteristics of the ferroelectric film 25 are sufficiently maintained.

以上説明したように、本実施形態によれば、比較的簡易な構成で十分な水・水素の内部侵入を確実に防止し、強誘電体膜２５を有する強誘電体キャパシタ構造３０の高性能を保持する信頼性の高いＦｅＲＡＭを実現することができる。   As described above, according to the present embodiment, sufficient internal penetration of water and hydrogen can be reliably prevented with a relatively simple configuration, and the high performance of the ferroelectric capacitor structure 30 having the ferroelectric film 25 can be improved. A highly reliable FeRAM can be realized.

［変形例３］
本例では、第１の実施形態の変形例２によるプレーナ型のＦｅＲＡＭの構成に加え、上層膜５４ａ以降に形成する上層の所定部位に、水素拡散防止膜を形成する。[Modification 3]
In this example, in addition to the structure of the planar type FeRAM according to the second modification of the first embodiment, a hydrogen diffusion prevention film is formed at a predetermined portion of the upper layer formed after the upper layer film 54a.

具体的には、図１３Ａに示すように、上層膜５４ａと下層絶縁膜６４との間（第１の導電パッド６０の端部上から上層膜５４ａ上を覆う部分）である第１の領域Ｒ１、下層絶縁膜６４と上層絶縁膜６５との間（下層絶縁膜６４上）である第２の領域Ｒ２、上層絶縁膜６５と下層絶縁膜７４との間（上層絶縁膜６５上）である第３の領域Ｒ３、下層絶縁膜７４と上層絶縁膜７５との間（下層絶縁膜７４上）である第４の領域Ｒ４、及び上層絶縁膜７５と緩衝防止膜７１との間（上層絶縁膜７５上）である第５の領域Ｒ５のうちから選ばれた少なくとも１つの領域に、アルミナ等の金属酸化物からなる水素拡散防止膜を形成する。   Specifically, as shown in FIG. 13A, the first region R1 between the upper layer film 54a and the lower layer insulating film 64 (the portion covering the upper layer film 54a from the end portion of the first conductive pad 60). The second region R2 between the lower insulating film 64 and the upper insulating film 65 (on the lower insulating film 64), and the second region R2 between the upper insulating film 65 and the lower insulating film 74 (on the upper insulating film 65). The third region R3, the fourth region R4 between the lower insulating film 74 and the upper insulating film 75 (on the lower insulating film 74), and the upper insulating film 75 between the upper insulating film 75 and the buffer preventing film 71 (upper insulating film 75). A hydrogen diffusion prevention film made of a metal oxide such as alumina is formed in at least one region selected from the fifth region R5.

ここで、水素拡散防止膜を所望の膜厚に形成し、エッチングストッパー等で削られることなく最も水素拡散防止機能を発揮できる領域はＲ２とＲ４であると考えられる。本例では、図１３Ｂに示すように、領域Ｒ２，Ｒ４にそれぞれ水素拡散防止膜７７，７８を形成する。水素拡散防止膜７７，７８は、膜厚１０ｎｍ以上で水素拡散防止機能を発揮するが、あまり厚く形成すると、エッチングが困難となる。そこで好ましくは、４０ｎｍ〜６０ｎｍ程度に形成する。   Here, it is considered that R2 and R4 are regions where the hydrogen diffusion preventing film is formed in a desired film thickness and the hydrogen diffusion preventing function can be most exerted without being cut by an etching stopper or the like. In this example, as shown in FIG. 13B, hydrogen diffusion preventing films 77 and 78 are formed in the regions R2 and R4, respectively. The hydrogen diffusion preventing films 77 and 78 exhibit a hydrogen diffusion preventing function when the film thickness is 10 nm or more. However, if the film is formed too thick, etching becomes difficult. Therefore, it is preferably formed in a thickness of about 40 to 60 nm.

領域Ｒ２については、図５において、上層膜５４ａ上に膜厚５０ｎｍ程度にアルミナ膜を成膜して、水素拡散防止膜７７を形成する。
そして、水素拡散防止膜７７、上層膜５４ａ、及び層間絶縁膜５４に開口したビア孔５５ａを充填するプラグ５５を形成し、第１の導電プラグ６０、第１のパシベーション膜６６を順次形成する。For the region R2, in FIG. 5, an alumina film is formed on the upper layer film 54a to a thickness of about 50 nm to form a hydrogen diffusion preventing film 77.
Then, the hydrogen diffusion preventing film 77, the upper layer film 54a, and the plug 55 filling the via hole 55a opened in the interlayer insulating film 54 are formed, and the first conductive plug 60 and the first passivation film 66 are sequentially formed.

領域Ｒ４については、第２の導電パッド７０を覆うように第１のパシベーション膜６６上に下層絶縁膜７４を形成した後、下層絶縁膜７４上に膜厚５０ｎｍ程度にアルミナ膜を成膜して、水素拡散防止膜７８を形成する。
そして、水素拡散防止膜７８上に上層絶縁膜７５を形成した後、上層絶縁膜７５、水素拡散防止膜７８、及び下層絶縁膜７４に開口７６ａを形成した後、開口７１ａを有する緩衝防止膜７１を形成する。In the region R4, a lower insulating film 74 is formed on the first passivation film 66 so as to cover the second conductive pad 70, and then an alumina film is formed on the lower insulating film 74 to a thickness of about 50 nm. Then, a hydrogen diffusion prevention film 78 is formed.
Then, after forming the upper insulating film 75 on the hydrogen diffusion preventing film 78, after forming the opening 76a in the upper insulating film 75, the hydrogen diffusion preventing film 78, and the lower insulating film 74, the buffer preventing film 71 having the opening 71a. Form.

本例では、第１の導電パッド６０の表面に針当てして各種試験を行う検査工程の後に、当該検査により亀裂５９等が生じた第１の導電パッド６０の表面を覆う第２の導電パッド７０を形成する。この第２の導電パッド７３は、第１の導電パッド６０に整合した位置で当該第１の導電パッド６０に包含されるサイズに形成される。即ち、第２の導電パッド７０は、第１の導電パッド６０と同様に、強誘電体キャパシタ構造３０と可及的に離間しており、第２の導電パッド７０の下方には強誘電体キャパシタ構造３０が存しないため、第２の導電パッド７０に外部との接続時に圧力が印加されても強誘電体キャパシタ構造３０に悪影響を与えることはない。   In this example, the second conductive pad covering the surface of the first conductive pad 60 in which a crack 59 or the like is generated by the inspection after an inspection process in which various tests are performed by applying a needle to the surface of the first conductive pad 60. 70 is formed. The second conductive pad 73 is formed in a size included in the first conductive pad 60 at a position aligned with the first conductive pad 60. That is, the second conductive pad 70 is separated from the ferroelectric capacitor structure 30 as much as possible, like the first conductive pad 60, and the ferroelectric capacitor is located below the second conductive pad 70. Since the structure 30 does not exist, even if a pressure is applied to the second conductive pad 70 when connected to the outside, the ferroelectric capacitor structure 30 is not adversely affected.

更に、第２の導電パッド７０は、第１のパシベーション膜６６の開口６６ａの内壁底面及び内壁側面から第１のパシベーション膜６６上にかけて覆うように形成される。第１のパシベーション膜６６の開口の内壁側面が最も顕著な水分・水素の浸入経路となることから、開口６６ａの内壁底面（即ち第１の導電パッド６０の表面）及び内壁側面から第１のパシベーション膜６６上にかけて覆うように第２の導電パッド７０を形成することにより、例えば上記の後工程におけるダイシング及びパッケージ化の際にも、当該浸入経路が可及的に閉ざされている。更に本例では、第２の導電パッド７０を形成した後に再度パシベーション膜として第２のパシベーション膜７６を形成することにより、更に確実に当該浸入経路が閉ざされる。   Further, the second conductive pad 70 is formed so as to cover the inner wall bottom surface and the inner wall side surface of the opening 66 a of the first passivation film 66 over the first passivation film 66. Since the inner wall side surface of the opening of the first passivation film 66 becomes the most remarkable moisture / hydrogen infiltration path, the first passivation is performed from the inner wall bottom surface of the opening 66a (that is, the surface of the first conductive pad 60) and the inner wall side surface. By forming the second conductive pad 70 so as to cover the film 66, the intrusion path is closed as much as possible, for example, in the dicing and packaging in the post-process described above. Furthermore, in this example, after the second conductive pad 70 is formed, the second passivation film 76 is formed again as a passivation film, so that the entry path is more reliably closed.

更に本例では、領域Ｒ２及びＲ４に水素拡散防止膜７７，７８が設けられており、水分・水素の内部浸入がより確実に抑止される。
従って、強誘電体膜２５への水分・水素の浸入が可及的に抑止され、強誘電体膜２５の高い強誘電特性が十分に保持される。Further, in this example, the hydrogen diffusion preventing films 77 and 78 are provided in the regions R2 and R4, so that the intrusion of moisture and hydrogen is more reliably suppressed.
Therefore, the penetration of moisture and hydrogen into the ferroelectric film 25 is suppressed as much as possible, and the high ferroelectric characteristics of the ferroelectric film 25 are sufficiently maintained.

以上説明したように、本実施形態によれば、比較的簡易な構成で十分な水・水素の内部侵入を確実に防止し、強誘電体膜２５を有する強誘電体キャパシタ構造３０の高性能を保持する信頼性の高いＦｅＲＡＭを実現することができる。   As described above, according to the present embodiment, sufficient internal penetration of water and hydrogen can be reliably prevented with a relatively simple configuration, and the high performance of the ferroelectric capacitor structure 30 having the ferroelectric film 25 can be improved. A highly reliable FeRAM can be realized.

（第２の実施形態）
本実施形態では、強誘電体キャパシタ構造の下部電極下及び上部電極上にそれぞれ導電プラグが形成されて導通がとられる構成の、いわゆるスタック型のＦｅＲＡＭを例示する。
図１４Ａ〜図２４は、第２の実施形態によるスタック型のＦｅＲＡＭの構成をその製造方法と共に工程順に示す概略断面図である。(Second Embodiment)
In the present embodiment, a so-called stack type FeRAM having a configuration in which conductive plugs are respectively formed below and on a lower electrode of a ferroelectric capacitor structure to establish conduction is illustrated.
FIG. 14A to FIG. 24 are schematic cross-sectional views showing the configuration of the stack type FeRAM according to the second embodiment in the order of steps together with the manufacturing method thereof.

先ず、図１４Ａに示すように、シリコン半導体基板１１０上に選択トランジスタとして機能するＭＯＳトランジスタ１２０を形成する。
詳細には、シリコン半導体基板１１０の表層に例えばＳＴＩ（Shallow Trench
Isolation）法により素子分離構造１１１を形成し、素子活性領域を確定する。
次に、素子活性領域に不純物、ここではホウ素（Ｂ）を例えばドーズ量３．０×１０１３／ｃｍ２、加速エネルギー３００ｋｅＶの条件でイオン注入し、ウェル１１２を形成する。First, as shown in FIG. 14A, a MOS transistor 120 that functions as a selection transistor is formed on a silicon semiconductor substrate 110.
Specifically, for example, on the surface layer of the silicon semiconductor substrate 110, for example, STI (Shallow Trench).
An element isolation structure 111 is formed by an isolation method, and an element active region is determined.
Next, an impurity, here boron (B), is ion-implanted into the element active region, for example, under the conditions of a dose of 3.0 × 10 13 / cm 2 and an acceleration energy of 300 keV to form the well 112.

次に、素子活性領域に熱酸化等により膜厚３．０ｎｍ程度の薄いゲート絶縁膜１１３を形成し、ゲート絶縁膜１１３上にＣＶＤ法により膜厚１８０ｎｍ程度の多結晶シリコン膜及び膜厚２９ｎｍ程度の例えばシリコン窒化膜を堆積し、シリコン窒化膜、多結晶シリコン膜、及びゲート絶縁膜１１３をリソグラフィー及びそれに続くドライエッチングにより電極形状に加工することにより、ゲート絶縁膜１１３上にゲート電極１１４をパターン形成する。このとき同時に、ゲート電極１１４上にはシリコン窒化膜からなるキャップ膜１１５がパターン形成される。   Next, a thin gate insulating film 113 having a thickness of about 3.0 nm is formed in the element active region by thermal oxidation or the like, and a polycrystalline silicon film having a thickness of about 180 nm and a thickness of about 29 nm are formed on the gate insulating film 113 by a CVD method. For example, a silicon nitride film is deposited, and the gate electrode 114 is patterned on the gate insulating film 113 by processing the silicon nitride film, the polycrystalline silicon film, and the gate insulating film 113 into an electrode shape by lithography and subsequent dry etching. Form. At the same time, a cap film 115 made of a silicon nitride film is patterned on the gate electrode 114.

次に、キャップ膜１１５をマスクとして素子活性領域に不純物、ここでは砒素（Ａｓ）を例えばドーズ量５．０×１０１４／ｃｍ２、加速エネルギー１０ｋｅＶの条件でイオン注入し、いわゆるＬＤＤ領域１１６を形成する。Next, using the cap film 115 as a mask, an impurity, for example, arsenic (As) here is ion-implanted into the element active region under the conditions of a dose amount of 5.0 × 10 14 / cm 2 and an acceleration energy of 10 keV to form a so-called LDD region 116. Form.

次に、全面に例えばシリコン酸化膜をＣＶＤ法により堆積し、このシリコン酸化膜をいわゆるエッチバックすることにより、ゲート電極１１４及びキャップ膜１１５の側面のみにシリコン酸化膜を残してサイドウォール絶縁膜１１７を形成する。   Next, for example, a silicon oxide film is deposited on the entire surface by a CVD method, and this silicon oxide film is so-called etched back to leave the silicon oxide film only on the side surfaces of the gate electrode 114 and the cap film 115, and the sidewall insulating film 117. Form.

次に、キャップ膜１１５及びサイドウォール絶縁膜１１７をマスクとして素子活性領域に不純物、ここではリン（Ｐ）をＬＤＤ領域１１６よりも不純物濃度が高くなる条件でイオン注入し、ＬＤＤ領域１１６と重畳されるソース／ドレイン領域１１８を形成して、ＭＯＳトランジスタ１２０を完成させる。   Next, using the cap film 115 and the sidewall insulating film 117 as a mask, an impurity, in this case, phosphorus (P) is ion-implanted into the element active region under a condition that the impurity concentration is higher than that of the LDD region 116 and overlapped with the LDD region 116. A source / drain region 118 is formed to complete the MOS transistor 120.

続いて、図１４Ｂに示すように、ＭＯＳトランジスタ１２０の保護膜１２１、層間絶縁膜１２２、及び上部絶縁膜１２３を順次形成する。
詳細には、ＭＯＳトランジスタ１２０を覆うように、保護膜１２１、層間絶縁膜１２２、及び上部絶縁膜１２３を順次形成する。ここで、保護膜１２１としては、シリコン酸化膜を材料とし、ＣＶＤ法により膜厚２０ｎｍ程度に堆積する。層間絶縁膜１２２としては、例えばプラズマＳｉＯ膜(膜厚２０ｎｍ程度)、プラズマＳｉＮ膜(膜厚８０ｎｍ程度)及びプラズマＴＥＯＳ膜(膜厚１０００ｎｍ程度)を順次成膜した積層構造を形成し、積層後、ＣＭＰにより膜厚が７００ｎｍ程度となるまで研磨する。上部絶縁膜１２３としては、シリコン窒化膜を材料とし、ＣＶＤ法により膜厚１００ｎｍ程度に堆積する。Subsequently, as shown in FIG. 14B, a protective film 121, an interlayer insulating film 122, and an upper insulating film 123 of the MOS transistor 120 are sequentially formed.
Specifically, a protective film 121, an interlayer insulating film 122, and an upper insulating film 123 are sequentially formed so as to cover the MOS transistor 120. Here, as the protective film 121, a silicon oxide film is used as a material, and is deposited to a thickness of about 20 nm by a CVD method. As the interlayer insulating film 122, for example, a stacked structure in which a plasma SiO film (film thickness of about 20 nm), a plasma SiN film (film thickness of about 80 nm) and a plasma TEOS film (film thickness of about 1000 nm) are sequentially formed is formed. Polishing is performed by CMP until the film thickness reaches about 700 nm. As the upper insulating film 123, a silicon nitride film is used as a material, and is deposited to a thickness of about 100 nm by a CVD method.

続いて、図１４Ｃに示すように、トランジスタ構造１２０のソース／ドレイン領域１１８と接続されるプラグ１１９を形成する。なお、図１４Ｃ以下の各図では、図示の便宜上、層間絶縁膜１２２から上部の構成のみを示し、シリコン半導体基板１１０やＭＯＳトランジスタ１２０等の図示を省略する。   Subsequently, as shown in FIG. 14C, a plug 119 connected to the source / drain region 118 of the transistor structure 120 is formed. 14C and subsequent figures, for convenience of illustration, only the structure above the interlayer insulating film 122 is shown, and illustration of the silicon semiconductor substrate 110, the MOS transistor 120, and the like is omitted.

詳細には、先ず、ソース／ドレイン領域１１８をエッチングストッパーとして、当該ソース／ドレイン領域１１８の表面の一部が露出するまで上部絶縁膜２２３、層間絶縁膜１２２、及び保護膜１２１をリソグラフィー及びそれに続くドライエッチングにより加工し、例えば約０．３μｍ径のビア孔１１９ａを形成する。   Specifically, first, using the source / drain region 118 as an etching stopper, lithography is performed on the upper insulating film 223, the interlayer insulating film 122, and the protective film 121 until a part of the surface of the source / drain region 118 is exposed. For example, a via hole 119a having a diameter of about 0.3 μm is formed by dry etching.

次に、ビア孔１１９ａの壁面を覆うように、スパッタ法により例えばＴｉ膜及びＴｉＮ膜を膜厚２０ｎｍ程度及びに膜厚５０ｎｍ程度に順次堆積して、下地膜（グルー膜）１１９ｂを形成する。そして、ＣＶＤ法によりグルー膜１１９ｂを介してビア孔１１９ａを埋め込むように例えばＷ膜を形成する。その後、ＣＭＰにより上部絶縁膜１２３をストッパーとしてＷ膜及びグルー膜１１９ｂを研磨し、ビア孔１１９ａ内をグルー膜１１９ａを介してＷで埋め込むプラグ１１９を形成する。ＣＭＰの後に、例えばＮ２Ｏのプラズマアニール処理を施す。Next, a base film (glue film) 119b is formed by sequentially depositing, for example, a Ti film and a TiN film to a film thickness of about 20 nm and a film thickness of about 50 nm so as to cover the wall surface of the via hole 119a. Then, for example, a W film is formed by the CVD method so as to fill the via hole 119a through the glue film 119b. Thereafter, the W film and the glue film 119b are polished by CMP using the upper insulating film 123 as a stopper, thereby forming a plug 119 filling the via hole 119a with W via the glue film 119a. After the CMP, for example, a plasma annealing treatment of N 2 O is performed.

続いて、図１４Ｄに示すように、下部電極層１２４、強誘電体膜１２５及び上部電極層１２６を順次形成する。
詳細には、先ず、スパッタ法により例えば膜厚が１５０ｎｍ〜２００ｎｍ程度にＰｔ膜を堆積し、下部電極層１２４を形成する。Subsequently, as shown in FIG. 14D, a lower electrode layer 124, a ferroelectric film 125, and an upper electrode layer 126 are sequentially formed.
Specifically, first, a Pt film is deposited to a thickness of, for example, about 150 nm to 200 nm by sputtering, and the lower electrode layer 124 is formed.

次に、ＲＦスパッタ法により、下部電極層１２４上に強誘電体である例えばＰＺＴからなる強誘電体膜２２５を膜厚１００ｎｍ〜３００ｎｍ程度に堆積する。そして、強誘電体膜１２５をアニール処理して当該強誘電体膜１２５を結晶化する。このアニール処理の条件としては、Ａｒ／Ｏ２ガスをＡｒが１．９８リットル／分、Ｏ２が０．０２５リットル／分の流量で供給しながら、例えば５５０℃〜６５０℃で６０秒間〜１２０秒間実行する。強誘電体膜１２５の材料としては、ＰＺＴの代わりに、Ｐｂ１−ｘＬａｘＺｒ１−ｙＴｉｙＯ３（０＜ｘ＜１，０＜ｙ＜１）、ＳｒＢｉ２（ＴａｘＮｂ１−ｘ）２Ｏ９（０＜ｘ＜１）、Ｂｉ４Ｔｉ２Ｏ１２等を用いても良い。Next, a ferroelectric film 225 made of a ferroelectric material such as PZT is deposited on the lower electrode layer 124 to a thickness of about 100 nm to 300 nm by RF sputtering. Then, the ferroelectric film 125 is annealed to crystallize the ferroelectric film 125. As conditions for the annealing treatment, Ar / O 2 gas is supplied at a flow rate of Ar of 1.98 liters / minute and O 2 of 0.025 liters / minute, for example, at 550 ° C. to 650 ° C. for 60 seconds to 120 seconds. Run for seconds. As the material of the ferroelectric film 125, instead of PZT, Pb 1-x La x Zr 1-y Ti y O 3 (0 <x <1,0 <y <1), SrBi 2 (Ta x Nb 1 -x) 2 O 9 (0 < x <1), may be used Bi 4 Ti 2 O 12 and the like.

次に、強誘電体膜１２５上に上部電極層１２６を堆積形成する。
上部電極層１２６としては、先ず反応性スパッタ法により、例えば導電性酸化物であるＩｒＯ２膜１２６ａを膜厚２００ｎｍ程度に形成する。その後、ＩｒＯ２膜１２６ａをアニール処理する。このアニール処理の条件としては、Ａｒ／Ｏ２ガスをＡｒが２．０リットル／分、Ｏ２が０．０２リットル／分の流量で供給しながら、例えば６５０℃〜８５０℃で１０秒間〜６０秒間実行する。そして、ＩｒＯ２膜１２６ａ上に、当該ＩｒＯ２膜１２６ａのキャップ膜として機能する貴金属膜、ここではＰｔ膜１２６ｂをスパッタ法により膜厚１００ｎｍ程度に形成する。ＩｒＯ２膜１２６ａ及びＰｔ膜１２６ｂから上部電極層１２６が構成される。なお、上部電極層１２６において、ＩｒＯ２膜１２６ａの代わりにＩｒ、Ｒｕ、ＲｕＯ２、ＳｒＲｕＯ３、その他の導電性酸化物やこれらの積層構造としても良い。また、Ｐｔ膜１２６ｂの形成を省略することも可能である。Next, an upper electrode layer 126 is deposited on the ferroelectric film 125.
As the upper electrode layer 126, first, for example, an IrO 2 film 126a, which is a conductive oxide, is formed to a thickness of about 200 nm by reactive sputtering. Thereafter, the IrO 2 film 126a is annealed. As conditions for this annealing treatment, Ar / O 2 gas is supplied at a flow rate of Ar of 2.0 liters / minute and O 2 of 0.02 liters / minute, for example, at 650 ° C. to 850 ° C. for 10 seconds to 60 seconds. Run for seconds. Then, on the IrO 2 film 126a, a noble metal film functioning as a cap film for the IrO 2 film 126a, here formed with a film thickness of approximately 100nm by sputtering Pt film 126b. The upper electrode layer 126 is composed of the IrO 2 film 126a and the Pt film 126b. In the upper electrode layer 126, Ir, Ru, RuO 2 , SrRuO 3 , other conductive oxides, or a stacked structure thereof may be used instead of the IrO 2 film 126a. In addition, the formation of the Pt film 126b can be omitted.

続いて、図１５Ａに示すように、ＴｉＮ膜１２８及びシリコン酸化膜１２９を形成する。
詳細には、ＴｉＮ膜１２８については、上部電極層１２６上にスパッタ法等により膜厚２００ｎｍ程度に堆積形成する。シリコン酸化膜１２９については、ＴｉＮ膜１２８上に、例えばＴＥＯＳを用いたＣＶＤ法により膜厚１０００ｎｍ程度に堆積形成する。ここで、ＴＥＯＳ膜の代わりにＨＤＰ膜を形成しても良い。なお、シリコン酸化膜１２９上に更にシリコン窒化膜を形成しても好適である。Subsequently, as shown in FIG. 15A, a TiN film 128 and a silicon oxide film 129 are formed.
Specifically, the TiN film 128 is deposited on the upper electrode layer 126 to a thickness of about 200 nm by sputtering or the like. The silicon oxide film 129 is deposited on the TiN film 128 to a thickness of about 1000 nm by, for example, a CVD method using TEOS. Here, an HDP film may be formed instead of the TEOS film. A silicon nitride film may be further formed on the silicon oxide film 129.

続いて、図１５Ｂに示すように、レジストマスク１０１を形成する。
詳細には、シリコン酸化膜１２９上にレジストを塗布し、このレジストをリソグラフィーにより電極形状に加工して、レジストマスク１０１を形成する。Subsequently, as shown in FIG. 15B, a resist mask 101 is formed.
Specifically, a resist is applied on the silicon oxide film 129, and this resist is processed into an electrode shape by lithography to form a resist mask 101.

続いて、図１５Ｃに示すように、シリコン酸化膜１２９を加工する。
詳細には、レジストマスク１０１をマスクとしてシリコン酸化膜１２９をドライエッチングする。このとき、レジストマスク１０１の電極形状に倣ってシリコン酸化膜１２９がパターニングされ、ハードマスク１２９ａが形成される。また、レジストマスク１０１のエッチングされて厚みが減少する。Subsequently, as shown in FIG. 15C, the silicon oxide film 129 is processed.
Specifically, the silicon oxide film 129 is dry etched using the resist mask 101 as a mask. At this time, the silicon oxide film 129 is patterned following the electrode shape of the resist mask 101 to form a hard mask 129a. Further, the resist mask 101 is etched to reduce the thickness.

続いて、図１５Ｄに示すように、ＴｉＮ膜１２８を加工する。
詳細には、レジストマスク１０１及びハードマスク１２９ａをマスクとして、ＴｉＮ膜１２８をドライエッチングする。このとき、ハードマスク１２９ａの電極形状に倣ってＴｉＮ膜１２８がパターニングされる。また、レジストマスク１０１は、当該エッチング中に自身がエッチングされて薄くなる。その後、灰化処理等によりレジストマスク１０１を除去する。Subsequently, as shown in FIG. 15D, the TiN film 128 is processed.
Specifically, the TiN film 128 is dry etched using the resist mask 101 and the hard mask 129a as a mask. At this time, the TiN film 128 is patterned following the electrode shape of the hard mask 129a. Further, the resist mask 101 is thinned by being etched during the etching. Thereafter, the resist mask 101 is removed by ashing or the like.

続いて、図１６Ａに示すように、上部電極層１２６、強誘電体膜１２５、及び下部電極層１２４を加工する。
詳細には、ハードマスク１２９ａ及びＴｉＮ膜１２８をマスクとし、上部絶縁膜１２３をエッチングストッパーとして、上部電極層１２６、強誘電体膜１２５、及び下部電極層１２４をドライエッチングする。このとき、ＴｉＮ膜１２８の電極形状に倣って、上部電極層１２６、強誘電体膜１２５、及び下部電極層１２４がパターニングされる。また、ハードマスク１２９ａは、当該エッチング中に自身がエッチングされて薄くなる。その後、ハードマスク１２９ａを全面ドライエッチング（エッチバック）によりエッチング除去する。Subsequently, as shown in FIG. 16A, the upper electrode layer 126, the ferroelectric film 125, and the lower electrode layer 124 are processed.
More specifically, the upper electrode layer 126, the ferroelectric film 125, and the lower electrode layer 124 are dry etched using the hard mask 129a and the TiN film 128 as a mask and the upper insulating film 123 as an etching stopper. At this time, the upper electrode layer 126, the ferroelectric film 125, and the lower electrode layer 124 are patterned following the electrode shape of the TiN film 128. Further, the hard mask 129a is thinned by being etched during the etching. Thereafter, the hard mask 129a is removed by dry etching (etchback) on the entire surface.

続いて、図１６Ｂに示すように、強誘電体キャパシタ構造１３０を完成させる。
詳細には、マスクとして用いられたＴｉＮ膜１２８をウェットエッチングにより除去する。このとき、下部電極１３１上に強誘電体膜１２５、上部電極１３２が順次積層され、強誘電体膜１２５を介して下部電極１３１と上部電極１３２とが容量結合する強誘電体キャパシタ構造１３０を完成させる。この強誘電体キャパシタ構造１３０においては、下部電極１３１がプラグ１１９と接続され、当該プラグ１１９を介してソース／ドレイン１１８と下部電極１３１とが電気的に接続される。Subsequently, as shown in FIG. 16B, the ferroelectric capacitor structure 130 is completed.
Specifically, the TiN film 128 used as a mask is removed by wet etching. At this time, the ferroelectric film 125 and the upper electrode 132 are sequentially stacked on the lower electrode 131, and the ferroelectric capacitor structure 130 in which the lower electrode 131 and the upper electrode 132 are capacitively coupled through the ferroelectric film 125 is completed. Let In the ferroelectric capacitor structure 130, the lower electrode 131 is connected to the plug 119, and the source / drain 118 and the lower electrode 131 are electrically connected via the plug 119.

続いて、図１６Ｃに示すように、強誘電体膜１２５への水素・水の浸入を防止するための水素拡散防止膜１３３及び層間絶縁膜１３４を形成する。
詳細には、先ず、強誘電体キャパシタ構造１３０の全面を覆うように、金属酸化物、例えばアルミナ（Ａｌ２Ｏ３）を材料として、スパッタ法により膜厚２０ｎｍ〜５０ｎｍ程度に堆積し、水素拡散防止膜１３３を形成する。その後、水素拡散防止膜１３３をアニール処理する。Subsequently, as shown in FIG. 16C, a hydrogen diffusion preventing film 133 and an interlayer insulating film 134 for preventing hydrogen / water from entering the ferroelectric film 125 are formed.
Specifically, first, a metal oxide, for example, alumina (Al 2 O 3 ) is used as a material so as to cover the entire surface of the ferroelectric capacitor structure 130, and is deposited to a thickness of about 20 nm to 50 nm by sputtering, and hydrogen diffusion is performed. A prevention film 133 is formed. Thereafter, the hydrogen diffusion preventing film 133 is annealed.

次に、強誘電体キャパシタ構造１３０を水素拡散防止膜１３３を介して覆うように、層間絶縁膜１３４を形成する。ここで、層間絶縁膜１３４としては、例えばＴＥＯＳを用いたプラズマＣＶＤ法により、シリコン酸化膜を膜厚１５００ｎｍ〜２５００ｎｍ程度に堆積した後、ＣＭＰにより例えば膜厚が１０００ｎｍ程度となるまで研磨して形成する。ＣＭＰの後に、層間絶縁膜１３４の脱水を目的として、例えばＮ２Ｏのプラズマアニール処理を施す。Next, an interlayer insulating film 134 is formed so as to cover the ferroelectric capacitor structure 130 with the hydrogen diffusion preventing film 133 interposed therebetween. Here, the interlayer insulating film 134 is formed by depositing a silicon oxide film to a film thickness of about 1500 nm to 2500 nm by a plasma CVD method using TEOS, for example, and then polishing the film to a film thickness of about 1000 nm by CMP. To do. After the CMP, for example, N 2 O plasma annealing is performed for the purpose of dehydrating the interlayer insulating film 134.

続いて、図１７Ａに示すように、強誘電体キャパシタ構造１３０の上部電極１３２へのビア孔１３５ａを形成する。
詳細には、リソグラフィー及びそれに続くドライエッチングにより層間絶縁膜１３４及び水素拡散防止膜１３３をパターニングし、上部電極１３２の表面の一部を露出させるビア孔１３５ａを形成する。Subsequently, as shown in FIG. 17A, a via hole 135a to the upper electrode 132 of the ferroelectric capacitor structure 130 is formed.
Specifically, the interlayer insulating film 134 and the hydrogen diffusion preventing film 133 are patterned by lithography and subsequent dry etching to form a via hole 135a exposing a part of the surface of the upper electrode 132.

続いて、図１７Ｂに示すように、強誘電体キャパシタ構造１３０の上部電極１３２と接続されるプラグ１３５を形成する。
詳細には、先ず、ビア孔１３５ａの壁面を覆うように、スパッタ法により例えばＴｉ膜及びＴｉＮ膜を膜厚２０ｎｍ程度及びに膜厚５０ｎｍ程度に順次堆積して、下地膜（グルー膜）１３５ｂを形成する。Subsequently, as shown in FIG. 17B, a plug 135 connected to the upper electrode 132 of the ferroelectric capacitor structure 130 is formed.
Specifically, first, for example, a Ti film and a TiN film are sequentially deposited to a thickness of about 20 nm and a thickness of about 50 nm by a sputtering method so as to cover the wall surface of the via hole 135a, and a base film (glue film) 135b is formed. Form.

次に、ＣＶＤ法によりグルー膜１３５ｂを介してビア孔１３５ａを埋め込むように例えばＷ膜を形成する。その後、ＣＭＰにより層間絶縁膜１３４をストッパーとしてＷ膜及びグルー膜１３５ｂを研磨し、ビア孔１３５ａ内をグルー膜１３５ａを介してＷで埋め込むプラグ１３５を形成する。ＣＭＰの後に、例えばＮ２Ｏのプラズマアニール処理を施す。Next, for example, a W film is formed by the CVD method so as to fill the via hole 135a through the glue film 135b. Thereafter, the W film and the glue film 135b are polished by CMP using the interlayer insulating film 134 as a stopper to form a plug 135 that fills the via hole 135a with W via the glue film 135a. After the CMP, for example, a plasma annealing treatment of N 2 O is performed.

続いて、図１７Ｃに示すように、プラグ１３５と接続される第１の配線１４５を形成する。
詳細には、先ず、層間絶縁膜１３４上の全面にスパッタ法等によりバリアメタル膜１４２、配線膜１４３及びバリアメタル膜１４４を堆積する。バリアメタル膜１４２としては、スパッタ法により例えばＴｉＮ膜を膜厚１５０ｎｍ程度に成膜する。配線膜１４３としては、例えばＡｌ合金膜（ここではＡｌ−Ｃｕ膜）を膜厚５５０ｎｍ程度に成膜する。バリアメタル膜１４４としては、スパッタ法により例えばＴｉ膜（膜厚５ｎｍ程度）及びＴｉＮ（膜厚１５０ｎｍ程度）を順次成膜する。ここで、配線膜１４３の構造は、同一ルールのＦｅＲＡＭ以外のロジック部と同じ構造とされているため、配線の加工や信頼性上の問題はない。Subsequently, as shown in FIG. 17C, a first wiring 145 connected to the plug 135 is formed.
Specifically, first, the barrier metal film 142, the wiring film 143, and the barrier metal film 144 are deposited on the entire surface of the interlayer insulating film 134 by sputtering or the like. As the barrier metal film 142, for example, a TiN film is formed to a thickness of about 150 nm by sputtering. As the wiring film 143, for example, an Al alloy film (here, an Al—Cu film) is formed to a film thickness of about 550 nm. As the barrier metal film 144, for example, a Ti film (film thickness of about 5 nm) and TiN (film thickness of about 150 nm) are sequentially formed by sputtering. Here, since the structure of the wiring film 143 is the same as that of the logic part other than the FeRAM having the same rule, there is no problem in processing or reliability of the wiring.

次に、反射防止膜として例えばＳｉＯＮ膜または反射防止膜（不図示）を成膜した後、リソグラフィー及びそれに続くドライエッチングにより反射防止膜、バリアメタル膜１４４、配線膜１４３及びバリアメタル膜１４２を配線形状に加工し、プラグ１３５と接続される第１の配線１４５をパターン形成する。ここで、第１の配線１４５と同一構造の耐湿リング１４５ａも第１の配線１４５と同時に形成するが、図示の都合上、図１８以降に示す。なお、配線膜１４３としてＡｌ合金膜を形成する代わりに、いわゆるダマシン法等を利用してＣｕ膜（又はＣｕ合金膜）を形成し、第１の配線１４５としてＣｕ配線を形成しても良い。   Next, after forming, for example, a SiON film or an antireflection film (not shown) as an antireflection film, the antireflection film, the barrier metal film 144, the wiring film 143, and the barrier metal film 142 are wired by lithography and subsequent dry etching. The first wiring 145 connected to the plug 135 is patterned by processing into a shape. Here, the moisture-resistant ring 145a having the same structure as that of the first wiring 145 is also formed at the same time as the first wiring 145. However, for the sake of illustration, FIG. Instead of forming an Al alloy film as the wiring film 143, a Cu film (or Cu alloy film) may be formed by using a so-called damascene method or the like, and a Cu wiring may be formed as the first wiring 145.

続いて、図１８に示すように、第１の配線１４５とプラグ１４７を介して接続される第２の配線１５３を形成する。
詳細には、先ず、第１の配線１４５（及び耐湿リング１４５ａ）を覆うように層間絶縁膜１４６及びその上層膜１４６ａを形成する。Subsequently, as shown in FIG. 18, a second wiring 153 connected to the first wiring 145 via the plug 147 is formed.
Specifically, first, an interlayer insulating film 146 and an upper layer film 146a are formed so as to cover the first wiring 145 (and the moisture-resistant ring 145a).

層間絶縁膜１４６としては、プラズマＴＥＯＳ−ＮＳＧ膜を膜厚２６００ｎｍ程度に堆積した後、その表層をＣＭＰ等により除去して表面を平坦化して形成する。そして、層間絶縁膜１４６の表面の窒化を目的として、例えばＮ２Ｏのプラズマアニール処理（例えば３５０℃で４分間）を施す。The interlayer insulating film 146 is formed by depositing a plasma TEOS-NSG film to a thickness of about 2600 nm and then removing the surface layer by CMP or the like to planarize the surface. Then, for example, N 2 O plasma annealing (for example, at 350 ° C. for 4 minutes) is performed for the purpose of nitriding the surface of the interlayer insulating film 146.

上層膜１４６ａとしては、プラズマＴＥＯＳ−ＮＳＧ膜を膜厚２６００ｎｍ程度に堆積して形成する。そして、上層膜１４６ａの表面の窒化を目的として、例えばＮ２Ｏのプラズマアニール処理（例えば３５０℃で２分間）を施す。As the upper layer film 146a, a plasma TEOS-NSG film is deposited to a thickness of about 2600 nm. Then, for the purpose of nitriding the surface of the upper layer film 146a, for example, N 2 O plasma annealing (for example, at 350 ° C. for 2 minutes) is performed.

次に、第１の配線１４５と接続されるプラグ１４７を形成する。
第１の配線１４５の表面の一部が露出するまで、上層膜１４６ａ及び層間絶縁膜１４６をリソグラフィー及びそれに続くドライエッチングにより加工して、例えば約０．２５μｍ径のビア孔１４７ａを形成する。次に、このビア孔１４７ａの壁面を覆うように下地膜（グルー膜）１４８を形成した後、ＣＶＤ法によりグルー膜１４８を介してビア孔１４７ａを埋め込むようにＷ膜を形成する。そして、上層膜１４６ａをストッパーとして例えばＷ膜及びグルー膜１４８を研磨し、ビア孔１４７ａ内をグルー膜１４８を介してＷで埋め込むプラグ１４７を形成する。Next, a plug 147 connected to the first wiring 145 is formed.
The upper layer film 146a and the interlayer insulating film 146 are processed by lithography and subsequent dry etching until a part of the surface of the first wiring 145 is exposed, thereby forming a via hole 147a having a diameter of about 0.25 μm, for example. Next, after forming a base film (glue film) 148 so as to cover the wall surface of the via hole 147a, a W film is formed by the CVD method so as to fill the via hole 147a via the glue film 148. Then, for example, the W film and the glue film 148 are polished using the upper layer film 146a as a stopper to form a plug 147 that fills the via hole 147a with W via the glue film 148.

次に、プラグ１４７とそれぞれ接続される第２の配線１５３を形成する。
先ず、全面にスパッタ法等により配線膜１５１及びバリアメタル膜１５２を堆積する。配線膜１５２としては、例えばＡｌ合金膜（ここではＡｌ−Ｃｕ膜）を膜厚５５０ｎｍ程度に成膜する。バリアメタル膜１５２としては、スパッタ法により例えばＴｉ膜（膜厚５ｎｍ程度）及びＴｉＮ（膜厚１５０ｎｍ程度）を順次成膜する。ここで、配線膜１５１の構造は、同一ルールのＦｅＲＡＭ以外のロジック部と同じ構造とされているため、配線の加工や信頼性上の問題はない。Next, second wirings 153 connected to the plugs 147 are formed.
First, a wiring film 151 and a barrier metal film 152 are deposited on the entire surface by sputtering or the like. As the wiring film 152, for example, an Al alloy film (here, an Al—Cu film) is formed to a thickness of about 550 nm. As the barrier metal film 152, for example, a Ti film (film thickness of about 5 nm) and TiN (film thickness of about 150 nm) are sequentially formed by sputtering. Here, since the structure of the wiring film 151 is the same as that of the logic part other than the FeRAM having the same rule, there is no problem in processing of the wiring and reliability.

次に、反射防止膜として例えばＳｉＯＮ膜または反射防止膜（不図示）を成膜した後、リソグラフィー及びそれに続くドライエッチングにより反射防止膜、バリアメタル膜１５３、配線膜１５２及びバリアメタル膜１５１を配線形状に加工し、第２の配線１５３をパターン形成する。このとき、第２の配線１５３と同一構造に、耐湿リング１４５ａとプラグ１４７を介して接続されてなる耐湿リング１５３ａを形成する。なお、配線膜１５２としてＡｌ合金膜を形成する代わりに、いわゆるダマシン法等を利用してＣｕ膜（又はＣｕ合金膜）を形成し、第２の配線１５３としてＣｕ配線を形成しても良い。   Next, after forming, for example, a SiON film or an antireflection film (not shown) as an antireflection film, the antireflection film, the barrier metal film 153, the wiring film 152, and the barrier metal film 151 are wired by lithography and subsequent dry etching. The second wiring 153 is patterned by processing into a shape. At this time, a moisture-resistant ring 153 a connected to the moisture-resistant ring 145 a and the plug 147 is formed in the same structure as the second wiring 153. Instead of forming an Al alloy film as the wiring film 152, a Cu film (or Cu alloy film) may be formed using a so-called damascene method or the like, and a Cu wiring may be formed as the second wiring 153.

続いて、図１９に示すように、第２の配線１５３とプラグ１５５により接続される第３の配線１６３及び第１の導電パッド１６０を形成する。
詳細には、先ず、配線１５３（及び耐湿リング１５３ａ）を覆うように層間絶縁膜１５４及びその上層膜１５４ａを形成する。Subsequently, as shown in FIG. 19, a third wiring 163 and a first conductive pad 160 connected to the second wiring 153 and the plug 155 are formed.
Specifically, first, an interlayer insulating film 154 and an upper layer film 154a are formed so as to cover the wiring 153 (and the moisture-resistant ring 153a).

層間絶縁膜１５４としては、プラズマＴＥＯＳ−ＮＳＧ膜を膜厚２２００ｎｍ程度に堆積した後、その表層をＣＭＰ等により除去して表面を平坦化して形成する。そして、層間絶縁膜１５４の表面の窒化を目的として、例えばＮ２Ｏのプラズマアニール処理（例えば３５０℃で４分間）を施す。The interlayer insulating film 154 is formed by depositing a plasma TEOS-NSG film to a thickness of about 2200 nm and then removing the surface layer by CMP or the like to planarize the surface. Then, for example, N 2 O plasma annealing (for example, at 350 ° C. for 4 minutes) is performed for the purpose of nitriding the surface of the interlayer insulating film 154.

上層膜１５４ａとしては、プラズマＴＥＯＳ−ＮＳＧ膜を膜厚２６００ｎｍ程度に堆積して形成する。そして、上層膜１５４ａの表面の窒化を目的として、例えばＮ２Ｏのプラズマアニール処理（例えば３５０℃で２分間）を施す。As the upper layer film 154a, a plasma TEOS-NSG film is deposited to a thickness of about 2600 nm. Then, for the purpose of nitriding the surface of the upper layer film 154a, for example, N 2 O plasma annealing (for example, at 350 ° C. for 2 minutes) is performed.

次に、第２の配線１５３と接続されるプラグ１５５を形成する。
第２の配線１５３の表面の一部が露出するまで、上層膜１５４ａ及び層間絶縁膜１５４をリソグラフィー及びそれに続くドライエッチングにより加工して、ビア孔１５５ａを形成する。次に、このビア孔１５５ａの壁面を覆うように下地膜（グルー膜）１５６を形成した後、ＣＶＤ法によりグルー膜１５６を介してビア孔１５５ａを埋め込むようにＷ膜を形成する。そして、上層膜１５４ａをストッパーとして例えばＷ膜及びグルー膜１５６を研磨し、ビア孔１５５ａ内をグルー膜１５６を介してＷで埋め込むプラグ１５５を形成する。Next, a plug 155 connected to the second wiring 153 is formed.
The upper layer film 154a and the interlayer insulating film 154 are processed by lithography and subsequent dry etching until a part of the surface of the second wiring 153 is exposed, thereby forming a via hole 155a. Next, after forming a base film (glue film) 156 so as to cover the wall surface of the via hole 155a, a W film is formed by the CVD method so as to fill the via hole 155a via the glue film 156. Then, for example, the W film and the glue film 156 are polished using the upper layer film 154a as a stopper to form a plug 155 that fills the via hole 155a with W via the glue film 156.

次に、プラグ１５５とそれぞれ接続される第３の配線１６３及び第１の導電パッド１６０を形成する。
先ず、全面に例えばＰＶＤ法により配線膜１６１及びバリアメタル膜１６２を堆積する。配線膜１６１としては、例えばＡｌ合金膜（ここではＡｌ−Ｃｕ膜）を膜厚５００ｎｍ程度に成膜する。バリアメタル膜１６２としては、スパッタ法により例えばＴｉＮを膜厚１５０ｎｍ程度に成膜する。ここで、配線膜１６１の構造は、同一ルールのＦｅＲＡＭ以外のロジック部と同じ構造とされているため、配線の加工や信頼性上の問題はない。Next, a third wiring 163 and a first conductive pad 160 connected to the plug 155 are formed.
First, a wiring film 161 and a barrier metal film 162 are deposited on the entire surface by, eg, PVD. As the wiring film 161, for example, an Al alloy film (here, an Al—Cu film) is formed to a thickness of about 500 nm. As the barrier metal film 162, for example, TiN is formed to a thickness of about 150 nm by sputtering. Here, since the structure of the wiring film 161 is the same as that of the logic part other than the FeRAM having the same rule, there is no problem in processing of the wiring and reliability.

次に、反射防止膜として例えばＳｉＯＮ膜または反射防止膜（不図示）を成膜した後、リソグラフィー及びそれに続くドライエッチングにより反射防止膜、バリアメタル膜１６２及び配線膜１６１を配線形状に加工し、第３の配線１６３をパターン形成する。このとき、第３の配線１６３と同一構造に、耐湿リング１５３ａとプラグ１５５を介して接続されてなる耐湿リング１６３ａを形成する。   Next, after forming, for example, a SiON film or an antireflection film (not shown) as an antireflection film, the antireflection film, the barrier metal film 162, and the wiring film 161 are processed into a wiring shape by lithography and subsequent dry etching, A pattern of the third wiring 163 is formed. At this time, a moisture-resistant ring 163a connected to the moisture-resistant ring 153a and the plug 155 in the same structure as the third wiring 163 is formed.

ここで、第３の配線６３と同時に、当該第３の配線６３と同一構造であり第２の配線１５３とプラグ１５５を介して接続されてなる第１の導電パッド１６０をパターン形成する。この第１の導電パッド１６０は、後述の検査工程における各種試験（プローブによる針当て）が施される検査用パッドであり、ここでは略矩形状に形成されている。ところで、ＦｅＲＡＭの強誘電体キャパシタ構造は言わば圧電素子であり、強誘電体キャパシタ構造の近傍において圧力印加がなされることにより、強誘電特性の著しい劣化を招く。検査工程では針当てにより第１の導電パッド１６０に圧力が印加されることは避けられない。そこで本実施形態では、当該劣化を防止するために、強誘電体キャパシタ構造１３０の上方位置からできるだけ離間させた位置に第１の導電パッド１６０を設ける。   Here, simultaneously with the third wiring 63, the first conductive pad 160 having the same structure as the third wiring 63 and connected to the second wiring 153 via the plug 155 is patterned. The first conductive pad 160 is an inspection pad to be subjected to various tests (needle contact with a probe) in an inspection process described later, and is formed in a substantially rectangular shape here. By the way, the ferroelectric capacitor structure of FeRAM is a so-called piezoelectric element, and when a pressure is applied in the vicinity of the ferroelectric capacitor structure, the ferroelectric characteristics are significantly deteriorated. In the inspection process, it is inevitable that pressure is applied to the first conductive pad 160 by needle contact. Therefore, in this embodiment, in order to prevent the deterioration, the first conductive pad 160 is provided at a position as far as possible from the upper position of the ferroelectric capacitor structure 130.

続いて、図２０に示すように、第３の配線１６３（耐湿リング１６３を含む）及び第１の導電パッド１６０を覆うパシベーション膜１６６を形成する。
詳細には、先ず、ＣＶＤ法等によりプラズマＴＥＯＳ−ＮＳＧ膜を膜厚１００ｎｍ程度に堆積し、下層絶縁膜１６４を形成する。そして、下層絶縁膜１６４の表面の窒化を目的として、例えばＮ２Ｏのプラズマアニール処理（例えば３５０℃で２分間）を施す。Subsequently, as shown in FIG. 20, a passivation film 166 that covers the third wiring 163 (including the moisture-resistant ring 163) and the first conductive pad 160 is formed.
Specifically, first, a plasma TEOS-NSG film is deposited to a thickness of about 100 nm by a CVD method or the like, and a lower insulating film 164 is formed. Then, for example, N 2 O plasma annealing (for example, at 350 ° C. for 2 minutes) is performed for the purpose of nitriding the surface of the lower insulating film 164.

次に、下層絶縁膜１６４上に、ＣＶＤ法等によりプラズマＳｉＮ膜を膜厚３５０ｎｍ程度に堆積し、上層絶縁膜１６５を形成する。このとき、下層絶縁膜１６４上に上層絶縁膜１６５が積層されてなる２層構造のパシベーション膜１６６が形成される。本実施形態では、パシベーション膜１６６が本発明の保護絶縁膜となる。なお、図示の例では、下層絶縁膜１６４及び上層絶縁膜１６５の各表面を平坦に示しているが、実際には当該表面は第３の配線１６３の影響を受けて若干凹凸状となる。   Next, a plasma SiN film is deposited to a thickness of about 350 nm on the lower insulating film 164 by a CVD method or the like to form an upper insulating film 165. At this time, a passivation film 166 having a two-layer structure in which an upper insulating film 165 is stacked on the lower insulating film 164 is formed. In this embodiment, the passivation film 166 is the protective insulating film of the present invention. Note that, in the illustrated example, the surfaces of the lower insulating film 164 and the upper insulating film 165 are shown flat, but actually the surfaces are slightly uneven due to the influence of the third wiring 163.

続いて、図２１に示すように、パシベーション膜１６６に開口１６６ａを形成する。
詳細には、リソグラフィー及びドライエッチングによりパシベーション膜１６６を加工し、第１の導電パッド１６０の表面の一部を露出させる開口１６６ａを形成する。なお、図２１〜図２４では、第１の導電パッド１６０及びその周囲の様子を示す平面図を添付する。Subsequently, as shown in FIG. 21, an opening 166 a is formed in the passivation film 166.
Specifically, the passivation film 166 is processed by lithography and dry etching to form an opening 166a that exposes a part of the surface of the first conductive pad 160. 21 to 24, plan views showing the first conductive pads 160 and their surroundings are attached.

続いて、図２２に示すように、不図示の検査機器を用い、当該検査機器の探針（プローブ）１５８を開口１６６ａから露出する第１の導電パッド１６０に当接（針当て）させて、各種の試験を行う。検査内容としては、装置の動作が正常に行われるか否かを調べる試験（ＰＴ１）、データの書き込み及び読み出しの良否を判定するリテンション試験（ＰＴ２，ＰＴ３）、最終的な確認試験（ＰＴ４）を順次行う。   Next, as shown in FIG. 22, using an inspection device (not shown), the probe (probe) 158 of the inspection device is brought into contact (needle contact) with the first conductive pad 160 exposed from the opening 166a, Perform various tests. As inspection contents, a test (PT1) for checking whether the operation of the apparatus is normally performed, a retention test (PT2, PT3) for determining whether data is written and read, and a final confirmation test (PT4). Do it sequentially.

ＦｅＲＡＭの場合、上記のＰＴ１〜ＰＴ４の各試験が必要であり、各試験時におけるプローブによる第１の導電パッド１６０の表面への複数回の当接により、第１の導電パッド１６０に亀裂１５９等が発生することが多い。   In the case of FeRAM, each of the above-described PT1 to PT4 is required, and a crack 159 or the like is formed in the first conductive pad 160 due to a plurality of times of contact with the surface of the first conductive pad 160 by the probe during each test. Often occurs.

続いて、図２３に示すように、第１の導電パッド１６０と直接的に接続される第２の導電パッド１７０を形成する。
詳細には、開口１６６ａの内壁面を覆うように、例えばＰＶＤ法により、パシベーション膜１６６上にＡｌ合金膜（ここではＡｌ−Ｃｕ膜：膜厚５００ｎｍ程度）及びＴｉＮ膜（膜厚１５０ｎｍ程度）を積層する。そして、これらＴｉＮ膜及びＡｌ合金膜をリソグラフィー及びそれに続くドライエッチングによりパターニングする。この場合、平面視で第１の導電パッド１６０よりも若干サイズが小さくなる程度に、第１の導電パッド１６０と同様の略矩形状となるように、当該パターニングを実行する。これにより、パシベーション膜１６６の開口１６６ａの内壁底面（即ち第１の導電パッド１６０の表面）及び内壁側面からパシベーション膜１６６上にかけて覆い、平面視で第１の導電パッド１６０の形成領域に包含される第２の導電パッド１７０が形成される。この第２の導電パッド１７０は、ボンディングワイヤ等が接続される外部接続用パッドである。Subsequently, as shown in FIG. 23, a second conductive pad 170 that is directly connected to the first conductive pad 160 is formed.
Specifically, an Al alloy film (here, Al—Cu film: about 500 nm thick) and a TiN film (about 150 nm thick) are formed on the passivation film 166 by, eg, PVD so as to cover the inner wall surface of the opening 166a. Laminate. Then, these TiN film and Al alloy film are patterned by lithography and subsequent dry etching. In this case, the patterning is performed so that the first conductive pad 160 has a substantially rectangular shape that is slightly smaller in size than the first conductive pad 160 in plan view. This covers the bottom surface of the inner wall of the opening 166a of the passivation film 166 (that is, the surface of the first conductive pad 160) and the side surface of the inner wall from the side of the passivation film 166, and is included in the formation region of the first conductive pad 160 in plan view. A second conductive pad 170 is formed. The second conductive pad 170 is an external connection pad to which a bonding wire or the like is connected.

続いて、図２４に示すように、緩衝防止膜１７１を形成する。   Subsequently, as shown in FIG. 24, a buffer preventing film 171 is formed.

詳細には、例えば感光性ポリイミドを膜厚３μｍ程度に塗布し、パシベーション膜１６６上を覆って保護し、第２の導電パッド１７０の表面の一部のみを露出させる開口１７１ａを有する緩衝防止膜１７１を形成する。ここで、非感光性ポリイミドを用いる場合には、非感光性ポリイミド上にレジストパターンを形成し、専用現像液で非感光性ポリイミドを溶解する。その後、例えば横型炉で緩衝防止膜１７１に例えば３１０℃でＮ２ガスを１００リットル／分の流量で４０分間の熱処理を施し、ポリイミドを硬化させる。なお、緩衝防止膜１７１の材料として、ポリイミドの代わりに例えばノボラック樹脂を用いても良い。Specifically, for example, a photosensitive polyimide is applied to a film thickness of about 3 μm, covers and protects the passivation film 166, and has an anti-buffer film 171 having an opening 171a that exposes only a part of the surface of the second conductive pad 170. Form. Here, when non-photosensitive polyimide is used, a resist pattern is formed on the non-photosensitive polyimide, and the non-photosensitive polyimide is dissolved with a dedicated developer. After that, for example, in a horizontal furnace, the buffer film 171 is heat-treated at 310 ° C., for example, with N 2 gas at a flow rate of 100 liters / minute for 40 minutes to cure the polyimide. For example, a novolac resin may be used as the material of the buffer preventing film 171 instead of polyimide.

しかる後、諸々の後工程を実行する。例えば、シリコン半導体基板１１０の背面研磨、基板のダイシング、ワイヤ・ボンディング等による、開口１７１ａから露出する第２の導電パッド１７０の表面への外部接続、パッケージ化、及びパッケージ最終検査等を経て、本実施形態によるＦｅＲＡＭを完成させる。   Thereafter, various post processes are executed. For example, the external connection to the surface of the second conductive pad 170 exposed from the opening 171a by packaging the back surface of the silicon semiconductor substrate 110, substrate dicing, wire bonding, etc., packaging, and final inspection of the package The FeRAM according to the embodiment is completed.

本実施形態では、第１の導電パッド１６０の表面に針当てして各種試験を行う検査工程の後に、当該検査により亀裂１５９等が生じた第１の導電パッド１６０の表面を覆う第２の導電パッド１７０を形成する。この第２の導電パッド１７０は、第１の導電パッド１６０に整合した位置で当該第１の導電パッド１６０に包含されるサイズに形成される。即ち、第２の導電パッド１７０は、第１の導電パッド１６０と同様に、強誘電体キャパシタ構造１３０と可及的に離間しており、第２の導電パッド１７０の下方には強誘電体キャパシタ構造１３０が存しないため、第２の導電パッド１７０に外部との接続時に圧力が印加されても強誘電体キャパシタ構造１３０に悪影響を与えることはない。   In the present embodiment, the second conductive layer covering the surface of the first conductive pad 160 in which a crack 159 or the like has been generated by the inspection after the inspection step of performing various tests by applying a needle to the surface of the first conductive pad 160. A pad 170 is formed. The second conductive pad 170 is formed in a size included in the first conductive pad 160 at a position aligned with the first conductive pad 160. That is, like the first conductive pad 160, the second conductive pad 170 is separated from the ferroelectric capacitor structure 130 as much as possible, and below the second conductive pad 170 is a ferroelectric capacitor. Since the structure 130 does not exist, even if a pressure is applied to the second conductive pad 170 when connected to the outside, the ferroelectric capacitor structure 130 is not adversely affected.

更に、第２の導電パッド１７０は、パシベーション膜１６６の開口１６６ａの内壁底面及び内壁側面からパシベーション膜１６６上にかけて覆うように形成される。パシベーション膜１６６の開口の内壁側面が最も顕著な水分・水素の浸入経路となることから、この内壁底面（即ち第１の導電パッド１６０の表面）及び内壁側面からパシベーション膜１６６上にかけて覆うように第２の導電パッド１７０を形成することにより、例えば上記の後工程におけるダイシング及びパッケージ化の際にも、当該浸入経路が可及的に閉ざされている。従って、強誘電体膜１２５への水分・水素の浸入が可及的に抑止され、強誘電体膜１２５の高い強誘電特性が十分に保持される。   Further, the second conductive pad 170 is formed so as to cover the inner wall bottom surface and the inner wall side surface of the opening 166 a of the passivation film 166 over the passivation film 166. Since the inner wall side surface of the opening of the passivation film 166 is the most remarkable moisture / hydrogen infiltration path, the inner wall bottom surface (that is, the surface of the first conductive pad 160) and the inner wall side surface are covered to cover the passivation film 166. By forming the second conductive pads 170, the intrusion path is closed as much as possible, for example, in the dicing and packaging in the above-described post-process. Therefore, the penetration of moisture and hydrogen into the ferroelectric film 125 is suppressed as much as possible, and the high ferroelectric characteristics of the ferroelectric film 125 are sufficiently maintained.

以上説明したように、本実施形態によれば、比較的簡易な構成で十分な水・水素の内部侵入を確実に防止し、強誘電体膜１２５を有する強誘電体キャパシタ構造１３０の高性能を保持する信頼性の高いＦｅＲＡＭを実現することができる。   As described above, according to the present embodiment, sufficient penetration of water and hydrogen can be reliably prevented with a relatively simple configuration, and the high performance of the ferroelectric capacitor structure 130 having the ferroelectric film 125 can be improved. A highly reliable FeRAM can be realized.

以上説明したように、本実施形態によれば、比較的簡易な構成で水素の強誘電体膜１２５への侵入を確実に防止し、強誘電体膜１２５を有する強誘電体キャパシタ構造１３０の高性能を保持する信頼性の高いスタック型のＦｅＲＡＭを実現することができる。   As described above, according to the present embodiment, hydrogen can be surely prevented from entering the ferroelectric film 125 with a relatively simple configuration, and the ferroelectric capacitor structure 130 having the ferroelectric film 125 can be prevented from being high. A highly reliable stack-type FeRAM that maintains performance can be realized.

なお、本実施形態でも、第１の実施形態と同様に、変形例１〜３（図１１Ａ〜図１３Ｂ）をそれぞれ適用しても良い。   In the present embodiment, as in the first embodiment, the first to third modifications (FIGS. 11A to 13B) may be applied.

本発明によれば、比較的簡易な構成で十分な水・水素の内部侵入を確実に防止し、強誘電体からなるキャパシタ膜を有するキャパシタ構造の高性能を保持する信頼性の高い半導体装置を実現することができる。
According to the present invention, there is provided a highly reliable semiconductor device that reliably prevents internal penetration of sufficient water and hydrogen with a relatively simple configuration and maintains high performance of a capacitor structure having a capacitor film made of a ferroelectric substance. Can be realized.

Claims (8)

半導体基板の上方に形成されており、下部電極と上部電極とにより強誘電体からなるキャパシタ膜を挟持してなるキャパシタ構造と、
前記キャパシタ構造の上方に形成されており、前記キャパシタ構造と電気的に接続されてなる配線構造と、
下方に前記キャパシタ構造の存しない局所的な形成領域で前記配線構造と電気的に接続されており、検査機器のプローブが直接的に当接することで各種の試験が施された第１の導電パッドと、
前記第１の導電パッド及び前記配線構造を覆い、前記第１の導電パッドの表面における前記検査の部位のみを露出させる開口を有する第１の保護絶縁膜と、
前記第１の保護絶縁膜上から前記開口の内壁面にかけて覆って前記第１の導電パッドと電気的に接続され、前記第１の導電パッドの前記形成領域に整合する位置に形成されており、外部との電気的接続を図る第２の導電パッドと、
前記第２の導電パッド及び前記第１の保護絶縁膜を覆い、前記第２の導電パッドの表面における前記外部との電気的接続の部位のみを露出させる開口を有する第２の保護絶縁膜と、
前記第２の保護絶縁膜を覆い、前記第２の導電パッドの表面における前記外部との電気的接続の部位を露出させる開口を有する絶縁膜と
を含み、
前記第１の保護絶縁膜は、第１酸化膜と、前記第１酸化膜上に形成された第１窒化膜とを含み、
前記第２の保護絶縁膜は、第２酸化膜と、前記第２酸化膜上に形成された第２窒化膜とを含み、
前記第１酸化膜と前記第１窒化膜との間、及び前記第２酸化膜と前記第２窒化膜との間の少なくとも一方にアルミナ膜が形成されていることを特徴とする半導体装置。 A capacitor structure formed above a semiconductor substrate and having a capacitor film made of a ferroelectric material sandwiched between a lower electrode and an upper electrode;
A wiring structure formed above the capacitor structure and electrically connected to the capacitor structure;
A first conductive pad which is electrically connected to the wiring structure in a local formation region where the capacitor structure does not exist below, and has been subjected to various tests by directly contacting a probe of an inspection device When,
A first protective insulating film that covers the first conductive pad and the wiring structure and has an opening that exposes only the inspection portion on the surface of the first conductive pad;
Covering from the first protective insulating film to the inner wall surface of the opening and electrically connected to the first conductive pad, the first conductive pad is formed at a position aligned with the formation region, A second conductive pad for electrical connection with the outside;
A second protective insulating film that covers the second conductive pad and the first protective insulating film and has an opening that exposes only the portion of the surface of the second conductive pad that is electrically connected to the outside;
It covers the second protective insulating film, look including an insulating film having an opening exposing a portion of the electrical connection between the outer the surface of the second conductive pad,
The first protective insulating film includes a first oxide film and a first nitride film formed on the first oxide film,
The second protective insulating film includes a second oxide film and a second nitride film formed on the second oxide film,
A semiconductor device, wherein an alumina film is formed between at least one of the first oxide film and the first nitride film and between the second oxide film and the second nitride film . 前記第２の導電パッドは、前記第１の導電パッドよりも小さく、前記第１の導電パッドの前記形成領域に包含される形状に形成されていることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor according to claim 1, wherein the second conductive pad is smaller than the first conductive pad and is formed in a shape included in the formation region of the first conductive pad. apparatus. 前記第２の導電パッドは、前記第１の導電パッドと直接的に接続されていることを特徴とする請求項１又は２に記載の半導体装置。   The semiconductor device according to claim 1, wherein the second conductive pad is directly connected to the first conductive pad. 前記絶縁膜は、ポリイミド又はノボラック樹脂を材料として形成されることを特徴とする請求項１〜３のいずれか１項に記載の半導体装置。 The insulating layer, the semiconductor device according to any one of claims 1 to 3, characterized in that formed polyimide or novolac resin as a material. 半導体基板の上方に、下部電極と上部電極とにより強誘電体からなるキャパシタ膜を挟持してなるキャパシタ構造を形成する工程と、
前記キャパシタ構造の上方に、前記キャパシタ構造と電気的に接続されるように配線構造を形成する工程と、
下方に前記キャパシタ構造の存しない局所的な形成領域において、前記配線構造と電気的に接続されるように第１の導電パッドを形成する工程と、
前記第１の導電パッド及び前記配線構造を覆うように第１の保護絶縁膜を形成した後、前記第１の保護絶縁膜に、前記第１の導電パッドの表面における検査の部位のみを露出させる開口を形成する工程と、
前記開口から、検査機器のプローブを前記第１の導電パッドの表面に直接的に当接することにより、各種の試験を行う工程と、
前記第１の保護絶縁膜上から前記開口の内壁面にかけて覆って前記第１の導電パッドと電気的に接続され、前記第１の導電パッドの前記形成領域に整合する位置に、外部との電気的接続を図る第２の導電パッドを形成する工程と、
前記第２の導電パッド及び前記第１の保護絶縁膜を覆うように第２の保護絶縁膜を形成した後、前記第２の保護絶縁膜に、前記第２の導電パッドの表面における前記外部との電気的接続の部位のみを露出させる開口を形成する工程と、
前記第２の保護絶縁膜を覆うように絶縁膜を形成した後、前記絶縁膜に、前記第２の導電パッドの表面における前記外部との電気的接続の部位を露出させる開口を形成する工程と
を含み、
前記第１の保護絶縁膜は、第１酸化膜と、前記第１酸化膜上に形成された第１窒化膜とを含み、
前記第２の保護絶縁膜は、第２酸化膜と、前記第２酸化膜上に形成された第２窒化膜とを含み、
前記第１酸化膜と前記第１窒化膜との間、及び前記第２酸化膜と前記第２窒化膜との間の少なくとも一方にアルミナ膜が形成されることを特徴とする半導体装置の製造方法。 Forming a capacitor structure in which a capacitor film made of a ferroelectric material is sandwiched between a lower electrode and an upper electrode above a semiconductor substrate;
Forming a wiring structure above the capacitor structure so as to be electrically connected to the capacitor structure;
Forming a first conductive pad so as to be electrically connected to the wiring structure in a local formation region below the capacitor structure;
After forming a first protective insulating film so as to cover the first conductive pad and the wiring structure, only the inspection site on the surface of the first conductive pad is exposed to the first protective insulating film. Forming an opening;
A process of performing various tests by directly contacting the probe of the inspection device to the surface of the first conductive pad from the opening;
Covering from the first protective insulating film to the inner wall surface of the opening, and electrically connected to the first conductive pad and aligned with the formation area of the first conductive pad, Forming a second conductive pad for achieving a general connection;
After forming a second protective insulating film so as to cover the second conductive pad and the first protective insulating film, the second protective insulating film is formed on the surface of the second conductive pad with the outside. Forming an opening that exposes only the portion of the electrical connection;
Forming an insulating film so as to cover the second protective insulating film, and then forming an opening in the insulating film that exposes a portion of the second conductive pad that is electrically connected to the outside; only including,
The first protective insulating film includes a first oxide film and a first nitride film formed on the first oxide film,
The second protective insulating film includes a second oxide film and a second nitride film formed on the second oxide film,
A method of manufacturing a semiconductor device, wherein an alumina film is formed between at least one of the first oxide film and the first nitride film and between the second oxide film and the second nitride film. . 前記第２の導電パッドを、前記第１の導電パッドよりも小さく、前記第１の導電パッドの前記形成領域に包含される形状に形成することを特徴とする請求項５に記載の半導体装置の製造方法。 6. The semiconductor device according to claim 5 , wherein the second conductive pad is formed in a shape that is smaller than the first conductive pad and is included in the formation region of the first conductive pad. Production method. 前記第２の導電パッドを、前記第１の導電パッドと直接的に接続されるように形成することを特徴とする請求項５又は６に記載の半導体装置の製造方法。 Said second conductive pad, manufacturing method of a semiconductor device according to claim 5 or 6, characterized in that formed so as to be connected directly with the first conductive pads. 前記絶縁膜は、ポリイミド又はノボラック樹脂を材料として形成されることを特徴とする請求項５〜７のいずれか１項に記載の半導体装置の製造方法。 The insulating layer, a method of manufacturing a semiconductor device according to any one of claims 5-7, characterized by being formed of polyimide or novolac resin as a material.
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