JP5351151B2 - 試験システム - Google Patents
試験システム Download PDFInfo
- Publication number
- JP5351151B2 JP5351151B2 JP2010514287A JP2010514287A JP5351151B2 JP 5351151 B2 JP5351151 B2 JP 5351151B2 JP 2010514287 A JP2010514287 A JP 2010514287A JP 2010514287 A JP2010514287 A JP 2010514287A JP 5351151 B2 JP5351151 B2 JP 5351151B2
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- JP
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- Prior art keywords
- test
- wafer
- writing
- semiconductor
- circuits
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000012360 testing method Methods 0.000 title claims description 301
- 235000012431 wafers Nutrition 0.000 claims description 299
- 239000004065 semiconductor Substances 0.000 claims description 137
- 230000032258 transport Effects 0.000 claims description 3
- 239000012528 membrane Substances 0.000 description 26
- 239000000758 substrate Substances 0.000 description 23
- 238000010586 diagram Methods 0.000 description 15
- 238000012546 transfer Methods 0.000 description 14
- 238000000034 method Methods 0.000 description 8
- 230000006837 decompression Effects 0.000 description 6
- 230000004044 response Effects 0.000 description 6
- 239000000523 sample Substances 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 5
- 238000007493 shaping process Methods 0.000 description 5
- 238000005259 measurement Methods 0.000 description 4
- 238000003825 pressing Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000013013 elastic material Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
- G01R31/318511—Wafer Test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
- G01R31/2889—Interfaces, e.g. between probe and tester
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56016—Apparatus features
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C2029/5602—Interface to device under test
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Tests Of Electronic Circuits (AREA)
Description
Claims (9)
- 半導体ウエハに形成された複数の半導体チップを試験する試験システムであって、
前記複数の半導体チップと対応して設けられ、それぞれ与えられる試験データに基づいて、対応する前記半導体チップを試験する複数の試験回路が形成された試験用ウエハと、
前記複数の試験回路と対応して設けられ、それぞれ対応する前記試験回路に、前記試験データを書き込む複数の書込回路が形成された書込用ウエハと
を備え、
それぞれの前記試験回路は、前記試験データを格納する、不揮発性且つ書き換え可能なパターンメモリを有する試験システム。 - それぞれの前記試験回路に、同一の前記試験データを並列に書き込む制御装置を更に備える
請求項1に記載の試験システム。 - 前記制御装置は、前記書込用ウエハを介して前記試験データをそれぞれの前記試験回路に書き込む
請求項2に記載の試験システム。 - 前記書込用ウエハは、与えられる前記試験データをそれぞれの前記書込回路に分配する分配回路が更に形成され、
前記制御装置は、前記分配回路に前記試験データを供給する
請求項2または3に記載の試験システム。 - 前記試験用ウエハが固定される配線基板を格納し、搬送される前記半導体ウエハに対して前記試験用ウエハから信号を供給することで、前記半導体ウエハを試験するチャンバを更に備え、
前記制御装置は、前記チャンバの外部から、前記配線基板を介して、それぞれの前記試験回路に前記試験データを書き込む
請求項2に記載の試験システム。 - 前記試験用ウエハが固定される配線基板を格納し、搬送される前記半導体ウエハに対して前記試験用ウエハから信号を供給することで、前記半導体ウエハを試験するチャンバを更に備え、
前記制御装置は、前記試験用ウエハに前記試験データを書き込む場合に、前記試験データを記憶した前記書込用ウエハを、前記チャンバ内に搬送し、前記チャンバ内において、前記書込用ウエハから前記試験用ウエハのそれぞれの前記試験回路に前記試験データを書き込む
請求項2または3に記載の試験システム。 - 前記書込用ウエハには、前記複数の書込回路に対して共通に設けられ、前記試験データを格納して、それぞれの前記書込回路に供給する共通格納部が更に形成される
請求項1から6のいずれか一項に記載の試験システム。 - 前記試験データが書き込まれた前記試験用ウエハと、前記半導体ウエハとを一体に固定するウエハ固定部と、
前記ウエハ固定部により一体に固定された前記試験用ウエハおよび前記半導体ウエハが搬送され、前記試験用ウエハを用いて前記半導体ウエハを試験するチャンバと
を更に備える請求項2に記載の試験システム。 - 前記制御装置は、前記チャンバから搬送された前記試験用ウエハに、次に行うべき試験に応じた前記試験データを書き込む
請求項8に記載の試験システム。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2008/059844 WO2009144791A1 (ja) | 2008-05-28 | 2008-05-28 | 試験システムおよび書込用ウエハ |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2009144791A1 JPWO2009144791A1 (ja) | 2011-09-29 |
JP5351151B2 true JP5351151B2 (ja) | 2013-11-27 |
Family
ID=41376691
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010514287A Expired - Fee Related JP5351151B2 (ja) | 2008-05-28 | 2008-05-28 | 試験システム |
Country Status (4)
Country | Link |
---|---|
US (1) | US8624620B2 (ja) |
JP (1) | JP5351151B2 (ja) |
TW (1) | TW200951463A (ja) |
WO (1) | WO2009144791A1 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20120112648A (ko) * | 2010-08-17 | 2012-10-11 | 가부시키가이샤 아드반테스트 | 접속 장치, 그것을 구비한 반도체 웨이퍼 시험 장치 및 접속 방법 |
KR20180138472A (ko) * | 2017-06-21 | 2018-12-31 | 에스케이하이닉스 주식회사 | 테스트 회로를 포함하는 반도체 장치 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6298234U (ja) * | 1985-12-10 | 1987-06-23 | ||
JPH11274252A (ja) * | 1998-03-19 | 1999-10-08 | Mitsubishi Electric Corp | 半導体装置の検査装置及びその検査方法 |
JP2006287035A (ja) * | 2005-04-01 | 2006-10-19 | Seiko Epson Corp | 半導体ウエハ、および強誘電体メモリ装置の試験方法 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3526485A1 (de) * | 1985-07-24 | 1987-02-05 | Heinz Krug | Schaltungsanordnung zum pruefen integrierter schaltungseinheiten |
US5600257A (en) * | 1995-08-09 | 1997-02-04 | International Business Machines Corporation | Semiconductor wafer test and burn-in |
US6750527B1 (en) * | 1996-05-30 | 2004-06-15 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device having a plurality of wells, test method of testing the semiconductor integrated circuit device, and test device which executes the test method |
US6181145B1 (en) * | 1997-10-13 | 2001-01-30 | Matsushita Electric Industrial Co., Ltd. | Probe card |
JPH11277252A (ja) | 1998-03-26 | 1999-10-12 | Toshiba Corp | イオンビーム加工方法及びマイクロデバイス |
US6337577B1 (en) * | 1998-05-11 | 2002-01-08 | Micron Technology, Inc. | Interconnect and system for testing bumped semiconductor components with on-board multiplex circuitry for expanding tester resources |
US6232790B1 (en) * | 1999-03-08 | 2001-05-15 | Honeywell Inc. | Method and apparatus for amplifying electrical test signals from a micromechanical device |
US6812718B1 (en) * | 1999-05-27 | 2004-11-02 | Nanonexus, Inc. | Massively parallel interface for electronic circuits |
US6400173B1 (en) | 1999-11-19 | 2002-06-04 | Hitachi, Ltd. | Test system and manufacturing of semiconductor device |
JP2001338953A (ja) * | 2000-05-29 | 2001-12-07 | Mitsubishi Electric Corp | 半導体試験装置、半導体試験方法および半導体装置 |
US7135676B2 (en) | 2000-06-27 | 2006-11-14 | Ebara Corporation | Inspection system by charged particle beam and method of manufacturing devices using the system |
US6379982B1 (en) * | 2000-08-17 | 2002-04-30 | Micron Technology, Inc. | Wafer on wafer packaging and method of fabrication for full-wafer burn-in and testing |
DE10060438B4 (de) * | 2000-12-05 | 2004-09-09 | Infineon Technologies Ag | Testanordnung zum parallelen Test einer Mehrzahl von integrierten Schaltkreisen und Testverfahren |
JP2002222839A (ja) | 2001-01-29 | 2002-08-09 | Advantest Corp | プローブカード |
TW515895B (en) | 2001-06-11 | 2003-01-01 | Weltrend Semiconductor Inc | Method and circuit for detecting total consumed power of system load output by the power supply |
US6815231B2 (en) * | 2001-06-11 | 2004-11-09 | Hitachi, Ltd. | Method of testing and manufacturing nonvolatile semiconductor memory |
US6871307B2 (en) * | 2001-10-10 | 2005-03-22 | Tower Semiconductorltd. | Efficient test structure for non-volatile memory and other semiconductor integrated circuits |
KR100634923B1 (ko) | 2002-01-25 | 2006-10-17 | 가부시키가이샤 어드밴티스트 | 프로브 카드 및 프로브 카드의 제조 방법 |
KR100712561B1 (ko) * | 2006-08-23 | 2007-05-02 | 삼성전자주식회사 | 웨이퍼 형태의 프로브 카드 및 그 제조방법과 웨이퍼형태의 프로브 카드를 구비한 반도체 검사장치 |
US7816154B2 (en) * | 2007-06-06 | 2010-10-19 | Renesas Electronics Corporation | Semiconductor device, a method of manufacturing a semiconductor device and a testing method of the same |
-
2008
- 2008-05-28 WO PCT/JP2008/059844 patent/WO2009144791A1/ja active Application Filing
- 2008-05-28 JP JP2010514287A patent/JP5351151B2/ja not_active Expired - Fee Related
-
2009
- 2009-04-29 TW TW098114216A patent/TW200951463A/zh unknown
-
2010
- 2010-11-22 US US12/952,110 patent/US8624620B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6298234U (ja) * | 1985-12-10 | 1987-06-23 | ||
JPH11274252A (ja) * | 1998-03-19 | 1999-10-08 | Mitsubishi Electric Corp | 半導体装置の検査装置及びその検査方法 |
JP2006287035A (ja) * | 2005-04-01 | 2006-10-19 | Seiko Epson Corp | 半導体ウエハ、および強誘電体メモリ装置の試験方法 |
Also Published As
Publication number | Publication date |
---|---|
TW200951463A (en) | 2009-12-16 |
US8624620B2 (en) | 2014-01-07 |
WO2009144791A1 (ja) | 2009-12-03 |
JPWO2009144791A1 (ja) | 2011-09-29 |
US20110115519A1 (en) | 2011-05-19 |
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