JP5319247B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5319247B2 JP5319247B2 JP2008292206A JP2008292206A JP5319247B2 JP 5319247 B2 JP5319247 B2 JP 5319247B2 JP 2008292206 A JP2008292206 A JP 2008292206A JP 2008292206 A JP2008292206 A JP 2008292206A JP 5319247 B2 JP5319247 B2 JP 5319247B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 39
- 239000004065 semiconductor Substances 0.000 title claims description 36
- 238000012545 processing Methods 0.000 claims description 44
- 238000000034 method Methods 0.000 claims description 40
- 239000000758 substrate Substances 0.000 claims description 36
- 238000002955 isolation Methods 0.000 claims description 35
- 230000000052 comparative effect Effects 0.000 description 26
- 238000012805 post-processing Methods 0.000 description 20
- 238000012546 transfer Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 7
- 238000011282 treatment Methods 0.000 description 6
- 239000000047 product Substances 0.000 description 5
- 239000006227 byproduct Substances 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 238000009966 trimming Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000007790 scraping Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Memories (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Description
図1は、第1実施形態の半導体装置101の製造方法を説明するための平面図及び側方断面図である。図1には、(1)で示す平面図と、(2)で示すA−A’断面図と、(3)で示すB−B’断面図が示されている。図1の平面図には、A−A’断面とB−B’断面の位置が示されている。
図10は、第2実施形態の半導体装置101の製造方法を示す工程図である。図10には、図10Aから図10Eの工程図が示されている。図10Aから図10Eの工程図は、当該製造方法の工程順に並んでいる。また、図10Aから図10Eには、図1や図2と同様に、(1)で示す平面図と、(2)で示すA−A’断面図と、(3)で示すB−B’断面図が示されている。図10の詳細については、図11から図13の説明後に説明する。
111 基板
112 ゲート絶縁膜
113 ゲート電極
121 穴
131 ハードマスク層
132 転写膜
141 素子分離層
151 酸化膜
201 第1のBARC
202 第1のレジスト
301 第2のBARC
302 第2のレジスト
Claims (5)
- ゲート電極の延伸方向の端部同士が隙間を挟んで対向する少なくとも一対のゲート電極を形成する、半導体装置の製造方法であって、
基板上に、ゲート絶縁膜とゲート電極層とを順に形成し、
前記ゲート電極層上に、第1の反射防止膜と第1のレジストとを順に形成し、
前記第1のレジストを露光及び現像し、
前記第1のレジスト又は前記第1の反射防止膜をマスクとして、前記ゲート電極層を加工することにより、前記ゲート電極層を、前記隙間が形成される領域から除去して、前記ゲート電極層に穴を形成し、
前記穴が形成された前記ゲート電極層上に、第2の反射防止膜と第2のレジストとを順に形成し、
前記第2のレジストを露光及び現像し、
前記第2のレジスト又は前記第2の反射防止膜をマスクとして、前記ゲート電極層を加工することにより、前記ゲート電極層から、前記端部同士が前記隙間を挟んで対向する前記少なくとも一対のゲート電極を形成する、
ことを特徴とする半導体装置の製造方法。 - 前記基板上に素子分離層を形成することで、前記基板上に素子領域と素子分離領域とを形成し、
前記素子分離層が形成された前記基板上に、前記ゲート絶縁膜と前記ゲート電極層とを順に形成し、
前記穴を、前記素子分離領域に形成することを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記第2の反射防止膜の膜厚は、前記穴の輪郭線上における膜厚が、前記第2の反射防止膜の平坦部の膜厚に対し、0%から20%薄いことを特徴とする請求項1又は2に記載の半導体装置の製造方法。
- ゲート電極の延伸方向の端部同士が隙間を挟んで対向する少なくとも一対のゲート電極を形成する、半導体装置の製造方法であって、
基板上に、ゲート絶縁膜とゲート電極層とを順に形成し、
前記ゲート電極層上に、第1の反射防止膜と第1のレジストとを順に形成し、
前記第1のレジストを露光及び現像し、
前記第1のレジスト又は前記第1の反射防止膜をマスクとして、前記ゲート電極層を加工することにより、前記ゲート電極層を、前記隙間が形成される領域から除去して、前記ゲート電極層に穴を形成し、
前記穴が形成された前記ゲート電極層上に酸化膜を塗布して、前記穴に前記酸化膜を埋め込み、
前記酸化膜が埋め込まれた前記ゲート電極層上に、第2の反射防止膜と第2のレジストとを順に形成し、
前記第2のレジストを露光及び現像し、
前記第2のレジスト又は前記第2の反射防止膜をマスクとして、前記ゲート電極層を加工することにより、前記ゲート電極層から、前記端部同士が前記隙間を挟んで対向する前記少なくとも一対のゲート電極を形成する、
ことを特徴とする半導体装置の製造方法。 - 前記基板上に素子分離層を形成することで、前記基板上に素子領域と素子分離領域とを形成し、
前記素子分離層が形成された前記基板上に、前記ゲート絶縁膜と前記ゲート電極層とを順に形成し、
前記穴を、前記素子領域と前記素子分離領域との境界線上に形成することを特徴とする請求項4に記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2008292206A JP5319247B2 (ja) | 2008-11-14 | 2008-11-14 | 半導体装置の製造方法 |
US12/470,094 US8168520B2 (en) | 2008-11-14 | 2009-05-21 | Method of manufacturing semiconductor device |
TW098138720A TWI421920B (zh) | 2008-11-14 | 2009-11-13 | 製造半導體裝置的方法 |
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JP2008292206A JP5319247B2 (ja) | 2008-11-14 | 2008-11-14 | 半導体装置の製造方法 |
Publications (2)
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JP2010118599A JP2010118599A (ja) | 2010-05-27 |
JP5319247B2 true JP5319247B2 (ja) | 2013-10-16 |
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JP2008292206A Expired - Fee Related JP5319247B2 (ja) | 2008-11-14 | 2008-11-14 | 半導体装置の製造方法 |
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US (1) | US8168520B2 (ja) |
JP (1) | JP5319247B2 (ja) |
TW (1) | TWI421920B (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
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US8304172B2 (en) * | 2009-11-12 | 2012-11-06 | Advanced Micro Devices, Inc. | Semiconductor device fabrication using a multiple exposure and block mask approach to reduce design rule violations |
DE102010040066B4 (de) | 2010-08-31 | 2012-05-24 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Verfahren zur Herstellung von Gateelektroden eines Halbleiterbauelements, die durch eine Hartmaske und Doppelbelichtung in Verbindung mit einem Größenreduzierungsabstandshalter hergestellt sind |
KR101815590B1 (ko) | 2010-11-23 | 2018-01-05 | 삼성전자 주식회사 | 반도체 소자의 패턴 형성 방법 |
US8610176B2 (en) * | 2011-01-11 | 2013-12-17 | Qualcomm Incorporated | Standard cell architecture using double poly patterning for multi VT devices |
JP5661524B2 (ja) * | 2011-03-22 | 2015-01-28 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
DE102011079919B4 (de) * | 2011-07-27 | 2016-11-10 | Globalfoundries Inc. | Verfahren zur Herstellung von komplementären Transistoren mit erhöhter Integrität von Gateschichtstapeln durch Vergrößern des Abstandes von Gateleitungen |
US8481381B2 (en) | 2011-09-14 | 2013-07-09 | Globalfoundries Inc. | Superior integrity of high-k metal gate stacks by preserving a resist material above end caps of gate electrode structures |
US8836040B2 (en) * | 2012-11-07 | 2014-09-16 | Qualcomm Incorporated | Shared-diffusion standard cell architecture |
WO2015181679A1 (en) * | 2014-05-27 | 2015-12-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
Family Cites Families (14)
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US6042998A (en) | 1993-09-30 | 2000-03-28 | The University Of New Mexico | Method and apparatus for extending spatial frequencies in photolithography images |
JPH09289153A (ja) * | 1996-04-23 | 1997-11-04 | Oki Electric Ind Co Ltd | 半導体装置の製造方法及びそれに用いるマスク |
US5858580A (en) | 1997-09-17 | 1999-01-12 | Numerical Technologies, Inc. | Phase shifting circuit manufacture method and apparatus |
JPH113936A (ja) * | 1997-06-13 | 1999-01-06 | Nec Corp | 半導体装置の製造方法 |
JPH11340436A (ja) * | 1998-05-25 | 1999-12-10 | Nec Corp | 半導体記憶装置の製造方法 |
JP4776813B2 (ja) * | 2001-06-12 | 2011-09-21 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US6337269B1 (en) * | 2001-06-21 | 2002-01-08 | United Microelectronics Corp. | Method of fabricating a dual damascene structure |
KR100428768B1 (ko) * | 2001-08-29 | 2004-04-30 | 삼성전자주식회사 | 트렌치 소자 분리형 반도체 장치 및 그 형성 방법 |
JP2005129568A (ja) * | 2003-10-21 | 2005-05-19 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2005259991A (ja) * | 2004-03-11 | 2005-09-22 | Sony Corp | パターン形成方法 |
JP2005268321A (ja) * | 2004-03-16 | 2005-09-29 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2007096099A (ja) | 2005-09-29 | 2007-04-12 | Toshiba Corp | 半導体装置の製造方法 |
KR100823704B1 (ko) * | 2006-10-20 | 2008-04-21 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 그 제조 방법 |
US7759235B2 (en) * | 2007-06-07 | 2010-07-20 | Infineon Technologies Ag | Semiconductor device manufacturing methods |
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2008
- 2008-11-14 JP JP2008292206A patent/JP5319247B2/ja not_active Expired - Fee Related
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2009
- 2009-05-21 US US12/470,094 patent/US8168520B2/en not_active Expired - Fee Related
- 2009-11-13 TW TW098138720A patent/TWI421920B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
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US8168520B2 (en) | 2012-05-01 |
TWI421920B (zh) | 2014-01-01 |
JP2010118599A (ja) | 2010-05-27 |
US20100124815A1 (en) | 2010-05-20 |
TW201110202A (en) | 2011-03-16 |
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