JP5313424B2 - トラッピング(trapping)を低減させたIII族窒化物ベースの電界効果トランジスタ(FET)およびトランジスタの製造方法 - Google Patents
トラッピング(trapping)を低減させたIII族窒化物ベースの電界効果トランジスタ(FET)およびトランジスタの製造方法 Download PDFInfo
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Description
(発明の分野)
本発明は、高周波のソリッドステートトランジスタ(solid state transistor)に関し、より詳しくは、III族窒化物ベースの電界効果トランジスタおよび高電子移動度トランジスタに関する。
マイクロ波システムは、一般に、ソリッドステートトランジスタを増幅器および発信器として使用しており、それにより、システムサイズ(system size)を著しく小さくし、信頼性を増大させた。拡大するマイクロ波システムに対処するためには、その動作周波数および動作電力を増すことが重要である。周波数信号が高いほどより多くの情報(帯域幅)を伝達することができ、非常に高い利得を持つより小さいアンテナが可能となり、解像度の改良されたレーダを提供する。
本発明は、好ましくは、GaN/AlGaNから形成され交流ゲートドライブに応答する改良された増幅特性を示すIII族窒化物ベースの改良されたFETおよびHEMTを提供する。また、本発明は、その新規なGaN/AlGaNのFETおよびHEMTを製造する新規な方法を提供する。
(新規GaN/AlGaNのFETおよびHEMT)
図1は、本発明に従って組み立てた新規なIII族窒化物ベースのFET10を示す。それは、サファイア(Al2O3)または炭化ケイ素(SiC)のいずれかであり得る基板11を含み、好ましい基板は、4Hポリタイプの炭化ケイ素である。3C、6Hおよび15Rポリタイプを含む他のポリタイプの炭化ケイ素もまた使用することができる。AlxGa1-xNバッファ層12(ただし、xは0と1の間)が基板11の上にあり、FET10の炭化ケイ素基板とその他のものとの間の適切な結晶構造の遷移(crystal structure transition)を提供する。
上述のように、誘電層は、そのFETおよびHEMTの表面とストレス下でも安定な強力な結合を有することが必要である。その層を付着するさまざまな方法を使用することができ、例えば、限定するものではないが、HEMTが形成される本来の位置へのスパッタリング、PECVD、MOCVDが挙げられる。
Claims (8)
- 電界効果トランジスタ(FET)であって、
III族窒化物半導体材料で形成された、比抵抗が高い非伝導層(20)と、
III族窒化物半導体材料で形成された、前記非伝導層(20)上のバリア層(18)と、
前記バリア層(18)表面の一部が隣接し、前記バリア層(18)と接触しているソースコンタクト、ドレインコンタクト、ゲートコンタクト(13、14、16)と、
ドープされていない電子ソース層より高い割合のドナー電子(68)を含むようにドープされ、前記ドナー電子により前記FETがマイクロ波の周波数において効率的な利得を生ずることを可能にする、前記コンタクト(13、14、16)の間の前記バリア層(18)表面上の窒化ケイ素(Si x N y )電子ソース層(22)と、を含み、
前記ドナー電子はシリコンを含むドーパントによって供給される、ことを特徴とするFET。
- 前記バリア層(18)がプラスに帯電した表面トラップ(69)を持ち、前記ドナー電子(68)が前記トラップ(69)を中性化し、前記ドナー電子(68)が前記トラップ(69)より高いエネルギー状態を有することを特徴とする請求項1に記載のFET。
- 前記電子ソース層(22)が、電子フィールド(electron field)、電圧または温度の上昇によってひき起こされるストレスのもとで前記バリア層(18)と安定な結合を有することを特徴とする請求項1に記載のFET。
- 前記バリア層(18)の表面が、実質的に損傷がないことを特徴とする請求項1に記載のFET。
- サファイアまたは炭化ケイ素の基板(11)をさらに含み、当該基板(11)は、前記非伝導層(20)に隣接し、前記バリア層(18)の反対側にあることを特徴とする請求項1に記載のFET。
- 前記非伝導層(20)と前記基板(11)との間にバッファ層(12)をさらに含むことを特徴とする請求項5に記載のFET。
- 前記バリア層(38)が、前記非伝導層(34)より幅広のエネルギーバンドギャップを有しており、前記FETが、前記バリア層(38)と前記非伝導層(34)との間に二次元電子ガス(2DEG)(42)をさらに含むことを特徴とする請求項1に記載のFET。
- 請求項1に記載のFETを製造する方法であって、
前記FETをスパッタリングチャンバに配置するステップ(126)と、
前記スパッタリングチャンバ中で前記FET上の前記電子ソース層(108)をスパッタするステップ(128)と、
前記スパッタリングチャンバを冷却しガス抜きするステップ(130)と、
前記スパッタリングチャンバから前記FETを取り出すステップ(130)と、
を含むことを特徴とする方法。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US18043500P | 2000-02-04 | 2000-02-04 | |
US60/180,435 | 2000-02-04 | ||
US09/771,800 US6586781B2 (en) | 2000-02-04 | 2001-01-29 | Group III nitride based FETs and HEMTs with reduced trapping and method for producing the same |
US09/771,800 | 2001-01-29 | ||
PCT/US2001/003433 WO2001057929A1 (en) | 2000-02-04 | 2001-02-01 | Group iii nitride based fets and hemts with reduced trapping and method for producing the same |
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JP2004517461A JP2004517461A (ja) | 2004-06-10 |
JP2004517461A5 JP2004517461A5 (ja) | 2005-01-27 |
JP5313424B2 true JP5313424B2 (ja) | 2013-10-09 |
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JP2001557092A Expired - Lifetime JP5313424B2 (ja) | 2000-02-04 | 2001-02-01 | トラッピング(trapping)を低減させたIII族窒化物ベースの電界効果トランジスタ(FET)およびトランジスタの製造方法 |
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Country | Link |
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US (1) | US6586781B2 (ja) |
EP (1) | EP1261988B1 (ja) |
JP (1) | JP5313424B2 (ja) |
KR (1) | KR100710654B1 (ja) |
CN (1) | CN1260827C (ja) |
AT (1) | ATE525751T1 (ja) |
AU (1) | AU2001233253A1 (ja) |
CA (1) | CA2399547C (ja) |
MY (1) | MY130244A (ja) |
WO (1) | WO2001057929A1 (ja) |
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US6825501B2 (en) * | 1997-08-29 | 2004-11-30 | Cree, Inc. | Robust Group III light emitting diode for high reliability in standard packaging applications |
JP2001284576A (ja) * | 2000-03-30 | 2001-10-12 | Toshiba Corp | 高電子移動度トランジスタ及びその製造方法 |
US7892974B2 (en) * | 2000-04-11 | 2011-02-22 | Cree, Inc. | Method of forming vias in silicon carbide and resulting devices and circuits |
US7125786B2 (en) | 2000-04-11 | 2006-10-24 | Cree, Inc. | Method of forming vias in silicon carbide and resulting devices and circuits |
US6548333B2 (en) | 2000-12-01 | 2003-04-15 | Cree, Inc. | Aluminum gallium nitride/gallium nitride high electron mobility transistors having a gate contact on a gallium nitride based cap segment |
US6649287B2 (en) * | 2000-12-14 | 2003-11-18 | Nitronex Corporation | Gallium nitride materials and methods |
JP3428962B2 (ja) * | 2000-12-19 | 2003-07-22 | 古河電気工業株式会社 | GaN系高移動度トランジスタ |
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KR100710654B1 (ko) | 2007-04-24 |
AU2001233253A1 (en) | 2001-08-14 |
CA2399547A1 (en) | 2001-08-09 |
ATE525751T1 (de) | 2011-10-15 |
WO2001057929A1 (en) | 2001-08-09 |
KR20020082846A (ko) | 2002-10-31 |
EP1261988A1 (en) | 2002-12-04 |
CN1419713A (zh) | 2003-05-21 |
JP2004517461A (ja) | 2004-06-10 |
CA2399547C (en) | 2011-04-19 |
US6586781B2 (en) | 2003-07-01 |
CN1260827C (zh) | 2006-06-21 |
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