JP5294064B2 - 多層セラミック基板およびそれを用いた電子部品並びに多層セラミック基板の製造方法 - Google Patents
多層セラミック基板およびそれを用いた電子部品並びに多層セラミック基板の製造方法 Download PDFInfo
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- JP5294064B2 JP5294064B2 JP2009030288A JP2009030288A JP5294064B2 JP 5294064 B2 JP5294064 B2 JP 5294064B2 JP 2009030288 A JP2009030288 A JP 2009030288A JP 2009030288 A JP2009030288 A JP 2009030288A JP 5294064 B2 JP5294064 B2 JP 5294064B2
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- opening
- cavity
- ceramic substrate
- multilayer ceramic
- green sheet
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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Description
3:第2のセラミックグリーンシート 4:導体 5:第2の開口部
6:第3のセラミックグリーンシート 7、8:圧着部材
9:凹み領域 10:導体層の中央 11:導体層の外縁 12、13:チップ素子
22、23、26:セラミック層 24:導体層 27:マイクロストリップ線路
28:ワイヤ
Claims (5)
- 複数のセラミック層を積層した、キャビティ付きの多層セラミック基板であって、
前記キャビティは底部に導体層を有し、
前記導体層の表面下において、前記導体層の外縁と重なるように又は前記外縁よりも内側に、セラミック層の段差を形成している凹み領域があり、
前記凹み領域はその外縁よりも中央の方が浅いことを特徴とする多層セラミック基板。 - 前記導体層の一部は前記凹み領域の外縁において、セラミック層の下に入りこんでいることを特徴とする請求項1に記載の多層セラミック基板。
- 請求項1または2に記載の多層セラミック基板を用いた電子部品であって、前記キャビティにチップ素子が搭載されていることを特徴とする電子部品。
- 前記凹み領域は前記導体層の外縁よりも内側に形成されており、前記チップ素子は、前記凹み領域を跨ぐように前記キャビティに搭載されていることを特徴とする請求項3に記載の電子部品。
- 複数のセラミック層を積層した、キャビティ付きの多層セラミック基板の製造方法であって、
第1の開口部を有する第1のセラミックグリーンシートを、第2のセラミックグリーンシートの上方に積み重ねる工程と、
積層方向から見て前記第1の開口部を含むように、前記第1のセラミックグリーンシートの、前記第1の開口部よりも大きい領域に導体を印刷する工程と、
前記第1の開口部と開口が同じか、それよりも開口が大きい第2の開口部を有する第3のセラミックグリーンシートを、積層方向から見て、前記第2の開口部が前記第1の開口部を含むように積み重ねる工程と、
積層されたセラミックグリーンシートを圧着する工程と、
圧着されたセラミックグリーンシートを焼成する工程とを有することを特徴とする多層セラミック基板の製造方法。
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JP2009030288A JP5294064B2 (ja) | 2009-02-12 | 2009-02-12 | 多層セラミック基板およびそれを用いた電子部品並びに多層セラミック基板の製造方法 |
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JP2009030288A JP5294064B2 (ja) | 2009-02-12 | 2009-02-12 | 多層セラミック基板およびそれを用いた電子部品並びに多層セラミック基板の製造方法 |
Publications (2)
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JP2010186880A JP2010186880A (ja) | 2010-08-26 |
JP5294064B2 true JP5294064B2 (ja) | 2013-09-18 |
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Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN106815382B (zh) * | 2015-11-30 | 2020-05-19 | 英业达科技有限公司 | 限制区转换方法与限制区转换装置 |
CN112335034A (zh) * | 2018-07-12 | 2021-02-05 | 三菱电机株式会社 | 半导体装置 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4599951B2 (ja) * | 2004-09-14 | 2010-12-15 | 株式会社村田製作所 | セラミック多層基板 |
WO2008126661A1 (ja) * | 2007-04-11 | 2008-10-23 | Murata Manufacturing Co., Ltd. | 多層セラミック基板およびその製造方法 |
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