JP5294064B2 - MULTILAYER CERAMIC SUBSTRATE, ELECTRONIC COMPONENT USING SAME, AND METHOD FOR PRODUCING MULTILAYER CERAMIC SUBSTRATE - Google Patents

MULTILAYER CERAMIC SUBSTRATE, ELECTRONIC COMPONENT USING SAME, AND METHOD FOR PRODUCING MULTILAYER CERAMIC SUBSTRATE Download PDF

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JP5294064B2
JP5294064B2 JP2009030288A JP2009030288A JP5294064B2 JP 5294064 B2 JP5294064 B2 JP 5294064B2 JP 2009030288 A JP2009030288 A JP 2009030288A JP 2009030288 A JP2009030288 A JP 2009030288A JP 5294064 B2 JP5294064 B2 JP 5294064B2
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opening
cavity
ceramic substrate
multilayer ceramic
green sheet
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JP2010186880A (en
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健児 林
初男 池田
馨 神内
昌幸 内田
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Hitachi Metals Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer ceramic substrate, excellent in mass-productivity with respect to the deformation of the cavity in the multilayer ceramic substrate having a cavity: an electronic component using the same: and a method for manufacturing the multilayer ceramic substrate. <P>SOLUTION: In the multilayer ceramic substrate having a cavity in which a plurality of ceramic layers are laminated, the cavity has a conductor layer on its bottom and a recess region having a step difference of the ceramic layer which is formed so as to overlap the outer edge of the conductor layer or inside the outer edge below the surface of the conductor layer, and the recess region is shallower in the center than in the outer edge. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

本発明は、本発明は、複数のセラミック基板を積層した多層セラミック基板およびそれを用いた電子部品並びに多層セラミック基板の製造方法に関する。   The present invention relates to a multilayer ceramic substrate in which a plurality of ceramic substrates are laminated, an electronic component using the multilayer ceramic substrate, and a method for manufacturing the multilayer ceramic substrate.

通信機器などの各種電子機器に用いられる配線基板には、多層セラミック基板が広く用いられている。一般的な多層セラミック基板を用いた電子部品では、複数のセラミック基板層が積層されており、各セラミック基板層の間には配線層が適宜形成され、増幅器やスイッチ回路などの半導体ＩＣや受動チップ部品など、必要なチップ部品はセラミック多層基板上に実装される。前記半導体ＩＣを搭載する場合、機能の高集積化・複合化等のためにキャビティ付きの多層セラミック基板が用いられる。   A multilayer ceramic substrate is widely used as a wiring substrate used in various electronic devices such as communication devices. In an electronic component using a general multilayer ceramic substrate, a plurality of ceramic substrate layers are laminated, and a wiring layer is appropriately formed between each ceramic substrate layer, and a semiconductor IC such as an amplifier or a switch circuit or a passive chip Necessary chip components such as components are mounted on a ceramic multilayer substrate. When the semiconductor IC is mounted, a multilayer ceramic substrate with a cavity is used for high integration / combination of functions.

キャビティ付きの多層セラミック基板のキャビティは、例えば複数のセラミックグリーンシートを積層する際、キャビティに対応する穴の開いたセラミックグリーンシートを表層に配置することで形成される。積層されたセラミックグリーンシート積層体は圧着された後、焼成されて多層セラミック基板が得られるが、圧着の際にキャビティに圧力が逃げるためにセラミックグリーンシートが変形してしまう。その変形の結果、例えばキャビティの深さが設定された値よりも小さくなる。図５（ａ）にはキャビティが変形した多層セラミック基板を用いた電子部品の例を示す。キャビティ底部に位置するセラミック層１７が盛り上がり、キャビティ底部の導体１６上に搭載されたＩＣ１４の高さが、セラミック層１５よりも大幅に高くなっている。すなわち、キャビティ１８の深さが変化することによって、キャビティに実装されるＩＣ１４の高さが大きく変化してしまう。この場合、例えばＩＣと多層セラミック基板側の電極をワイヤボンディングで接続する場合に、ワイヤを長くする必要があるなど、特性変動を生じる。また、キャビティ底の凸形状により実装時にＩＣが傾き、それぞれのワイヤ長がばらつくことにより、特性変動を生じるおそれがある（図５（ｂ））。特に、多層セラミック基板を、準ミリ波帯域（１０ＧＨｚ〜３０ＧＨｚ）やミリ波帯域（３０ＧＨｚ〜３００ＧＨｚ）の高周波信号を取り扱う電子部品に適用する場合、前記特性変動の影響が特に著しく、製品歩留まりの低下に繋がってしまう。   A cavity of a multilayer ceramic substrate with a cavity is formed, for example, by arranging ceramic green sheets with holes corresponding to the cavities on the surface layer when laminating a plurality of ceramic green sheets. The laminated ceramic green sheet laminate is pressure-bonded and then fired to obtain a multilayer ceramic substrate. However, pressure is released to the cavity during the pressure-bonding, so that the ceramic green sheet is deformed. As a result of the deformation, for example, the depth of the cavity becomes smaller than a set value. FIG. 5A shows an example of an electronic component using a multilayer ceramic substrate with a deformed cavity. The ceramic layer 17 located at the bottom of the cavity rises, and the height of the IC 14 mounted on the conductor 16 at the bottom of the cavity is significantly higher than that of the ceramic layer 15. That is, as the depth of the cavity 18 changes, the height of the IC 14 mounted in the cavity changes greatly. In this case, for example, when the IC and the electrode on the multilayer ceramic substrate side are connected by wire bonding, characteristic variation occurs, for example, it is necessary to lengthen the wire. Further, the IC may be inclined at the time of mounting due to the convex shape of the bottom of the cavity, and the respective wire lengths may vary, resulting in characteristic fluctuations (FIG. 5B). In particular, when the multilayer ceramic substrate is applied to an electronic component that handles a high frequency signal in a quasi-millimeter wave band (10 GHz to 30 GHz) or a millimeter wave band (30 GHz to 300 GHz), the influence of the characteristic variation is particularly significant, resulting in a decrease in product yield. It will lead to.

上記キャビティに係る変形の問題に対して、例えば特許文献１には、キャビティ穴と同等かわずかに小さい穴を形成した剛体板と、該剛体板の上に載せた弾性体を介してセラミックグリーンシートを加圧する方法が開示されている。また、特許文献２には、開口部に弾性体を載置して加圧する方法が開示されている。   For example, Patent Document 1 discloses a ceramic green sheet through a rigid plate formed with a hole equal to or slightly smaller than the cavity hole, and an elastic body placed on the rigid plate. A method of pressurizing is disclosed. Patent Document 2 discloses a method of placing and pressing an elastic body in an opening.

特開平６−２２４５５９号公報JP-A-6-224559 特開２００４−２００３３８号公報Japanese Patent Laid-Open No. 2004-200338

しかしながら、特許文献１および２に開示された方法では、複雑な形状の剛体板や弾性体が別途必要となり、生産性やコストなどの量産性の観点から十分なものとは言えなかった。   However, in the methods disclosed in Patent Documents 1 and 2, a rigid plate or an elastic body having a complicated shape is separately required, and it cannot be said that it is sufficient from the viewpoint of mass productivity such as productivity and cost.

そこで、本発明は、上記点に鑑み、量産性に優れた多層セラミック基板およびそれを用いた電子部品並びに多層セラミック基板の製造方法を提供することを目的とする。   In view of the above, the present invention has an object to provide a multilayer ceramic substrate excellent in mass productivity, an electronic component using the same, and a method for manufacturing the multilayer ceramic substrate.

本発明の多層セラミック基板は、複数のセラミック層を積層した、キャビティ付きの多層セラミック基板であって、前記キャビティは底部に導体層を有し、前記導体層の表面下において、前記導体層の外縁と重なるように又は前記外縁よりも内側に、セラミック層の段差を形成している凹み領域があり、前記凹み領域はその外縁よりも中央の方が浅いことを特徴とする。該凹み領域がキャビティ底部の変形の緩衝空間となるため、キャビティ深さが変動することが抑制される。さらに、前記凹み領域を形成すること、および前記凹み領域の中央を浅くすることによって、キャビティ底部の導体の密着性が向上する。これらの構成を採用することで、複雑な形状の剛体板や弾性体を必須としないため、量産性にも優れる。   The multilayer ceramic substrate of the present invention is a multilayer ceramic substrate with a cavity in which a plurality of ceramic layers are laminated, the cavity having a conductor layer at the bottom, and an outer edge of the conductor layer below the surface of the conductor layer. There is a recessed area in which a step of the ceramic layer is formed inside the outer edge so as to overlap with the outer edge, and the recessed area is shallower in the center than the outer edge. Since the recessed region serves as a buffer space for deformation at the bottom of the cavity, fluctuations in the cavity depth are suppressed. Furthermore, the adhesiveness of the conductor at the bottom of the cavity is improved by forming the recessed region and making the center of the recessed region shallow. By adopting these configurations, a rigid plate or elastic body having a complicated shape is not essential, so that mass productivity is excellent.

また、前記多層セラミック基板において、前記導体層の一部は前記凹み領域の外縁において、セラミック層の下に入りこんでいることが好ましい。該構成はキャビティ底部の導体の密着性向上に寄与する。   In the multilayer ceramic substrate, it is preferable that a part of the conductor layer penetrates under the ceramic layer at an outer edge of the recessed region. This configuration contributes to improving the adhesion of the conductor at the bottom of the cavity.

本発明の電子部品は、前記多層セラミック基板を用いた電子部品であって、前記キャビティにチップ素子が搭載されていることを特徴とする。   The electronic component of the present invention is an electronic component using the multilayer ceramic substrate, wherein a chip element is mounted in the cavity.

また、前記電子部品において、前記凹み領域は前記導体層の外縁よりも内側に形成されており、前記チップ素子は、前記凹み領域を跨ぐように前記キャビティに搭載されていることが好ましい。前記凹み領域の周りは変形が少ない領域であるので、かかる領域を用いて、すなわち前記凹み領域を跨ぐようにチップ素子を搭載することで、電子部品におけるチップ素子の高さのばらつきを抑えることができる。   In the electronic component, it is preferable that the recessed area is formed inside an outer edge of the conductor layer, and the chip element is mounted in the cavity so as to straddle the recessed area. Since the area around the recessed area is a region with little deformation, by using such an area, that is, by mounting the chip element so as to straddle the recessed area, it is possible to suppress variation in the height of the chip element in the electronic component. it can.

本発明の多層セラミック基板の製造方法は、複数のセラミック層を積層した、キャビティ付きの多層セラミック基板の製造方法であって、第１の開口部を有する第１のセラミックグリーンシートを、第２のセラミックグリーンシートの上方に積み重ねる工程と、積層方向から見て前記第１の開口部を含むように、前記第１のセラミックグリーンシートの、前記第１の開口部よりも大きい領域に導体を印刷する工程と、前記第１の開口部と開口が同じか、それよりも開口が大きい第２の開口部を有する第３のセラミックグリーンシートを、積層方向から見て、前記第２の開口部が前記第１の開口部を含むように積み重ねる工程と、積層されたセラミックグリーンシートを圧着する工程と、圧着されたセラミックグリーンシートを焼成する工程とを有することを特徴とする。かかる構成によれば、複雑な形状の剛体板や弾性体を必須とせずに、キャビティの高さを制御できるため、量産性にも優れた多層セラミック基板の製造方法を実現することができる。   A method for manufacturing a multilayer ceramic substrate according to the present invention is a method for manufacturing a multilayer ceramic substrate with a cavity, in which a plurality of ceramic layers are laminated, wherein a first ceramic green sheet having a first opening is provided as a second A step of stacking the ceramic green sheets above and printing a conductor in a region larger than the first opening of the first ceramic green sheet so as to include the first opening as viewed from the stacking direction. And when the third ceramic green sheet having a second opening having the same or larger opening than the first opening is viewed from the stacking direction, the second opening is A step of stacking so as to include the first opening, a step of pressure-bonding the laminated ceramic green sheets, and a step of firing the pressure-bonded ceramic green sheets; Characterized in that it has. According to such a configuration, since the height of the cavity can be controlled without requiring a complicated-shaped rigid body plate or elastic body, a method for manufacturing a multilayer ceramic substrate excellent in mass productivity can be realized.

本発明によれば、量産性に優れた多層セラミック基板およびそれを用いた電子部品並びに多層セラミック基板の製造方法を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the multilayer ceramic substrate excellent in mass-productivity, an electronic component using the same, and a multilayer ceramic substrate can be provided.

本発明に係る多層セラミック基板の製造方法の一実施形態を示す図である。It is a figure which shows one Embodiment of the manufacturing method of the multilayer ceramic substrate which concerns on this invention. 本発明に係る多層セラミック基板の実施形態を示す図である。It is a figure which shows embodiment of the multilayer ceramic substrate which concerns on this invention. 本発明に係る電子部品の一実施形態を示す図である。It is a figure which shows one Embodiment of the electronic component which concerns on this invention. 本発明に係る電子部品の他の実施形態を示す図である。It is a figure which shows other embodiment of the electronic component which concerns on this invention. 従来の電子部品の例を示す図である。It is a figure which shows the example of the conventional electronic component.

本発明の多層セラミック基板の製造方法は、複数のセラミック層を積層した、キャビティ付きの多層セラミック基板の製造方法に係る。かかる多層セラミック基板は、本発明に係る構成として特に限定する部分を除き、通常の多層セラミック基板の製造方法を適用して製造することができる。例えば、１０００℃以下で低温焼結が可能なセラミック誘電体材料ＬＴＣＣ（Low Temperature Co-fired Ceramics）からなり、厚さが１０μｍ〜２００μｍのグリーンシートに、低抵抗率のＡｇやＣｕ等の導体ペーストを印刷して所定の電極パターンを形成し、複数のグリーンシートを適宜一体的に積層し、焼結することにより製造することが出来る。前記誘電体材料としては、例えばＡｌ、Ｓｉ、Ｓｒを主成分として、Ｔｉ、Ｂｉ、Ｃｕ、Ｍｎ、Ｎａ、Ｋを副成分とする材料や、Ａｌ、Ｓｉ、Ｓｒを主成分としてＣａ、Ｐｂ、Ｎａ、Ｋを複成分とする材料や、Ａｌ、Ｍｇ、Ｓｉ、Ｇｄを含む材料や、Ａｌ、Ｓｉ、Ｚｒ、Ｍｇを含む材料が用いられ、誘電率は３〜１５程度の材料を用いる。また、前記セラミック基板をＨＴＣＣ（高温同時焼成セラミック）技術を用いて、誘電体材料をＡｌ２Ｏ３を主体とするものとし、伝送線路等をタングステンやモリブデン等の高温で焼結可能な金属導体として構成しても良い。 The method for producing a multilayer ceramic substrate of the present invention relates to a method for producing a multilayer ceramic substrate with a cavity in which a plurality of ceramic layers are laminated. Such a multilayer ceramic substrate can be manufactured by applying an ordinary method for manufacturing a multilayer ceramic substrate, except for a portion that is particularly limited as a configuration according to the present invention. For example, it is made of a ceramic dielectric material LTCC (Low Temperature Co-fired Ceramics) that can be sintered at a low temperature of 1000 ° C. or less. Can be manufactured by forming a predetermined electrode pattern, laminating a plurality of green sheets appropriately and sintering. As the dielectric material, for example, Al, Si, Sr as a main component, Ti, Bi, Cu, Mn, Na, K as a subcomponent, Al, Si, Sr as a main component, Ca, Pb, A material containing Na and K as a composite component, a material containing Al, Mg, Si, and Gd, and a material containing Al, Si, Zr, and Mg are used, and a material having a dielectric constant of about 3 to 15 is used. Further, the ceramic substrate is made of HTCC (high temperature co-fired ceramic) technology, the dielectric material is mainly Al 2 O 3 , and the transmission line is a metal conductor that can be sintered at a high temperature such as tungsten or molybdenum. You may comprise as.

以下、本発明を実施例とともに具体的に説明するが、本発明はこれらの実施例に限定されるものではない。図１に本発明の多層セラミック基板の製造方法の実施形態を、セラミックグリーンシートの積層から圧着までの工程に着目して示す。図１の（ａ）〜（ｄ）はセラミックグリーンシートの積層方向に垂直な方向から見た、開口部における断面図である。まず、第１の開口部１を有する第１のセラミックグリーンシート２を、第２のセラミックグリーンシート３の上方に積み重ねる（工程（ａ））。次に、積層方向から見て第１の開口部１を含むように、第１のセラミックグリーンシート２の、第１の開口部１よりも大きい領域に導体を印刷する（工程（ｂ））。さらに、第１の開口部１と開口が同じか、それよりも開口が大きい第２の開口部５を有する第３のセラミックグリーンシート６を、積層方向から見て、第２の開口部５が第１の開口部１を含むように積み重ねる（工程（ｃ））。その後、積層されたセラミックグリーンシートを圧着する（工程（ｄ））。さらに圧着されたセラミックグリーンシートを焼成する工程を経て多層セラミック基板が得られる。   EXAMPLES Hereinafter, although this invention is demonstrated concretely with an Example, this invention is not limited to these Examples. FIG. 1 shows an embodiment of a method for producing a multilayer ceramic substrate according to the present invention, focusing on the steps from lamination of ceramic green sheets to pressure bonding. (A)-(d) of FIG. 1 is sectional drawing in an opening part seen from the direction perpendicular | vertical to the lamination direction of a ceramic green sheet. First, the first ceramic green sheet 2 having the first opening 1 is stacked above the second ceramic green sheet 3 (step (a)). Next, a conductor is printed in a region larger than the first opening 1 of the first ceramic green sheet 2 so as to include the first opening 1 when viewed from the stacking direction (step (b)). Further, when the third ceramic green sheet 6 having the second opening 5 having the same opening as or larger than the first opening 1 is viewed from the stacking direction, the second opening 5 is Stacking so as to include the first opening 1 (step (c)). Thereafter, the laminated ceramic green sheets are pressure-bonded (step (d)). Further, a multilayer ceramic substrate is obtained through a step of firing the pressed ceramic green sheet.

上記各工程についてさらに詳述する。工程（ａ）において、第１の開口部１は多層セラミック基板のキャビティの位置に対応して形成された開口部である。図１に示すように第１のセラミックグリーンシートは、一層でもよいし、同じ形状の開口部を有する複数のセラミックグリーンシートを開口部が一致するように積層して用いてもよい。または、異なる大きさの開口部を有する複数のセラミックグリーンシートを用いて開口部を階段状に配置してもよい。かかる開口部はメカ式やレーザ式のパンチャを用いて形成すればよい。第１の開口部１は後述する凹み部を形成するためのものである。なお、図１にはキャビティ周辺の一部を示してあるが、セラミックグリーンシートの他の部分にさらにキャビティに対応した開口部を設け、複数のキャビティを形成してもよい。また、図１では、第２のセラミックグリーンシート３として、第１の開口部１との間で有底キャビティを形成するための、第１の開口部１に対応する部分に開口部を有さないセラミックグリーンシートを用いている。但し、第１の開口部１に対応する部分にサーマルビアなどのビアを形成したセラミックグリーンシートを用いることもできる。サーマルビア等のビアの直径は通常１００μｍ〜１５０μｍ程度であるのに対して、チップ素子搭載用キャビティを形成するための開口部は、通常一辺が１ｍｍ以上の矩形である。すなわち、第１および第２の開口部にはサーマルビア等のビアは含まない趣旨である。また、第２のセラミックグリーンシート３は便宜上一層しか図示されていないが、該セラミックグリーンシートは複数層用いることもできる。   The above steps will be further described in detail. In step (a), the first opening 1 is an opening formed corresponding to the position of the cavity of the multilayer ceramic substrate. As shown in FIG. 1, the first ceramic green sheet may be a single layer, or a plurality of ceramic green sheets having openings having the same shape may be laminated so that the openings coincide. Alternatively, the openings may be arranged stepwise using a plurality of ceramic green sheets having openings of different sizes. Such an opening may be formed using a mechanical or laser puncher. The 1st opening part 1 is for forming the dent part mentioned later. Although a part of the periphery of the cavity is shown in FIG. 1, a plurality of cavities may be formed by providing openings corresponding to the cavities in other parts of the ceramic green sheet. Further, in FIG. 1, the second ceramic green sheet 3 has an opening at a portion corresponding to the first opening 1 for forming a bottomed cavity with the first opening 1. There is no ceramic green sheet. However, a ceramic green sheet in which a via such as a thermal via is formed in a portion corresponding to the first opening 1 can also be used. The diameter of a via such as a thermal via is usually about 100 μm to 150 μm, whereas the opening for forming a chip element mounting cavity is usually a rectangle having a side of 1 mm or more. That is, the first and second openings do not include vias such as thermal vias. Further, only one layer of the second ceramic green sheet 3 is shown for convenience, but a plurality of layers of the ceramic green sheet can be used.

工程（ｂ）に関して、図１には積層方向から開口部を見た図を（ｂ’）として示した。図１に示す実施形態では、点線で表された第１の開口部１全体を含むように第１のセラミックグリーンシート全体に渡って導体４が印刷されている。例えば第２のセラミックグリーンシート３上に第１のセラミックグリーンシート２を積層した状態で、導体を印刷して、第１の開口部１への導体充填も行う。前記印刷とは別に、開口部１への導体充填を行ってもよい。なお、導体４は第１の開口部を含むように第１の開口部１よりも大きい領域に対して印刷すればよいので、開口部１に重なる部分以外についてはその形状、大きさを変更することができる。   Regarding the step (b), FIG. 1 shows a view of the opening from the stacking direction as (b ′). In the embodiment shown in FIG. 1, the conductor 4 is printed over the entire first ceramic green sheet so as to include the entire first opening 1 represented by a dotted line. For example, a conductor is printed in a state where the first ceramic green sheet 2 is laminated on the second ceramic green sheet 3, and the conductor is filled into the first opening 1. Separately from the printing, the opening 1 may be filled with a conductor. In addition, since the conductor 4 should just print with respect to the area | region larger than the 1st opening part 1 so that the 1st opening part may be included, the shape and magnitude | size are changed except for the part which overlaps with the opening part 1. be able to.

工程（ｃ）に関して、図１には積層方向から開口部を見た図を（ｃ’）として示した。図１に示す構成では、積層方向から見て、矩形の第２の開口部５の内側に矩形の第１の開口部１（図中点線で表示）が配置されている。図１に示すように第３のセラミックグリーンシートは、一層でもよいし、同じ形状の開口部を有する複数のセラミックグリーンシートを開口部が一致するように積層して用いてもよい。かかる開口部は第１の開口部と同様にメカ式やレーザ式のパンチャを用いて形成すればよい。第２の開口部５が多層セラミック基板のキャビティに対応している。図1に示す構成では、導体４は第２の開口部５よりも広く、第１のセラミックグリーンシート２の全面に渡って形成されているので、積層方向から見て、第２の開口部５の底面全体に渡って、導体が配置されている。但し、上記工程（ｂ）に関して説明したとおり、導体４は、積層方向から見て第１の開口部１を含むように、第１のセラミックグリーンシート２の、第１の開口部１よりも大きい領域に印刷すればよいので、かかる条件を満たす範囲で第２の開口部の底面の一部に導体４が印刷されていない領域があってもよい。また、図１に示す構成では、第２の開口部５の方が第１の開口部１よりも開口が大きいが、第２の開口部５と第１の開口部１の形状および大きさが同じであってもよい。すなわち、第２の開口部が第１の開口部を含むように積み重ねるとは、同じ形状および大きさを有する第２の開口部と第１の開口部とが、その外縁で一致するような場合も含む。また、第１の開口部１と開口が同じか、それよりも開口が大きい第２の開口部５が、積層方向から見て、第１の開口部１を含むように配置されてさえいればよいので、第１の開口部の外縁の一部と第２の開口部の外縁の一部が重なっていてもよい。第２の開口部５が第１の開口部１よりも大きい構成を採用する場合、キャビティ底部の変形量をより小さくする観点からは、第２の開口部５の外縁と第１の開口部１の外縁との差は４００μｍ以下とすることが好ましい。積層ずれなどの工程ばらつきを考慮すると、かかる差は２０〜２００μｍであることがより好ましい。   Regarding step (c), FIG. 1 shows a view of the opening from the stacking direction as (c ′). In the configuration shown in FIG. 1, a rectangular first opening 1 (indicated by a dotted line in the figure) is arranged inside the rectangular second opening 5 when viewed from the stacking direction. As shown in FIG. 1, the third ceramic green sheet may be a single layer, or a plurality of ceramic green sheets having openings having the same shape may be laminated so that the openings coincide. Such an opening may be formed by using a mechanical or laser puncher in the same manner as the first opening. The second opening 5 corresponds to the cavity of the multilayer ceramic substrate. In the configuration shown in FIG. 1, the conductor 4 is wider than the second opening 5 and is formed over the entire surface of the first ceramic green sheet 2, so that the second opening 5 is viewed from the stacking direction. A conductor is disposed over the entire bottom surface of the. However, as described with respect to the step (b), the conductor 4 is larger than the first opening 1 of the first ceramic green sheet 2 so as to include the first opening 1 when viewed from the stacking direction. Since the region may be printed, there may be a region where the conductor 4 is not printed on a part of the bottom surface of the second opening within a range satisfying such a condition. In the configuration shown in FIG. 1, the second opening 5 has a larger opening than the first opening 1, but the shape and size of the second opening 5 and the first opening 1 are the same. It may be the same. That is, stacking so that the second opening includes the first opening means that the second opening and the first opening having the same shape and size coincide with each other at the outer edge. Including. The second opening 5 having the same opening as or larger than the first opening 1 only needs to be arranged so as to include the first opening 1 when viewed from the stacking direction. Since it is good, a part of outer edge of the 1st opening part and a part of outer edge of the 2nd opening part may overlap. When adopting a configuration in which the second opening 5 is larger than the first opening 1, the outer edge of the second opening 5 and the first opening 1 from the viewpoint of reducing the deformation amount of the cavity bottom. The difference from the outer edge is preferably 400 μm or less. In consideration of process variations such as stacking deviation, the difference is more preferably 20 to 200 μm.

また、工程（ｃ）の中で、導体４を形成した第１のセラミックグリーンシート２の上に、第２の開口部５を有する第３のセラミックグリーンシート６を重ねる前に、積層方向から見て、第２の開口部５の外縁を跨ぐように第１のセラミックグリーンシート２の上に誘電体ペーストを配置してもよい。すなわち、積層方向から見て、第２の開口部５の外縁を含むように環状に誘電体ペーストを配置してもよい。かかる誘電体ペーストは、第１のセラミックグリーンシート２と導体４を形成した第３のセラミックグリーンシート６との界面に存在することで、これらの密着性を向上させる。誘電体ペースト配置の構成はこれに限定するものではなく、第２の開口部５の外縁の一部を跨ぐように配置してもよい。また、第２の開口部５の外縁を跨がずに、第１のセラミックグリーンシート２と、第３のセラミックグリーンシート６との界面だけに誘電体ペーストを環状に配置してもよい。かかる場合、第２の開口部５の外縁と環状の誘電体ペーストの内側が一致するようにする。また、この場合、導体４を形成した第１のセラミックグリーンシート２ではなく、第３のセラミックグリーンシート６に誘電体ペーストを配置してもよい。なお、誘電体ペーストには、セラミックグリーンシートと同じ組成のセラミック材料を用いることが好ましい。   In addition, in the step (c), before the third ceramic green sheet 6 having the second opening 5 is overlaid on the first ceramic green sheet 2 on which the conductor 4 is formed, it is viewed from the stacking direction. Thus, a dielectric paste may be disposed on the first ceramic green sheet 2 so as to straddle the outer edge of the second opening 5. That is, the dielectric paste may be arranged in an annular shape so as to include the outer edge of the second opening 5 when viewed from the stacking direction. Such a dielectric paste is present at the interface between the first ceramic green sheet 2 and the third ceramic green sheet 6 on which the conductors 4 are formed, thereby improving their adhesion. The configuration of the dielectric paste arrangement is not limited to this, and the dielectric paste arrangement may be arranged across a part of the outer edge of the second opening 5. Alternatively, the dielectric paste may be arranged in an annular shape only at the interface between the first ceramic green sheet 2 and the third ceramic green sheet 6 without straddling the outer edge of the second opening 5. In such a case, the outer edge of the second opening 5 and the inner side of the annular dielectric paste are made to coincide. In this case, a dielectric paste may be disposed on the third ceramic green sheet 6 instead of the first ceramic green sheet 2 on which the conductor 4 is formed. The dielectric paste is preferably a ceramic material having the same composition as the ceramic green sheet.

積層されたセラミックグリーンシートは、金型、弾性体、フィルム等を用いて構成された圧着部材７、８を介して加圧されて圧着される（工程（ｄ））。さらに圧着されたセラミックグリーンシート（積層体）は、焼成工程を経て多層セラミック基板が得られる。得られた多層セラミック基板のキャビティに半導体ＩＣなどのチップ素子が搭載されて配線基板、積層モジュールなどの電子部品が構成される。工程（ｄ）における加圧による底部の盛り上がりの変形は第１の開口部１および導体４によって吸収され、キャビティ底部の導体から上のキャビティ深さが小さくなることを防ぐことができる。また、第１のセラミックグリーンシートの第１の開口部１の周りの部分は、キャビティを形成する第２の開口部５の外周付近に位置されているために変形が抑えられている。したがって、かかる外周部分を用いて、チップ素子の搭載位置精度の向上を図ることができる。また、上述の開口部を有する第１および第３のセラミックグリーンシートは通常の多層セラミック基板の製造方法と同様の工程および精度で作製することができる。したがって、本実施形態の多層セラミック基板の製造方法は、キャビティの変形を抑制するために、複雑な形状の剛体板や弾性体が必須でないため、キャビティ変形の抑制と量産性との両立に有効である。なお、上記工程（ｂ）を省略した製造方法は、キャビティ変形抑制のための製造方法として、キャビティ底部の導体層の形態を問わずに適用することもできる。この場合、キャビティ底部に形成される段差は、キャビティ変形抑制のために用いられるので、通常の多段キャビティのようにキャビティ内の各段に別個に導体を形成する必要はない。   The laminated ceramic green sheets are pressed and pressure-bonded through pressure-bonding members 7 and 8 formed using a mold, an elastic body, a film, and the like (step (d)). Furthermore, the ceramic green sheet (laminated body) that has been pressure-bonded is subjected to a firing step to obtain a multilayer ceramic substrate. A chip element such as a semiconductor IC is mounted in the cavity of the obtained multilayer ceramic substrate to constitute an electronic component such as a wiring substrate or a laminated module. The deformation of the bulge at the bottom due to the pressurization in the step (d) is absorbed by the first opening 1 and the conductor 4, and the cavity depth above the conductor at the bottom of the cavity can be prevented from being reduced. Moreover, since the part around the 1st opening part 1 of a 1st ceramic green sheet is located in the outer periphery vicinity of the 2nd opening part 5 which forms a cavity, a deformation | transformation is suppressed. Therefore, it is possible to improve the mounting position accuracy of the chip element using the outer peripheral portion. In addition, the first and third ceramic green sheets having the above-described opening can be manufactured with the same process and accuracy as in the method for manufacturing a normal multilayer ceramic substrate. Therefore, the method for manufacturing a multilayer ceramic substrate of the present embodiment is effective in achieving both suppression of cavity deformation and mass productivity because a rigid plate or elastic body having a complicated shape is not essential in order to suppress deformation of the cavity. is there. In addition, the manufacturing method which abbreviate | omitted the said process (b) can also be applied regardless of the form of the conductor layer of a cavity bottom part as a manufacturing method for cavity deformation | transformation suppression. In this case, the step formed at the bottom of the cavity is used to suppress the deformation of the cavity, so that it is not necessary to form a conductor separately at each step in the cavity as in a normal multi-stage cavity.

次に、このようにして得られる多層セラミック基板について説明する。図２（ａ）には本願発明に係る、複数のセラミック層を積層した、キャビティ付きの多層セラミック基板を示す。図２（ａ）はセラミック基板２２、２３、２６を積層した多層セラミック基板のキャビティ部分における断面図である。キャビティ２５は底部に導体層２４を有している。前記導体層２４の表面下において、該導体層２４の外縁よりも内側に、セラミック層の段差を形成している凹み領域９がある。また、かかる凹み領域は上述のように第１のセラミックグリーンシート２の第１の開口部１によって形成されたものである。かかる凹み領域９は外側から中央に向かうにしたがって、盛り上がっているが、凹み領域９の外縁１１よりも中央１０の方が浅くなるようにしてある。導体層２４の表面下に、深さが変化している凹み領域９を設けることによって、導体層の密着性向上が期待できる。かかる凹み領域９を形成することで、キャビティ底部における導体量を増やすことができる。キャビティにＭＭＩＣなど発熱量の大きいチップ素子が搭載される場合、発生する熱をすみやかに放熱することが必要となる。そのため、例えば、チップ素子が搭載されるキャビティ底部の導体層には放熱のためのサーマルビアが接続される。凹み領域９を形成してチップ素子が搭載されるキャビティ底部の導体量を増やすことで放熱能のいっそうの向上を図ることができる。また、凹み領域９の外縁１１よりも中央１０の方が浅くなるようにすることで、凹み部の中央の盛り上がりがチップ素子の高さ変動に影響を与えることを抑制している。なお、図２（ａ）に示す実施形態では、導体層２４はキャビティ２５の底部全体に形成されているが、凹み領域９にかからない部分であれば導体層が形成されていない領域を設けてもよい。また、図２（ａ）に示す実施形態では、導体層はキャビティ底部から連続して多層セラミック基板内部の略全体に渡って形成されているが、必要とされる機能に応じて多層セラミック基板内部の一部に導体層を設けていない構成を採用してもよい。なお、図２（ａ）に示す実施形態では、セラミック層の段差を形成している凹み領域９が、導体層の外縁よりも内側に配置されているが、図２（ｂ）に示すように前記導体層の外縁と重なるように配置、すなわち凹み領域９の外縁とキャビティ底部の外縁が重なるように配置されていてもよい。また、導体層２４の表面下において、導体層の外縁よりも内側に、セラミック層の段差を形成している凹み領域９が配置されてさえいればよいので、キャビティ２５底部の外縁の一部と凹み部９の外縁の一部が重なっていてもよい。   Next, the multilayer ceramic substrate thus obtained will be described. FIG. 2 (a) shows a multilayer ceramic substrate with a cavity in which a plurality of ceramic layers according to the present invention are laminated. FIG. 2A is a cross-sectional view of the cavity portion of the multilayer ceramic substrate in which the ceramic substrates 22, 23, and 26 are laminated. The cavity 25 has a conductor layer 24 at the bottom. Below the surface of the conductor layer 24, there is a recessed region 9 that forms a step in the ceramic layer inside the outer edge of the conductor layer 24. In addition, such a recessed region is formed by the first opening 1 of the first ceramic green sheet 2 as described above. The recessed area 9 rises from the outside toward the center, but the center 10 is shallower than the outer edge 11 of the recessed area 9. By providing the recessed region 9 whose depth is changed below the surface of the conductor layer 24, it is possible to expect an improvement in the adhesion of the conductor layer. By forming the recessed region 9, the amount of conductor at the cavity bottom can be increased. When a chip element with a large calorific value such as MMIC is mounted in the cavity, it is necessary to quickly dissipate the generated heat. Therefore, for example, a thermal via for heat dissipation is connected to the conductor layer at the bottom of the cavity where the chip element is mounted. By forming the recessed region 9 and increasing the amount of conductor at the bottom of the cavity where the chip element is mounted, it is possible to further improve the heat dissipation capability. Further, by making the center 10 shallower than the outer edge 11 of the recessed area 9, it is possible to suppress the rise of the center of the recessed part from affecting the height variation of the chip element. In the embodiment shown in FIG. 2A, the conductor layer 24 is formed over the entire bottom of the cavity 25. However, if the portion does not cover the recessed region 9, a region where no conductor layer is formed may be provided. Good. In the embodiment shown in FIG. 2A, the conductor layer is formed over substantially the entire interior of the multilayer ceramic substrate continuously from the bottom of the cavity, but depending on the required function, A configuration in which a conductor layer is not provided in a part of may be adopted. In the embodiment shown in FIG. 2A, the recessed region 9 forming the step of the ceramic layer is arranged on the inner side of the outer edge of the conductor layer. However, as shown in FIG. It may be arranged so as to overlap with the outer edge of the conductor layer, that is, arranged so that the outer edge of the recessed region 9 and the outer edge of the bottom of the cavity overlap. Further, since it is only necessary that the recessed region 9 forming the step of the ceramic layer is disposed below the outer edge of the conductor layer 24 below the surface of the conductor layer 24, a part of the outer edge of the bottom of the cavity 25 A part of the outer edge of the recess 9 may overlap.

また、図２（ａ）に示す構成では、セラミック層２２のキャビティ側の端部はオーバーハングの状態になっており、導体層２４の一部は前記凹み領域の外縁１１において、セラミック層２２の下に入りこんでいる。但し、セラミック層２２のキャビティ側の端部の形態が、かかる形態に限定されるものではない。例えば図２（ｃ）に示すように、セラミック層２２の断面形状は図２（ａ）の形態の逆であってもよい。但し、セラミック層２２のキャビティ側の端部がオーバーハングの状態になっている図２（ａ）に示す構成によれば、導体層２４の密着性のいっそうの向上が期待できる。セラミック層２２のキャビティ側の端部のかかる構成は、多層セラミック基板を製造する際に、テーパを有する開口部を形成したセラミックグリーンシートを用いたり（その表裏を使い分ける）、開口部に剛体板や弾性体を挿入せずに、加圧の際の圧力を制御することで実現、制御される。   Further, in the configuration shown in FIG. 2A, the cavity-side end of the ceramic layer 22 is in an overhang state, and a part of the conductor layer 24 is formed on the outer edge 11 of the recessed region. I'm in the bottom. However, the form of the end of the ceramic layer 22 on the cavity side is not limited to such form. For example, as shown in FIG. 2C, the cross-sectional shape of the ceramic layer 22 may be the reverse of that shown in FIG. However, according to the configuration shown in FIG. 2A in which the cavity side end of the ceramic layer 22 is in an overhang state, further improvement in the adhesion of the conductor layer 24 can be expected. Such a configuration of the cavity side end of the ceramic layer 22 can be achieved by using a ceramic green sheet having a tapered opening (use different front and back) when manufacturing a multilayer ceramic substrate, It is realized and controlled by controlling the pressure at the time of pressurization without inserting an elastic body.

図３には、図２に示した多層セラミック基板を用いた電子部品の実施形態を示した。かかる電子部品は、キャビティにチップ素子１２としてＭＭＩＣが搭載されている通信モジュール用基板である。図３における実施形態の場合、導体層２２はグランド電極として用いている。図３に示す実施形態では、チップ素子１２は積層方向から見て凹み領域９内に配置されている。搭載した状態で、チップ素子１２の上面が、セラミック層２６の上面と略同一となるようにすればよい。チップ素子１２の上面に形成されたマイクロストリップ線路と裏面側に形成されたグランドとの間隔と、セラミック層２６の上面に形成されたマイクロストリップ線路２７とその下層に形成されたグランドとの間隔とが、略同一となるようにすることが好ましく、かかる観点からチップ素子１２の上面の高さと、セラミック層２６の上面の高さとの間に所定のずれを設定してもよい。チップ素子の端子電極とセラミック層２６に形成した信号線路との接続に必要なワイヤ２８の長さの増加を抑えるため、チップ素子１２の上面と、セラミック層２６の上面の高さが同じになるようにすることが好ましい。凹み領域９は外縁よりも中央の方が浅くなるようにしてあるので、かかる位置にチップ素子１２を配置してもチップ素子の高さがセラミック層２６の高さから大きくずれることが回避できる。なお、電子部品としては、例えば、通信モジュール用基板、アンテナ基板、各種センサ基板などである。但し、本願発明に係る多層セラミック基板はこれに限らず、高周波信号を取り扱う回路を誘電体基板に構成した回路基板等に広く適用できる。また、本願発明に係る多層セラミック基板およびそれを用いた電子部品は、キャビティの寸法精度に優れ、高周波数領域において顕著になるワイヤ接続における特性変動も抑制できることから、特に、準ミリ波帯またはミリ波帯の回路基板等の電子部品に好適である。   FIG. 3 shows an embodiment of an electronic component using the multilayer ceramic substrate shown in FIG. Such an electronic component is a communication module substrate in which an MMIC is mounted as a chip element 12 in a cavity. In the embodiment in FIG. 3, the conductor layer 22 is used as a ground electrode. In the embodiment shown in FIG. 3, the chip element 12 is disposed in the recessed area 9 when viewed from the stacking direction. What is necessary is just to make it the upper surface of the chip element 12 become substantially the same as the upper surface of the ceramic layer 26 in the mounted state. The distance between the microstrip line formed on the upper surface of the chip element 12 and the ground formed on the back surface side, and the distance between the microstrip line 27 formed on the upper surface of the ceramic layer 26 and the ground formed on the lower layer thereof. However, it is preferable that they be substantially the same, and from this viewpoint, a predetermined deviation may be set between the height of the upper surface of the chip element 12 and the height of the upper surface of the ceramic layer 26. In order to suppress an increase in the length of the wire 28 necessary for connection between the terminal electrode of the chip element and the signal line formed in the ceramic layer 26, the height of the upper surface of the chip element 12 and the upper surface of the ceramic layer 26 are the same. It is preferable to do so. Since the center of the recessed area 9 is shallower than the outer edge, even if the chip element 12 is disposed at such a position, the height of the chip element can be prevented from greatly deviating from the height of the ceramic layer 26. Examples of the electronic component include a communication module substrate, an antenna substrate, and various sensor substrates. However, the multilayer ceramic substrate according to the present invention is not limited to this, and can be widely applied to a circuit substrate in which a circuit that handles a high-frequency signal is configured as a dielectric substrate. In addition, the multilayer ceramic substrate and the electronic component using the multilayer ceramic substrate according to the present invention are excellent in dimensional accuracy of the cavity and can suppress fluctuations in characteristics in wire connection that become remarkable in a high frequency region. It is suitable for electronic components such as a waveband circuit board.

図３に示す電子部品では、多層セラミック基板の表面のキャビティにＭＭＩＣが搭載されており、基板の表面の他の部分には、マイクロストリップ線路、電力分配回路、フィルタ回路、部品搭載用端子等（図示せず）が形成されている。また、上述のようにチップ素子１２の表面のマイクロストリップ線路と多層セラミック基板表面のマイクロストリップ線路２７はワイヤ２８により接続されている。半導体素子として、増幅回路、低雑音増幅回路、ミキサ、発振回路等が一つのチップ上に集積され、一体形成されている。これら半導体素子はそれぞれの回路が個別のチップに集積されていても良い。多層セラミック基板上のマイクロストリップ線路は１００μｍ下層の電極をグランドとして構成されている。また、チップ素子１２の基板の厚さは１００μｍであり、該基板の裏面に形成された電極はグランドを構成している。これら２つのグランドはチップ素子を多層セラミック基板のキャビティに半田等で実装することにより、電気的に接続される。この接着層の厚さは１０〜２０μｍ程度あるが、かかる厚さに伴うチップ素子と多層セラミック基板との表面段差は許容範囲である。ここで、使用される線路構造はマイクロストリップ線路に限らず、表面回路型の高周波信号線路であればどの構造を用いても問題ない。なお、チップ素子上の線路と多層セラミック基板上の線路は同構造の線路を利用するのが、伝播モードを変換する必要がなく、低損失となるため好適である。マイクロストリップ線路を構成するグランド電極の下層には各回路への電源供給用ライン、ＩＦ信号用ライン等が形成される。図では単層で形成されているが、当然、必要によって複数層で形成されても良い、また、複数層で形成する場合、ライン構成層間にアイソレーションを向上させるためのシールド電極（グランド電極）を形成しても良い。裏面の搭載端子まではビア構造で接続される。マイクロ波では通常のビア構造で良いが、数１０ＧＨｚで使用する場合、同軸構造を利用することが低損失の観点から望ましい。   In the electronic component shown in FIG. 3, the MMIC is mounted in the cavity on the surface of the multilayer ceramic substrate, and a microstrip line, a power distribution circuit, a filter circuit, a component mounting terminal, etc. ( (Not shown) is formed. Further, as described above, the microstrip line on the surface of the chip element 12 and the microstrip line 27 on the surface of the multilayer ceramic substrate are connected by the wire 28. As a semiconductor element, an amplifier circuit, a low noise amplifier circuit, a mixer, an oscillation circuit, and the like are integrated on a single chip and integrally formed. Each of these semiconductor elements may be integrated on a separate chip. The microstrip line on the multilayer ceramic substrate is configured with the electrode of the lower layer of 100 μm as the ground. Moreover, the thickness of the substrate of the chip element 12 is 100 μm, and the electrode formed on the back surface of the substrate constitutes the ground. These two grounds are electrically connected by mounting the chip element in the cavity of the multilayer ceramic substrate with solder or the like. The thickness of the adhesive layer is about 10 to 20 μm, but the surface step between the chip element and the multilayer ceramic substrate with such thickness is within an allowable range. Here, the line structure used is not limited to the microstrip line, and any structure can be used as long as it is a surface circuit type high-frequency signal line. Note that it is preferable to use a line having the same structure as the line on the chip element and the line on the multilayer ceramic substrate because it is not necessary to convert the propagation mode and the loss is low. A power supply line for each circuit, an IF signal line, and the like are formed below the ground electrode constituting the microstrip line. In the figure, it is formed of a single layer, but of course, it may be formed of a plurality of layers if necessary, and when formed of a plurality of layers, a shield electrode (ground electrode) for improving isolation between the line constituting layers. May be formed. The mounting terminals on the back are connected with a via structure. For microwaves, a normal via structure may be used, but when using at several tens of GHz, it is desirable to use a coaxial structure from the viewpoint of low loss.

図４には、図２に示した多層セラミック基板を用いた電子部品の他の実施形態を示した。かかる電子部品では、チップ素子１３は、凹み領域９を跨ぐようにキャビティに搭載されている。その他の構成は図３に示す実施形態と同様である。チップ素子１３の端部が、凹み領域を囲む、変形が抑えられたセラミック層部分にかかるように配置することで、チップ素子の搭載精度が高くなる。   FIG. 4 shows another embodiment of an electronic component using the multilayer ceramic substrate shown in FIG. In such an electronic component, the chip element 13 is mounted in the cavity so as to straddle the recessed area 9. Other configurations are the same as those of the embodiment shown in FIG. By disposing the end portion of the chip element 13 so as to cover the ceramic layer portion that surrounds the recessed area and is prevented from being deformed, the mounting accuracy of the chip element is increased.

１：第１の開口部 ２：第１のセラミックグリーンシート
３：第２のセラミックグリーンシート ４：導体 ５：第２の開口部
６：第３のセラミックグリーンシート ７、８：圧着部材
９：凹み領域 １０：導体層の中央 １１：導体層の外縁 １２、１３：チップ素子
２２、２３、２６：セラミック層 ２４：導体層 ２７：マイクロストリップ線路
２８：ワイヤ 1: 1st opening part 2: 1st ceramic green sheet 3: 2nd ceramic green sheet 4: Conductor 5: 2nd opening part 6: 3rd ceramic green sheet 7, 8: Crimping member 9: Recess Region 10: Center of conductor layer 11: Outer edge of conductor layer 12, 13: Chip element 22, 23, 26: Ceramic layer 24: Conductor layer 27: Microstrip line 28: Wire

Claims (5)

複数のセラミック層を積層した、キャビティ付きの多層セラミック基板であって、
前記キャビティは底部に導体層を有し、
前記導体層の表面下において、前記導体層の外縁と重なるように又は前記外縁よりも内側に、セラミック層の段差を形成している凹み領域があり、
前記凹み領域はその外縁よりも中央の方が浅いことを特徴とする多層セラミック基板。 A multilayer ceramic substrate with a cavity in which a plurality of ceramic layers are laminated,
The cavity has a conductor layer at the bottom;
Under the surface of the conductor layer, there is a recessed area forming a step of the ceramic layer so as to overlap with the outer edge of the conductor layer or inside the outer edge,
The multilayer ceramic substrate according to claim 1, wherein the recessed region is shallower in the center than in the outer edge. 前記導体層の一部は前記凹み領域の外縁において、セラミック層の下に入りこんでいることを特徴とする請求項１に記載の多層セラミック基板。   2. The multilayer ceramic substrate according to claim 1, wherein a part of the conductor layer penetrates under the ceramic layer at an outer edge of the recessed region. 請求項１または２に記載の多層セラミック基板を用いた電子部品であって、前記キャビティにチップ素子が搭載されていることを特徴とする電子部品。   An electronic component using the multilayer ceramic substrate according to claim 1, wherein a chip element is mounted in the cavity. 前記凹み領域は前記導体層の外縁よりも内側に形成されており、前記チップ素子は、前記凹み領域を跨ぐように前記キャビティに搭載されていることを特徴とする請求項３に記載の電子部品。   4. The electronic component according to claim 3, wherein the recessed area is formed inside an outer edge of the conductor layer, and the chip element is mounted in the cavity so as to straddle the recessed area. . 複数のセラミック層を積層した、キャビティ付きの多層セラミック基板の製造方法であって、
第１の開口部を有する第１のセラミックグリーンシートを、第２のセラミックグリーンシートの上方に積み重ねる工程と、
積層方向から見て前記第１の開口部を含むように、前記第１のセラミックグリーンシートの、前記第１の開口部よりも大きい領域に導体を印刷する工程と、
前記第１の開口部と開口が同じか、それよりも開口が大きい第２の開口部を有する第３のセラミックグリーンシートを、積層方向から見て、前記第２の開口部が前記第１の開口部を含むように積み重ねる工程と、
積層されたセラミックグリーンシートを圧着する工程と、
圧着されたセラミックグリーンシートを焼成する工程とを有することを特徴とする多層セラミック基板の製造方法。 A method of manufacturing a multilayer ceramic substrate with a cavity, in which a plurality of ceramic layers are laminated,
Stacking a first ceramic green sheet having a first opening above a second ceramic green sheet;
Printing a conductor in a region larger than the first opening of the first ceramic green sheet so as to include the first opening when viewed from the stacking direction;
When the third ceramic green sheet having the second opening having the same opening as or larger than the first opening is viewed from the stacking direction, the second opening is the first opening. Stacking to include an opening,
Crimping the laminated ceramic green sheets;
And a step of firing the pressed ceramic green sheet.
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