JP5269317B2 - 調整可能な反射防止コーティングを含む構造およびその形成方法。 - Google Patents
調整可能な反射防止コーティングを含む構造およびその形成方法。 Download PDFInfo
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- JP5269317B2 JP5269317B2 JP2006539479A JP2006539479A JP5269317B2 JP 5269317 B2 JP5269317 B2 JP 5269317B2 JP 2006539479 A JP2006539479 A JP 2006539479A JP 2006539479 A JP2006539479 A JP 2006539479A JP 5269317 B2 JP5269317 B2 JP 5269317B2
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
- H01L2221/1015—Forming openings in dielectrics for dual damascene structures
- H01L2221/1031—Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric
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Description
Claims (32)
- 半導体基板と、
前記半導体基板上に形成され、ハードマスク層および前記ハードマスク層上に構造式R:C:H:Xを有して形成された少なくとも1つの調整可能なエッチング耐性反射防止コーティング(TERA膜)を備えた多層ハードマスクを内部に含む膜スタックとを具備し、
前記Rは、Si、Ge、B、Sn、Fe、Ti、およびそれらの組合せからなる群から選択され、
前記Xは、存在しないかまたはO、N、S、およびFの1つ以上からなる群から選択されており、
前記TERA膜は、膜厚方向に沿って傾斜付けされる屈折率および減衰係数を有しており、
前記膜スタック内に形成される金属配線のためのダマシン構造を更に具備する半導体デバイス。 - 前記調整可能な反射防止コーティングは、前記膜スタックの前記金属配線の形成の間のリソグラフィ構造の一部である請求項1のデバイス。
- 前記調整可能な反射防止コーティングは、前記ダマシン構造のためのケミカルメカニカルポリシング(CMP)のストップ層である請求項1のデバイス。
- 前記調整可能な反射防止コーティングは、シングルハードマスクと、複数の層のハードマスクの上部層と、反射防止コーティングとのうちの少なくとも1つを含んでいる請求項1のデバイス。
- 前記調整可能な反射防止コーティングは、前記膜スタックの光学的性質に実質的に整合する光学的性質を有するように構成されている請求項1のデバイス。
- 前記光学的性質は、屈折率と、減衰係数とのうちの少なくとも一方である請求項5のデバイス。
- 前記屈折率は、1.4から2.6までの範囲の値である請求項6のデバイス。
- 前記減衰係数は、0.01から0.78までの範囲の値である請求項6のデバイス。
- 前記屈折率と、前記減衰係数とのうちの少なくとも一方は、前記調整可能な反射防止コーティングの厚さ方向に沿って傾斜付けされている請求項6のデバイス。
- 前記屈折率は、1.2から2.6までの範囲の値である請求項6のデバイス。
- 前記調整可能な反射防止コーティングは、化学気相成長(CVD)コーティングと、プラズマ増強CVDコーティングとのうちの少なくとも一方である請求項1のデバイス。
- 前記調整可能な反射防止コーティングは、前記シングルダマシン構造の限界寸法の制御と、前記ダマシン構造の限界寸法の変化の制御とのうちの少なくとも一方を提供するように構成されている請求項1のデバイス。
- 前記ダマシン構造は、シングルダマシン構造である請求項1の半導体デバイス。
- 前記ダマシン構造は、デュアルダマシン構造である請求項1の半導体デバイス。
- 前記膜スタックは、low―k誘電体層を更に含んでいる請求項1の半導体デバイス。
- 基板上に誘電体材料層を形成することと、
この誘電体材料層上に多層ハードマスクを形成するようにハードマスク層および前記ハードマスク層上に構造式R:C:H:Xを有して形成された調整可能なエッチング耐性反射防止(TERA)材料の少なくとも1つの層を形成することと、
配線構造と、ハードマスクと、反射防止コーティングと、ケミカルメカニカルポリシング(CMP)のストップ層との形成のためのリソグラフィ構造のうちの少なくとも1つに前記TERA材料の層を使用することにより金属配線のためのデュアルダマシン構造を形成することとを具備し、
前記Rは、Si、Ge、B、Sn、Fe、Ti、およびそれらの組合せからなる群から選択され、
前記Xは、存在しないかまたはO、N、S、およびFの1つ以上からなる群から選択されており、
前記TERA材料の層は、膜厚方向に沿って傾斜付けされる屈折率および減衰係数を有している、集積回路構造を形成するためのプロセス。 - 前記TERA材料の層の上に、前記TERA材料の層の光学的性質と実質的に同じ光学的性質を有する感光材料の層を形成することと、
放射線のパターンに前記感光材料の層を露光させることとを更に具備し、
前記TERA材料の層を前記形成することは、前記放射線のパターンと実質的に同様の前記感光材料の層にパターンを作成するのを容易にする請求項16のプロセス。 - 前記TERA材料の層を前記形成することは、デバイス構造に対する金属配線の形成のためのリソグラフィ構造の一部を提供することを有している請求項17のプロセス。
- 前記TERA材料の層を前記形成することは、化学気相成長(CVD)と、プラズマ増強CVDとのうちの少なくとも一方を使用して前記TERA材料の層を堆積させることを有している請求項17のプロセス。
- ダマシン構造を前記形成することは、シングルダマシン構造で調整可能な反射防止コーティングを集積化することを有している請求項16のプロセス。
- ダマシン構造を前記形成することは、デュアルダマシン構造で調整可能な反射防止コーティングを集積化することを有している請求項16のプロセス。
- ダマシン構造を前記形成することは、ビアファースト方法と、全ビアファースト方法と、ストップ層の無い全ビア方法と、トレンチファースト方法と、埋込みビアマスク方法とのうちの少なくとも1つを有する方法を使用して形成されたデュアルダマシン構造で調整可能な反射防止コーティングを集積化することを有している請求項21のプロセス。
- 金属ラインと、
基板上に形成された金属キャップ層と、
前記金属キャップ層上に形成された第1の誘電体層と、
前記第1の誘電体層上に形成された第2の誘電体層と、
前記誘電体層上に形成されたハードマスク層および前記ハードマスク層上に形成され、構造式R:C:H:Xを有して形成された調整可能なエッチング耐性反射防止(TERA)コーティングを含む多層ハードマスクと、
前記TERAコーティング上に形成された光感応材料の第1の層と、を有する、前記基板を含む膜スタックを準備することと;
前記感光材料の第1の層に第1のパターンを形成することと;
前記第1のパターンを前記TERAコーティングに転写することと;
感光材料の第2の層を前記TERAコーティング上に形成することと;
前記感光材料の第2の層に第2のパターンを形成することと;
前記第2のパターンを前記TERAコーティングに転写すること;
前記第1のパターンを前記ハードマスク層に転写することと;
前記第1のパターンを前記第2の誘電体層に転写すること;
前記第2のパターンを前記ハードマスク層に転写すること;
前記第2のパターンを前記第2の誘電体層に転写すること;
前記第1のパターンを前記第1の誘電体層に転写すること;
前記第1のパターンを前記金属キャップ層に転写することを具備し、
前記Rは、Si、Ge、B、Sn、Fe、Ti、およびそれらの組合せからなる群から選択され、
前記Xは、存在しないかまたはO、N、S、およびFの1つ以上からなる群から選択されており、
前記TERA膜は、膜厚方向に沿って傾斜付けされる屈折率および減衰係数を有している、配線構造を形成する方法。 - 前記感光材料の第1の層を取り除くことを更に具備する請求項23の方法。
- 前記感光材料の第2の層を取り除くことを更に具備する請求項23の方法。
- 前記エッチストップ層上に形成される前記第2の誘電体層の前に、前記第1の誘電体層上に形成されるエッチストップ層を有する前記膜スタックを準備することと;
前記第1のパターンを前記エッチストップ層に転写することとを更に具備する請求項23の方法。 - 前記TERAコーティング上に下部の反射防止コーティング(BARC)層を形成することと;
前記BARC層を取り除くこととを更に具備する請求項23の方法。 - 金属ラインと、
基板上に形成された金属キャップ層と、
前記金属キャップ層上に形成された第1の誘電体層と、
前記第1の誘電体層上に形成された第2の誘電体層と、
前記誘電体層上に形成されたハードマスク層、前記ハードマスク層上に形成された第1の調整可能なエッチング耐性反射防止(TERA)コーティングおよび前記第1のTERAコーティング上に形成された第2のTERAコーティングを含む多層ハードマスクと、
前記TERAコーティング上に形成された光感応材料の第1の層と、を有する、前記基板を含む膜スタックを準備することと;
前記感光材料の第1の層に第1のパターンを形成することと;
前記第1のパターンを前記第2のTERAコーティングに転写することと;
感光材料の第2の層を前記TERAコーティング上に形成することと;
前記感光材料の第2の層に第2のパターンを形成することと;
前記第2のパターンを前記第1のTERAコーティングに転写することと;
前記第2のパターンを前記ハードマスク層に転写することと;
前記第2のパターンを前記第2の誘電体層に転写することと;
前記第2のパターンを前記第1の誘電体層に転写することと;
前記第1のパターンを前記第1のTERAコーティングに転写することと;
前記第1のパターンを前記ハードマスク層に転写することと;
前記第1のパターンを前記第2の誘電体層に転写することと;
前記第2のパターンを前記金属キャップ層に転写することとを具備し、
前記TERAコーティングは、構造式R:C:H:Xを有しており、
前記Rは、Si、Ge、B、Sn、Fe、Ti、およびそれらの組合せからなる群から選択され、
前記Xは、存在しないかまたはO、N、S、およびFの1つ以上からなる群から選択されており、
前記TERAコーティングは、膜厚方向に沿って傾斜付けされる屈折率および減衰係数を有している、配線構造を形成する方法。 - 前記第2のTERAコーティングに前記第1のパターンを前記転写した後に、前記光感応材料の第1の層を取り除くことを更に具備する請求項28の方法。
- 前記第2の誘電体層に前記第2のパターンを前記転写した後に、前記光感応材料の第2の層を取り除くことを更に具備する請求項28または29の方法。
- 前記エッチストップ層上に形成される前記第2の誘電体層の前に、前記第1の誘電体層上に形成されるエッチストップ層を有する前記膜スタックを準備することと;
前記第2のパターンを前記エッチストップ層に転写することとを更に具備する請求項28,29または30の方法。
- 金属ラインと、
基板上に形成された金属キャップ層と、
前記金属キャップ層上に形成された第1の誘電体層と、
前記第1の誘電体層上に形成されたハードマスクおよび前記ハードマスク層上に形成された調整可能なエッチング耐性反射防止(TERA)コーティングを含む第1の多層ハードマスクと、
前記TERAコーティング上に形成された光感応材料の第1の層と、を有する、前記基板を含む膜スタックを準備することと;
前記感光材料の第1の層に第1のパターンを形成することと;
前記第1のパターンを前記TERAコーティングに転写することと;
前記第1のパターンを前記ハードマスク層に転写することと;
前記第1のパターンを前記第1の誘電体層に転写することと;
前記第1のパターンを前記金属キャップ層に転写することと;
前記TERAコーティングを取り除くことと;
前記第1の誘電体層および前記金属キャップ層の前記第1のパターンを金属で埋めることと;
第2の金属キャップ層を前記膜スタック上に形成することと;
第2の誘電体層を前記第2の金属キャップ層上に形成することと;
第2の多層ハードマスクを形成するように第2のハードマスク層を前記第2の誘電体層上に形成し、第2のTERAコーティングを前記第2のハードマスク層上に形成することと;
感光材料の第2の層を前記第2のTERAコーティング上に形成することと;
前記感光材料の第2の層に第2のパターンを形成することと;
前記第2のパターンを前記第2のTERAコーティングに転写することと;
前記第2のパターンを前記第2のハードマスク層に転写することと;
前記第2のパターンを前記第2の誘電体層に転写することと;
前記第2のパターンを前記第2の金属キャップ層に転写することとを具備し、
前記TERAコーティングは、構造式R:C:H:Xを有しており、
前記Rは、Si、Ge、B、Sn、Fe、Ti、およびそれらの組合せからなる群から選択され、
前記Xは、存在しないかまたはO、N、S、およびFの1つ以上からなる群から選択されており、
前記TERAコーティングは、膜厚方向に沿って傾斜付けされる屈折率および減衰係数を有している、配線構造を形成する方法。
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Families Citing this family (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7176571B2 (en) * | 2004-01-08 | 2007-02-13 | Taiwan Semiconductor Manufacturing Company | Nitride barrier layer to prevent metal (Cu) leakage issue in a dual damascene structure |
US7803705B2 (en) * | 2004-01-13 | 2010-09-28 | Tokyo Electron Limited | Manufacturing method of semiconductor device and film deposition system |
US7497959B2 (en) | 2004-05-11 | 2009-03-03 | International Business Machines Corporation | Methods and structures for protecting one area while processing another area on a chip |
US7504727B2 (en) | 2004-05-14 | 2009-03-17 | International Business Machines Corporation | Semiconductor interconnect structure utilizing a porous dielectric material as an etch stop layer between adjacent non-porous dielectric materials |
US20060049139A1 (en) * | 2004-08-26 | 2006-03-09 | Tokyo Electron Limited | Method and system for etching a gate stack |
US7067435B2 (en) * | 2004-09-29 | 2006-06-27 | Texas Instruments Incorporated | Method for etch-stop layer etching during damascene dielectric etching with low polymerization |
JP4357434B2 (ja) * | 2005-02-25 | 2009-11-04 | 株式会社東芝 | 半導体装置の製造方法 |
US7371684B2 (en) * | 2005-05-16 | 2008-05-13 | International Business Machines Corporation | Process for preparing electronics structures using a sacrificial multilayer hardmask scheme |
US7682516B2 (en) * | 2005-10-05 | 2010-03-23 | Lam Research Corporation | Vertical profile fixing |
US7514347B2 (en) * | 2005-10-13 | 2009-04-07 | United Microelectronics Corp. | Interconnect structure and fabricating method thereof |
US7485573B2 (en) * | 2006-02-17 | 2009-02-03 | International Business Machines Corporation | Process of making a semiconductor device using multiple antireflective materials |
US20070205507A1 (en) * | 2006-03-01 | 2007-09-06 | Hui-Lin Chang | Carbon and nitrogen based cap materials for metal hard mask scheme |
US20070218681A1 (en) * | 2006-03-16 | 2007-09-20 | Tokyo Electron Limited | Plasma etching method and computer-readable storage medium |
KR100781422B1 (ko) * | 2006-05-24 | 2007-12-03 | 동부일렉트로닉스 주식회사 | 듀얼 다마신 패턴 형성 방법 |
US7781332B2 (en) * | 2007-09-19 | 2010-08-24 | International Business Machines Corporation | Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer |
US8618663B2 (en) | 2007-09-20 | 2013-12-31 | International Business Machines Corporation | Patternable dielectric film structure with improved lithography and method of fabricating same |
DE102007052048A1 (de) * | 2007-10-31 | 2009-05-14 | Advanced Micro Devices, Inc., Sunnyvale | Doppelintegrationsschema für Metallschicht mit geringem Widerstand |
KR100907890B1 (ko) * | 2007-12-03 | 2009-07-15 | 주식회사 동부하이텍 | 반도체 소자의 제조 방법 |
US8003522B2 (en) * | 2007-12-19 | 2011-08-23 | Fairchild Semiconductor Corporation | Method for forming trenches with wide upper portion and narrow lower portion |
EP2306498A1 (en) * | 2008-06-17 | 2011-04-06 | Ulvac, Inc. | Method for manufacturing multistep substrate |
US8597531B2 (en) * | 2009-04-02 | 2013-12-03 | Infineon Technologies Ag | Method for manufacturing a device on a substrate |
US20110151222A1 (en) * | 2009-12-22 | 2011-06-23 | Agc Flat Glass North America, Inc. | Anti-reflective coatings and methods of making the same |
US8896120B2 (en) * | 2010-04-27 | 2014-11-25 | International Business Machines Corporation | Structures and methods for air gap integration |
US8298954B1 (en) * | 2011-05-06 | 2012-10-30 | International Business Machines Corporation | Sidewall image transfer process employing a cap material layer for a metal nitride layer |
JP6096470B2 (ja) * | 2012-10-29 | 2017-03-15 | 東京エレクトロン株式会社 | プラズマ処理方法及びプラズマ処理装置 |
JP6132525B2 (ja) | 2012-11-30 | 2017-05-24 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
WO2014134124A1 (en) * | 2013-03-01 | 2014-09-04 | Kleptsyn Vladimir | Anti-reflective coating |
US8809185B1 (en) * | 2013-07-29 | 2014-08-19 | Tokyo Electron Limited | Dry etching method for metallization pattern profiling |
CN108122822B (zh) * | 2016-11-29 | 2021-04-23 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的制备方法 |
JP6945385B2 (ja) * | 2017-08-14 | 2021-10-06 | 東京エレクトロン株式会社 | プラズマ処理方法及びプラズマ処理装置 |
CN110718506A (zh) * | 2019-09-30 | 2020-01-21 | 上海华力集成电路制造有限公司 | 一种制作14nm节点后段制程32nm线宽金属的方法 |
CN113161284A (zh) * | 2020-01-07 | 2021-07-23 | 台湾积体电路制造股份有限公司 | 用于制造互连结构的方法 |
WO2021173421A1 (en) * | 2020-02-25 | 2021-09-02 | Tokyo Electron Limited | Dielectric etch stop layer for reactive ion etch (rie) lag reduction and chamfer corner protection |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6117619A (en) * | 1998-01-05 | 2000-09-12 | Micron Technology, Inc. | Low temperature anti-reflective coating for IC lithography |
TW392324B (en) * | 1998-01-23 | 2000-06-01 | United Microelectronics Corp | Dual damascene process |
US6316167B1 (en) * | 2000-01-10 | 2001-11-13 | International Business Machines Corporation | Tunabale vapor deposited materials as antireflective coatings, hardmasks and as combined antireflective coating/hardmasks and methods of fabrication thereof and application thereof |
US6284149B1 (en) * | 1998-09-18 | 2001-09-04 | Applied Materials, Inc. | High-density plasma etching of carbon-based low-k materials in a integrated circuit |
JP2001068455A (ja) * | 1999-08-30 | 2001-03-16 | Hitachi Ltd | 半導体装置の製造方法 |
JP2001077196A (ja) * | 1999-09-08 | 2001-03-23 | Sony Corp | 半導体装置の製造方法 |
US20010051420A1 (en) * | 2000-01-19 | 2001-12-13 | Besser Paul R. | Dielectric formation to seal porosity of low dielectic constant (low k) materials after etch |
JP2002093778A (ja) * | 2000-09-11 | 2002-03-29 | Toshiba Corp | 有機膜のエッチング方法およびこれを用いた半導体装置の製造方法 |
US6441491B1 (en) * | 2000-10-25 | 2002-08-27 | International Business Machines Corporation | Ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device and electronic device containing the same |
US6500773B1 (en) * | 2000-11-27 | 2002-12-31 | Applied Materials, Inc. | Method of depositing organosilicate layers |
WO2002054484A2 (en) * | 2001-01-03 | 2002-07-11 | Dow Corning Corporation | Metal ion diffusion barrier layers |
US6309955B1 (en) * | 2001-02-16 | 2001-10-30 | Advanced Micro Devices, Inc. | Method for using a CVD organic barc as a hard mask during via etch |
JP2002252222A (ja) * | 2001-02-22 | 2002-09-06 | Nec Corp | 半導体装置の製造方法、及び半導体装置 |
US6486059B2 (en) * | 2001-04-19 | 2002-11-26 | Silicon Intergrated Systems Corp. | Dual damascene process using an oxide liner for a dielectric barrier layer |
US6777171B2 (en) * | 2001-04-20 | 2004-08-17 | Applied Materials, Inc. | Fluorine-containing layers for damascene structures |
US6620727B2 (en) * | 2001-08-23 | 2003-09-16 | Texas Instruments Incorporated | Aluminum hardmask for dielectric etch |
JP4085648B2 (ja) * | 2002-02-22 | 2008-05-14 | ソニー株式会社 | 半導体装置の製造方法 |
US7105460B2 (en) * | 2002-07-11 | 2006-09-12 | Applied Materials | Nitrogen-free dielectric anti-reflective coating and hardmask |
US6903023B2 (en) * | 2002-09-16 | 2005-06-07 | International Business Machines Corporation | In-situ plasma etch for TERA hard mask materials |
US6803313B2 (en) * | 2002-09-27 | 2004-10-12 | Advanced Micro Devices, Inc. | Method for forming a hardmask employing multiple independently formed layers of a pecvd material to reduce pinholes |
US6853043B2 (en) * | 2002-11-04 | 2005-02-08 | Applied Materials, Inc. | Nitrogen-free antireflective coating for use with photolithographic patterning |
US6917108B2 (en) * | 2002-11-14 | 2005-07-12 | International Business Machines Corporation | Reliable low-k interconnect structure with hybrid dielectric |
US6869542B2 (en) * | 2003-03-12 | 2005-03-22 | International Business Machines Corporation | Hard mask integrated etch process for patterning of silicon oxide and other dielectric materials |
US20050062164A1 (en) * | 2003-09-23 | 2005-03-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for improving time dependent dielectric breakdown lifetimes |
US7553769B2 (en) * | 2003-10-10 | 2009-06-30 | Tokyo Electron Limited | Method for treating a dielectric film |
US7611758B2 (en) * | 2003-11-06 | 2009-11-03 | Tokyo Electron Limited | Method of improving post-develop photoresist profile on a deposited dielectric film |
-
2003
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2004
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JP2007511906A (ja) | 2007-05-10 |
KR101044984B1 (ko) | 2011-06-29 |
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US20050230677A1 (en) | 2005-10-20 |
US20050104150A1 (en) | 2005-05-19 |
TWI307544B (en) | 2009-03-11 |
KR20070005912A (ko) | 2007-01-10 |
US7199046B2 (en) | 2007-04-03 |
WO2005053011A1 (en) | 2005-06-09 |
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