CN110718506A - 一种制作14nm节点后段制程32nm线宽金属的方法 - Google Patents

一种制作14nm节点后段制程32nm线宽金属的方法 Download PDF

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CN110718506A
CN110718506A CN201910938330.8A CN201910938330A CN110718506A CN 110718506 A CN110718506 A CN 110718506A CN 201910938330 A CN201910938330 A CN 201910938330A CN 110718506 A CN110718506 A CN 110718506A
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毛永吉
叶荣鸿
刘立尧
张瑜
胡展源
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Abstract

本发明提供一种制作14nm节点后段制程32nm线宽金属的方法，提供用于制作后段金属线的半导体结构，该半导体结构至少包括碳涂层以及位于碳涂层上的中间层；在中间层上形成光阻层并按照版图对所述光阻层进行曝光；利用显影液对曝光后的光阻层进行显影，显影后的光阻与其接触区的所述中间层反应，形成上窄下宽的凹槽；利用位于半导体结构上的凹槽刻蚀形成14nm节点后段制程32nm线宽金属。本发明利用改性底部抗反射层成分使其能与显影后的光阻接触区域反应，形成光阻底部内凹结构，从而减小金属线纵向的收缩，达到横纵收缩均匀性提升，减小通孔与金属线错位的缺陷并且增大芯片有效使用面积。

Description

一种制作14nm节点后段制程32nm线宽金属的方法
技术领域
本发明涉及半导体制造领域，特别是涉及一种制作14nm节点后段制程32nm线宽金属的方法。
背景技术
由于193nm DUV光刻技术无法满足14nm、10nm和7nm节点技术所需的精细节距图案，因此开发了双图案化技术以实现精细节距图案化。14nm节点后段BEOL金属线版图设计规则为节距64nm，采用双图案化方法，曝光关键尺寸CD保持为53nm，通过金属硬掩膜刻蚀将CD缩小到30nm。通过2个掩模完成双图案，达到64nm节距的金属线。
14nm技术节点，64nm节距(线宽32nm，线宽距离32nm)的后段金属缩小CD(关键尺寸)的制程如下：如图1a至图1c所示，图1a中提供碳涂层03及位于该碳涂层03上的中间层02，在所述碳涂层03下设有在层叠结构04，经过曝光和显影，光阻01显影后的凹槽宽度为53nm；如图1b所示，之后刻蚀底部抗反射图层SHB(中间层02)，形成该SHB的底部宽度为32nm，其顶部宽度与光阻显影后的宽度53nm一致；如图1c所示，接着按照32nm的宽度刻蚀层叠结构形成缩小后的CD宽度。
如图2a所述，现有技术中14nm节点后段缩小CD后的金属线在横向(1D)和纵向(2D)方向上形成不同程度的收缩；参阅图2b，实验结果显示，1D与2D的比值约为0.63，意味着金属线横向(1D)缩小1nm，将会导致金属线在纵向(2D)上缩小1.56nm。由此可见，横向和纵向收缩程度的巨大差距将会导致金属线与通孔的错位(如图3所示)。尽管可以通过OPC(光学邻近修正)技术进行补偿，但是由于芯片面积的局限性给OPC技术带来了挑战。
因此，需要提出一种新的方法来解决上述问题。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种制作14nm节点后段制程32nm线宽金属的方法，用于解决现有技术中14nm节点后段缩小CD后的金属线在横向和纵向上形成不同程度的收缩，导致金属线与通孔错位带来缺陷的问题。
为实现上述目的及其他相关目的，本发明提供一种制作14nm节点后段制程32nm线宽金属的方法，该方法至少包括以下步骤：步骤一、提供用于制作后段金属线的半导体结构，该半导体结构至少包括碳涂层以及位于所述碳涂层上的中间层；步骤二、在所述中间层上形成光阻层并按照版图对所述光阻层进行曝光；步骤三、利用显影液对曝光后的所述光阻层进行显影，显影后的光阻与其接触区的所述中间层反应，形成上窄下宽的凹槽；步骤四、利用位于所述半导体结构上的所述凹槽刻蚀形成14nm节点后段制程32nm线宽金属。
优选地，所述半导体结构包括位于所述碳涂层下的层叠结构。
优选地，所述层叠结构自下而上依次为：含碳氮化硅层、第一无氮抗反射涂层、TiN层、第二无氮抗反射涂层。
优选地，步骤一中所述碳涂层的厚度为1800埃。
优选地，步骤一中所述中间层为底部抗反射层。
优选地，所述底部抗反射层的厚度为330埃。
优选地，步骤二中在所述中间层上形成的光阻层厚度为750埃。
优选地，所述层叠结构中的所述含碳氮化硅层厚度为100埃。
优选地，所述层叠结构中的所述第一无氮抗反射涂层的厚度为200埃。
优选地，所述层叠结构中的所述TiN层的厚度为250埃。
优选地，所述层叠结构中的所述第二无氮抗反射涂层的厚度为400埃。
优选地，步骤三中形成的所述上窄下宽的凹槽，其中窄的一部分宽度为53nm，宽的一部分宽度为59nm。
优选地，步骤四中利用位于所述半导体结构上的所述凹槽刻蚀形成14nm节点后段制程32nm线宽金属的方法至少包括：(a)按照所述中间层底部的宽度刻蚀所述中间层，暴露出所述碳涂层的宽度为32nm；(b)沿所述暴露出的碳涂层刻蚀所述层叠结构，形成32nm的凹槽。
如上所述，本发明的制作14nm节点后段制程32nm线宽金属的方法，具有以下有益效果：本发明利用改性底部抗反射层(BARC)成分使其能与显影后的光阻接触区域反应，形成光阻底部内凹结构，从而减小金属线纵向(2D)的收缩，达到1D/2D收缩均匀性提升，减小通孔与金属线错位的缺陷并且增大芯片有效使用面积。
附图说明
图1a和图1c显示为现有技术中14nm节点后段金属收缩的工艺流程示意图；
图1d显示为现有技术中14nm节点后段制程32nm线宽金属在横纵方向的收缩示意图；
图2a显示为现有技术中的14nm节点后段金属在1D、2D方向的不同程度的收缩示意图；
图2b显示为现有技术中14nm节点后段金属收缩的1D/2D线性关系图；
图3显示为现有技术中14nm节点后段金属在1D、2D方向上的不同收缩导致与通孔错位的示意图；
图4和图5a显示为本发明中制作14nm节点后段金属的工艺结构示意图；
图5b显示为本发明的光阻刻蚀形成的上宽下窄的凹槽的平面尺寸示意图；
图5c显示为采用本发明的方法形成的14nm节点后段制程32nm线宽金属在横纵方向的收缩示意图；
图6显示为采用本发明的方法制作的14nm节点后段金属的电子显微镜图；
图7显示为分别采用本发明的方法和现有技术的方法制作14nm节点后段金属在1D和2D方向上的收缩对比示意图；
图8显示为本发明中制作14nm节点后段制程32nm线宽金属的方法流程图。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图4至图8。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
一种制作14nm节点后段制程32nm线宽金属的方法，如图8所示，图8显示为本发明中制作14nm节点后段制程32nm线宽金属的方法流程图。该方法至少包括以下步骤：
步骤一、提供用于制作后段金属线的半导体结构，如图4所示，图4显示为本发明中制作14nm节点后段金属的工艺结构示意图，该半导体结构至少包括碳涂层(Spin OnCarbon，SOC)03以及位于所述碳涂层03上的中间层(SHB)02；本发明中位于所述碳涂层03上的中间层02的作用是为其上面的光阻01提供底部抗反射层。
本发明进一步地，步骤一中所述半导体结构包括位于所述碳涂层下的层叠结构。图4及图5a中未示出所述层叠结构，可参阅图1a至图1c中位于所述碳涂层03下的层叠结构04。本发明进一步地，步骤一中所述碳涂层03的厚度为1800埃。所述中间层02为底部抗反射层。本实施例中，所述底部抗反射层(中间层02)的厚度为330埃。
本发明更进一步地，步骤一中所述层叠结构自下而上依次为：含碳氮化硅层、第一无氮抗反射涂层(NFDARC)、TiN层、第二无氮抗反射涂层(NFDARC)。亦即位于所述碳涂层03下的层叠结构由含碳氮化硅层、第一无氮抗反射涂层(NFDARC)、TiN层、第二无氮抗反射涂层(NFDARC)构成，并且所述第二无氮抗反射涂层(NFDARC)与所述碳涂层03相邻，本实施例中所述层叠结构中的所述含碳氮化硅层厚度为100埃。
本发明优选地，所述层叠结构中的所述第二无氮抗反射涂层(NFDARC)的厚度为400埃。位于所述第二无氮抗反射涂层(NFDARC)下表面的是所述TiN层，本实施例中，该TiN层的厚度为250埃。在所述250埃厚度的TiN层下表面是所述第一无氮抗反射涂层(NFDARC)，本发明进一步地，所述层叠结构中的所述第一无氮抗反射涂层(NFDARC)的厚度为200埃。
步骤二、在所述中间层上形成光阻层并按照版图对所述光阻层进行曝光；参阅图4，图4显示为本发明中制作14nm节点后段金属的工艺结构示意图，在所述中间层02(底部抗反射层)上悬涂光刻胶，形成光阻层01，并对所述光阻层01按照光罩图形进行曝光。
本发明进一步地，步骤二中在所述中间层(SHB)02上形成的光阻层厚度为750埃。
步骤三、利用显影液对曝光后的所述光阻层进行显影，显影后的光阻与其接触区的所述中间层反应，形成上窄下宽的凹槽；本发明的所述中间层02是将现有技术中的BARC改性后形成的特殊性质的光刻防反射层，改性BARC分成使其能与显影后的光阻(BARC与光阻的接触区)反应，形成光阻底部内凹结构，如图5a所示，图5a显示的是光阻01与所述中间层02接触区(光阻01底部)形成内凹结构的示意图，图4显示的光阻01已经显影，还没有形成光阻内凹结构。本发明进一步地，如图5a所示，步骤三中形成的所述上窄下宽的凹槽，其中窄的一部分宽度为53nm，宽的一部分宽度为59nm。如图5b所示，图5b显示的是本发明的光阻刻蚀形成的上宽下窄的凹槽的平面尺寸示意图；所形成的凹槽的窄的部分其横纵方向各比宽的部分少3nm。
该步骤利用该特殊性质的中间层(底部抗反射层)形成所述内凹的光阻结构，目的是能够使得后续形成的14nm节点后段的32nm线宽的金属在横向(1D)和纵向(2D)的收缩(shrink)程度达到一致。从而减小通孔与金属的错位缺陷，并增大芯片有效使用面积。
步骤四、利用位于所述半导体结构上的所述凹槽刻蚀形成14nm节点后段制程32nm线宽金属。本发明进一步地，步骤四中利用位于所述半导体结构上的所述凹槽刻蚀形成14nm节点后段制程32nm线宽金属的方法至少包括：(a)按照所述中间层底部的宽度刻蚀所述中间层，暴露出所述碳涂层的宽度为32nm；(b)沿所述暴露出的碳涂层刻蚀所述层叠结构，形成32nm的凹槽。
14nm节点后段制程32nm线宽金属的过程中，在进行等离子体刻蚀时，金属线的末端受到三个方向上的多晶硅的轰击，导致金属线的纵向(2D)收缩比横向(1D)收缩严重，而采用本发明的方法，在步骤四中将光阻底部拓宽，用以弥补后续刻蚀导致的金属线在纵向的收缩，使得横向(1D)和纵向(2D)的收缩比达到基本一致，如图5c所示，图5c显示的是采用本发明的方法形成的14nm节点后段制程32nm线宽金属在横纵方向的收缩示意图，而图1d显示的是现有技术中14nm节点后段制程32nm线宽金属在横纵方向的收缩示意图；二者比较可以看出，本发明的方法得到的32nm线宽金属在横纵方向的收缩一致，都为10.5nm，而现有技术得到的32nm线宽金属在横向(1D)左右的收缩都为10.5nm，纵向(2D)左右的收缩都为16.5nm，因此采用本发明的方法可以改善金属线和通孔的错位问题。
如图6所示，图6显示为采用本发明的方法制作的14nm节点后段金属的电子显微镜图。再如图7所示，图7显示为分别采用本发明的方法和现有技术的方法制作14nm节点后段金属在1D和2D方向上的收缩对比示意图。图7左侧的柱状图为现有技术中14nm节点后段金属在横向(1D)和纵向(2D)收缩的比较，图7右侧的柱状图为采用本发明的方法制作14nm节点后段金属在横向(1D)和纵向(2D)收缩的比较，经对比发现采用本发明的方法制作14nm节点后段金属，其横向和纵向的收缩一致。
综上所述，本发明利用改性底部抗反射层(BARC)成分使其能与显影后的光阻接触区域反应，形成光阻底部内凹结构，从而减小金属线纵向(2D)的收缩，达到1D/2D收缩均匀性提升，减小通孔与金属线错位的缺陷并且增大芯片有效使用面积。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (13)

1.一种制作14nm节点后段制程32nm线宽金属的方法，其特征在于，该方法至少包括以下步骤：
步骤一、提供用于制作后段金属线的半导体结构，该半导体结构至少包括碳涂层以及位于所述碳涂层上的中间层；
步骤二、在所述中间层上形成光阻层并按照版图对所述光阻层进行曝光；
步骤三、利用显影液对曝光后的所述光阻层进行显影，显影后的光阻与其接触区的所述中间层反应，形成上窄下宽的凹槽；
步骤四、利用位于所述半导体结构上的所述凹槽刻蚀形成14nm节点后段制程32nm线宽金属。
2.根据权利要求1所述的制作14nm节点后段制程32nm线宽金属的方法，其特征在于：步骤一中所述半导体结构包括位于所述碳涂层下的层叠结构。
3.根据权利要求2所述的制作14nm节点后段制程32nm线宽金属的方法，其特征在于：步骤一中所述层叠结构自下而上依次为：含碳氮化硅层、第一无氮抗反射涂层、TiN层、第二无氮抗反射涂层。
4.根据权利要求3所述的制作14nm节点后段制程32nm线宽金属的方法，其特征在于：步骤一中所述碳涂层的厚度为1800埃。
5.根据权利要求1所述的制作14nm节点后段制程32nm线宽金属的方法，其特征在于：步骤一中所述中间层为底部抗反射层。
6.根据权利要求5所述的制作14nm节点后段制程32nm线宽金属的方法，其特征在于：所述底部抗反射层的厚度为330埃。
7.根据权利要求1所述的制作14nm节点后段制程32nm线宽金属的方法，其特征在于：步骤二中在所述中间层上形成的光阻层厚度为750埃。
8.根据权利要求3所述的制作14nm节点后段制程32nm线宽金属的方法，其特征在于：所述层叠结构中的所述含碳氮化硅层厚度为100埃。
9.根据权利要求3所述的制作14nm节点后段制程32nm线宽金属的方法，其特征在于：所述层叠结构中的所述第一无氮抗反射涂层的厚度为200埃。
10.根据权利要求3所述的制作14nm节点后段制程32nm线宽金属的方法，其特征在于：所述层叠结构中的所述TiN层的厚度为250埃。
11.根据权利要求3所述的制作14nm节点后段制程32nm线宽金属的方法，其特征在于：所述层叠结构中的所述第二无氮抗反射涂层的厚度为400埃。
12.根据权利要求3所述的制作14nm节点后段制程32nm线宽金属的方法，其特征在于：步骤三中形成的所述上窄下宽的凹槽，其中窄的一部分宽度为53nm，宽的一部分宽度为59nm。
13.根据权利要求12所述的制作14nm节点后段制程32nm线宽金属的方法，其特征在于：步骤四中利用位于所述半导体结构上的所述凹槽刻蚀形成14nm节点后段制程32nm线宽金属的方法至少包括：(a)按照所述中间层底部的宽度刻蚀所述中间层，暴露出所述碳涂层的宽度为32nm；(b)沿所述暴露出的碳涂层刻蚀所述层叠结构，形成32nm的凹槽。
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