JP5261888B2 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
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- JP5261888B2 JP5261888B2 JP2006139055A JP2006139055A JP5261888B2 JP 5261888 B2 JP5261888 B2 JP 5261888B2 JP 2006139055 A JP2006139055 A JP 2006139055A JP 2006139055 A JP2006139055 A JP 2006139055A JP 5261888 B2 JP5261888 B2 JP 5261888B2
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4067—Refresh in standby or low power modes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Dram (AREA)
- Dc-Dc Converters (AREA)
Description
最後に、/RAS=L、/CAS=H、/WE=Lのプリチャージコマンドによりコアが非活性化される。即ち、wlzがLOWとなり、ワード線WLが非活性化される。次にwlzのLOWに応答してsaezがLOWとなり、センスアンプが非活性化される。更にsaezのLOWに応答してrrzがLOWとなり、ブロック選択が解除される。そしてrrzのLOWに応答してwritezがLOWとなり、書き込みコマンドのコア動作が終了する。raszのLOWに応答して、powactzがLOWとなり、電源回路104はスタンバイ状態に戻る。
11 コア制御回路
12 メモリコア回路
13 状態検出回路
14 電源回路
15 入出力バッファ
31 パルス発生回路
32 遅延回路
100 半導体記憶装置
101 コア制御回路
102 メモリコア回路
103 状態検出回路
104 電源回路
105 入出力バッファ
131 パルス発生回路
132 遅延回路
Claims (7)
- ワード線を含むDRAMメモリコア回路と、
第1の状態と第2の状態との何れか選択された一方において動作することにより所定の電源電圧を生成して該DRAMメモリコア回路に供給し、前記第1の状態と前記第2の状態との両方において前記電源電圧の低下を検出すると前記電源電圧を上昇させ、該第2の状態においてよりも該第1の状態においての方がより大きな電流を消費する電源回路と、
該DRAMメモリコア回路の該ワード線が活性化されてから非活性化されるまでの期間において、該DRAMメモリコア回路のセンスアンプを活性化するセンスアンプ活性化信号のアサートから所定の遅延時間後に該電源回路を該第1の状態から該第2の状態に移行させ、ライトイネーブル信号のデアサートに応答して該第1の状態に戻すように該電源回路を制御する制御回路
を含むことを特徴とする半導体記憶装置。 - 該半導体記憶装置はSRAM互換の入出力インターフェースを有し、該制御回路は、書き込み動作において該DRAMメモリコア回路の該ワード線が活性化されてから非活性化されるまでの期間に該電源回路を該第1の状態から該第2の状態に移行させ更に該第1の状態に戻すように該電源回路を制御するとともに、読み出し動作及びリフレッシュ動作において該DRAMメモリコア回路の該ワード線が活性化されてから非活性化されるまでの期間に該電源回路が該第1の状態に保たれるように該電源回路を制御することを特徴とする請求項1記載の半導体記憶装置。
- 該電源回路は該第2の状態においてよりも該第1の状態においての方が該電源電圧の変動に対してより迅速に応答して該電源電圧をより迅速に所定値に回復するよう構成されることを特徴とする請求項1記載の半導体記憶装置。
- 該電源回路は、
該電源電圧のレベルに応答して出力を変化させる検出回路と、
該検出回路の出力に応答して発振信号を出力するオシレータ回路と、
該オシレータ回路の発振信号に応じて該電源電圧を生成するポンプ回路
を含み、該検出回路は該第2の状態においてよりも該第1の状態においての方がより大きな電流を消費すると共に応答速度がより速く、該オシレータ回路は該第2の状態においてよりも該第1の状態においての方がより大きな電流を消費すると共に該発振信号の発振周期がより短いことを特徴とする請求項1記載の半導体記憶装置。 - 該検出回路は、
第1の電流を消費し第1の応答速度を有する第1の検出器と、
第2の電流を消費し第2の応答速度を有する第2の検出器
を含み、該オシレータ回路は、
該第1の検出器の出力に応答して第1の発振信号を出力する第1のオシレータと、
該第2の検出器の出力に応答して第2の発振信号を出力する第2のオシレータと、
該第1の発振信号と該第2の発振信号との何れか一方を選択して出力するセレクタ
を含むことを特徴とする請求項4記載の半導体記憶装置。 - ワード線を含むDRAMメモリコア回路と、
第1の状態と第2の状態との何れか選択された一方において動作することにより所定の電源電圧を生成して該DRAMメモリコア回路に供給し、該第2の状態においてよりも該第1の状態においての方がより大きな電流を消費する電源回路と、
該DRAMメモリコア回路の該ワード線が活性化されてから非活性化されるまでの期間に該電源回路を該第1の状態から該第2の状態に移行させ、ライトイネーブル信号のデアサートに応答して該第1の状態に戻すように該電源回路を制御する制御回路
を含み、
該制御回路は、該DRAMメモリコア回路のセンスアンプを活性化するセンスアンプ活性化信号のアサートから所定の遅延時間後に該電源回路を該第1の状態から該第2の状態に移行させ、
該制御回路は、該センスアンプ活性化信号のアサートから該所定の遅延時間が経過する前に該DRAMメモリコア回路のコラム選択線を活性化するコラム選択線活性化信号が活性化されると、該電源回路を該第2の状態に移行させることなく該第1の状態に維持することを特徴とする半導体記憶装置。 - 該制御回路は、該DRAMメモリコア回路のコラム選択線を活性化するコラム選択線活性化信号に応答して該電源回路を該第2の状態から該第1の状態に戻すことを特徴とする請求項1記載の半導体記憶装置。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006139055A JP5261888B2 (ja) | 2006-05-18 | 2006-05-18 | 半導体記憶装置 |
TW096116870A TWI348703B (en) | 2006-05-18 | 2007-05-11 | Semiconductor memory device with reduced current consumption |
EP07108186A EP1858026A1 (en) | 2006-05-18 | 2007-05-14 | Semiconductor memory device with reduced current consumption |
US11/798,629 US7633825B2 (en) | 2006-05-18 | 2007-05-15 | Semiconductor memory device with reduced current consumption |
KR1020070048041A KR100899517B1 (ko) | 2006-05-18 | 2007-05-17 | 반도체 기억 장치 |
CN2007101033144A CN101075479B (zh) | 2006-05-18 | 2007-05-18 | 具有低电流消耗特性的半导体存储装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006139055A JP5261888B2 (ja) | 2006-05-18 | 2006-05-18 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007310963A JP2007310963A (ja) | 2007-11-29 |
JP5261888B2 true JP5261888B2 (ja) | 2013-08-14 |
Family
ID=38330164
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006139055A Expired - Fee Related JP5261888B2 (ja) | 2006-05-18 | 2006-05-18 | 半導体記憶装置 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7633825B2 (ja) |
EP (1) | EP1858026A1 (ja) |
JP (1) | JP5261888B2 (ja) |
KR (1) | KR100899517B1 (ja) |
CN (1) | CN101075479B (ja) |
TW (1) | TWI348703B (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7352649B2 (en) * | 2005-07-21 | 2008-04-01 | Micron Technology, Inc. | High speed array pipeline architecture |
JP5261888B2 (ja) | 2006-05-18 | 2013-08-14 | 富士通セミコンダクター株式会社 | 半導体記憶装置 |
JP5116787B2 (ja) * | 2009-03-05 | 2013-01-09 | 住友重機械工業株式会社 | ハイブリッド型作業機械 |
CN103971729B (zh) * | 2013-01-30 | 2016-12-28 | 旺宏电子股份有限公司 | 偏压提供电路、存储区段控制器与存储器电路 |
KR20160002106A (ko) * | 2014-06-30 | 2016-01-07 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 그의 동작방법 |
CN105810233B (zh) * | 2014-12-31 | 2018-05-15 | 北京兆易创新科技股份有限公司 | 一种低功耗存储器的装置和方法 |
US10199090B2 (en) | 2016-09-21 | 2019-02-05 | Apple Inc. | Low active power write driver with reduced-power boost circuit |
CN107195322A (zh) * | 2017-07-11 | 2017-09-22 | 高科创芯(北京)科技有限公司 | 一种基于忆阻器的动态电源管理*** |
CN110905309B (zh) * | 2019-11-18 | 2021-09-17 | 北京新能源汽车股份有限公司 | 电子锁的控制***、方法和车辆 |
CN115603713B (zh) * | 2022-12-01 | 2023-04-04 | 深圳市恒运昌真空技术有限公司 | 一种脉冲信号处理方法、装置及匹配电路 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63106993A (ja) * | 1986-10-24 | 1988-05-12 | Hitachi Ltd | 半導体記憶装置 |
JPH03125394A (ja) * | 1989-10-09 | 1991-05-28 | Hitachi Micro Comput Eng Ltd | 半導体記憶装置 |
GB9007791D0 (en) * | 1990-04-06 | 1990-06-06 | Foss Richard C | High voltage boosted wordline supply charge pump and regulator for dram |
JPH04129089A (ja) * | 1990-09-19 | 1992-04-30 | Mitsubishi Electric Corp | ダイナミック型半導体記憶装置 |
JPH05159572A (ja) * | 1991-12-04 | 1993-06-25 | Hitachi Ltd | 半導体装置 |
JPH07105682A (ja) | 1993-10-06 | 1995-04-21 | Nec Corp | ダイナミックメモリ装置 |
JPH11288588A (ja) * | 1998-04-02 | 1999-10-19 | Mitsubishi Electric Corp | 半導体回路装置 |
JP4017248B2 (ja) * | 1998-04-10 | 2007-12-05 | 株式会社日立製作所 | 半導体装置 |
JP2001067867A (ja) * | 1999-08-31 | 2001-03-16 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP4271812B2 (ja) * | 2000-01-31 | 2009-06-03 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置の内部電源電圧生成回路の制御方法、半導体記憶装置の内部電源電圧生成回路の制御方法及び半導体記憶装置の内部電源電圧生成回路 |
US6418075B2 (en) | 2000-07-21 | 2002-07-09 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor merged logic and memory capable of preventing an increase in an abnormal current during power-up |
US6381182B1 (en) * | 2000-09-13 | 2002-04-30 | Infineon Technologies Ag | Combined tracking of WLL and VPP low threshold voltage in DRAM array |
US6518834B2 (en) * | 2001-05-14 | 2003-02-11 | Semiconductor Components Industries Llc | Circuit and method for reducing leakage current within an electronic system |
JP2002367369A (ja) * | 2001-06-05 | 2002-12-20 | Nec Corp | 半導体記憶装置 |
US6515929B1 (en) * | 2001-10-29 | 2003-02-04 | Etron Technology, Inc. | Partial refresh feature in pseudo SRAM |
JP2003178584A (ja) * | 2001-12-07 | 2003-06-27 | Toshiba Corp | 電圧発生回路 |
JP4249412B2 (ja) * | 2001-12-27 | 2009-04-02 | Necエレクトロニクス株式会社 | 半導体記憶装置 |
JP3959341B2 (ja) * | 2002-02-18 | 2007-08-15 | 株式会社東芝 | 半導体集積回路装置 |
KR100691485B1 (ko) * | 2003-07-29 | 2007-03-09 | 주식회사 하이닉스반도체 | 액티브 모드시에 전류소모를 줄일 수 있는 반도체 메모리장치 |
KR100534216B1 (ko) * | 2004-06-18 | 2005-12-08 | 삼성전자주식회사 | 반도체 메모리에서의 워드라인 드라이버 회로 및 그에따른 구동방법 |
JP4330516B2 (ja) * | 2004-08-04 | 2009-09-16 | パナソニック株式会社 | 半導体記憶装置 |
JP4255082B2 (ja) * | 2005-06-27 | 2009-04-15 | 富士通マイクロエレクトロニクス株式会社 | 電圧供給回路および半導体メモリ |
JP5261888B2 (ja) | 2006-05-18 | 2013-08-14 | 富士通セミコンダクター株式会社 | 半導体記憶装置 |
-
2006
- 2006-05-18 JP JP2006139055A patent/JP5261888B2/ja not_active Expired - Fee Related
-
2007
- 2007-05-11 TW TW096116870A patent/TWI348703B/zh not_active IP Right Cessation
- 2007-05-14 EP EP07108186A patent/EP1858026A1/en not_active Withdrawn
- 2007-05-15 US US11/798,629 patent/US7633825B2/en not_active Expired - Fee Related
- 2007-05-17 KR KR1020070048041A patent/KR100899517B1/ko active IP Right Grant
- 2007-05-18 CN CN2007101033144A patent/CN101075479B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US7633825B2 (en) | 2009-12-15 |
TW200744101A (en) | 2007-12-01 |
EP1858026A1 (en) | 2007-11-21 |
CN101075479A (zh) | 2007-11-21 |
JP2007310963A (ja) | 2007-11-29 |
US20070268769A1 (en) | 2007-11-22 |
CN101075479B (zh) | 2012-05-16 |
KR20070112018A (ko) | 2007-11-22 |
KR100899517B1 (ko) | 2009-05-27 |
TWI348703B (en) | 2011-09-11 |
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