JP5258497B2 - Wiring structure for solder joint inspection of printed wiring board - Google Patents

Wiring structure for solder joint inspection of printed wiring board Download PDF

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JP5258497B2
JP5258497B2 JP2008264429A JP2008264429A JP5258497B2 JP 5258497 B2 JP5258497 B2 JP 5258497B2 JP 2008264429 A JP2008264429 A JP 2008264429A JP 2008264429 A JP2008264429 A JP 2008264429A JP 5258497 B2 JP5258497 B2 JP 5258497B2
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printed wiring
wiring board
solder joint
package
pad
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JP2010093207A (en
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睦 島嵜
雅夫 金谷
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Mitsubishi Electric Corp
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Description

この発明は、はんだ接合部を有するプリント配線板のはんだ接合検査用配線構造に関するものである。   The present invention relates to a wiring structure for inspecting solder joints of a printed wiring board having solder joints.

例えば、ＢＧＡ（Ball Grid Array）パッケージを実装したプリント配線板（以降「基板」と称する。）のはんだ接合部は、パッケージと基板との間に隠れるので、パッケージの周囲に配置された外部接続端子であるはんだボール（以降「ピン」と称する。）以外のピンでは、そのはんだ接合の状態を目視で確認することができない。   For example, since a solder joint portion of a printed wiring board (hereinafter referred to as “substrate”) mounted with a BGA (Ball Grid Array) package is hidden between the package and the substrate, external connection terminals arranged around the package For pins other than the solder balls (hereinafter referred to as “pins”), the solder joint state cannot be visually confirmed.

隠れたはんだ接合部を検査する方法としては、Ｘ線撮影装置による透視映像を用いてはんだ形状を確認する方法の他に、ＴＤＲ（Time Domain Reflectometry：時間領域反射計測装置）を用いて、はんだ接合部につながる基板配線からの反射波の波形計測を行って電気的な接続有無を調べ、はんだ接合の状態を判断する方法が用いられる（例えば特許文献１の図２参照）。   As a method of inspecting the hidden solder joint, in addition to the method of confirming the solder shape using a fluoroscopic image obtained by an X-ray imaging apparatus, a solder joint using TDR (Time Domain Reflectometry) is used. A method is used in which the presence or absence of electrical connection is determined by measuring the waveform of a reflected wave from the substrate wiring connected to the part to determine the state of solder bonding (see, for example, FIG. 2 of Patent Document 1).

半導体集積回路パッケージの中でも、特にピン数の多いＢＧＡパッケージは、ＧＮＤやＶＣＣ等の給電ピンが複数あるので、ＢＧＡパッケージを実装する基板は、配線引き出しのために、多層の基板を用いる。そして、この多層の基板において、ＧＮＤやＶＣＣ等への給電配線は、ベタ面をなす導体プレーンによる層（以降「給電層」と称する。）で形成される。ＢＧＡパッケージの給電ピンは、通常、はんだ接合される基板のＢＧＡパッドの直近に設けてあるビアで給電層に接続されている（例えば特許文献２の図１参照）。   Among the semiconductor integrated circuit packages, a BGA package having a large number of pins has a plurality of power supply pins such as GND and VCC. Therefore, a substrate on which the BGA package is mounted uses a multilayer substrate for wiring extraction. In this multilayer substrate, the power supply wiring to GND, VCC, etc. is formed by a layer (hereinafter referred to as “power supply layer”) made of a solid conductor plane. The power supply pin of the BGA package is normally connected to the power supply layer by a via provided in the immediate vicinity of the BGA pad of the substrate to be soldered (see, for example, FIG. 1 of Patent Document 2).

特開平９−６１４８６号公報JP-A-9-61486 特開２００６−３２４４４４号公報JP 2006-324444 A

ここで、ＴＤＲによるはんだ接合部の電気接続検査は、基板配線にプローブを接触させて行うので、基板配線にプローブ用のテストパッドを設けるか、配線区間内に在るビアやランドをテストパッドとして代用する。しかし、特にピン数の多いＢＧＡパッケージを実装する基板では、全ピンに対する検査のために、ピン数と同数のテストパッドを設けるのは、配置が困難であるだけでなく、ＢＧＡパッケージ実装の本質である基板面積の節約効果が期待できなくなる。そのため、ＢＧＡパッケージを実装する基板では、回路形成における配線引き出しのために、ＢＧＡパッドの直近に設けられるビアをテストパッドとして代用するのが有効である。この場合、プローブは、基板のＢＧＡ実装面と反対面のビアに接触させる。   Here, since the electrical connection inspection of the solder joint portion by TDR is performed by bringing a probe into contact with the board wiring, a test pad for the probe is provided on the board wiring, or a via or land in the wiring section is used as a test pad. to substitute. However, it is not only difficult to arrange test pads as many as the number of pins for the inspection of all pins, especially on a board mounting a BGA package with a large number of pins. The saving effect of a certain substrate area cannot be expected. For this reason, in a substrate on which a BGA package is mounted, it is effective to substitute a via provided in the immediate vicinity of the BGA pad as a test pad in order to lead out a wiring in forming a circuit. In this case, the probe is brought into contact with a via on the surface opposite to the BGA mounting surface of the substrate.

ところが、ＢＧＡパッケージを実装する基板は、前記したように、ＢＧＡ給電ピンがＢＧＡパッド直近のビアで給電層に接続される構造の多層基板であり、給電配線は伝送路を構成しないベタ面である。そのため、電流経路が不確定である。同時に、複数の給電ピンが給電層によって共通配線されるので、はんだ接合部のインピーダンスは、常に、ほぼゼロとなる。つまり、給電ピンは、接合されていないピンが存在しても、他の接合されているピンによって電気的には短絡されている。したがって、電流経路となる配線区間にプローブを接触させて、インピーダンスの時間変化を計測し接合状態を判断するＴＤＲでは、ＢＧＡパッド直近のビアにプローブを接触させても、はんだ接合部の電気接続検査ができないという問題があった。   However, as described above, the board on which the BGA package is mounted is a multilayer board having a structure in which the BGA feed pin is connected to the feed layer through the via close to the BGA pad, and the feed wiring is a solid surface that does not constitute a transmission path. . Therefore, the current path is indeterminate. At the same time, since the plurality of power supply pins are commonly wired by the power supply layer, the impedance of the solder joint is always almost zero. That is, the power feeding pin is electrically short-circuited by another joined pin even if there is an unjoined pin. Therefore, in TDR, in which the probe is brought into contact with the wiring section serving as the current path, the impedance change over time is measured and the joining state is judged, even if the probe is brought into contact with the via close to the BGA pad, the electrical connection inspection of the solder joint is performed. There was a problem that could not.

この発明は、上記に鑑みてなされたものであり、はんだ接合部を有するプリント配線板において、ＴＤＲを用いて該はんだ接合部の接合状態に応じたインピーダンス差異を計測可能にするはんだ接合部検査用配線構造を得ることを目的とする。   The present invention has been made in view of the above, and in a printed wiring board having a solder joint, using a TDR, it is possible to measure an impedance difference according to the joint state of the solder joint. The object is to obtain a wiring structure.

上述した目的を達成するために、この発明は、プリント配線板において、実装される電子部品の給電用端子がはんだ接合されるパッドと給電層との間を接続する伝送遅延時間Ｌｓの伝送線路と、前記伝送線路上の前記パッドからの伝送遅延時間がＬｔ（Ｌｔ≦Ｌｓ／２）である位置に配置されたテストパッドとを備えていることを特徴とする。   In order to achieve the above-described object, the present invention provides a transmission line having a transmission delay time Ls for connecting a power supply terminal between a power supply terminal of a mounted electronic component and a power supply layer in a printed wiring board. And a test pad arranged at a position where a transmission delay time from the pad on the transmission line is Lt (Lt ≦ Ls / 2).

この発明によれば、はんだ接合によって実装される電子部品における給電用のはんだ接合部への電流経路を確定し、複数の同機能はんだ接合部による電気的な短絡点を時間的に離すことができるので、ＴＤＲを用いて該はんだ接合部の接合状態に応じたインピーダンス差異が計測可能になるという効果を奏する。   According to the present invention, it is possible to determine a current path to a power supply solder joint in an electronic component mounted by solder joint, and to temporally separate electrical short-circuit points by a plurality of the same function solder joints. Therefore, there is an effect that the impedance difference according to the joining state of the solder joint can be measured using TDR.

以下に図面を参照して、この発明にかかるプリント配線板のはんだ接合部検査用配線構造の好適な実施の形態を詳細に説明する。   Exemplary embodiments of a wiring structure for inspecting a solder joint portion of a printed wiring board according to the present invention will be described below in detail with reference to the drawings.

実施の形態１．
図１は、この発明の実施の形態１によるプリント配線板のはんだ接合部検査用配線構造の配線条件を説明する配線パターン図である。図１において、符号１は、検査対象の電子部品として、例えば、ＢＧＡパッケージである。符号２と符号５は、それぞれ、基板の実装面に配置されるパッドである。ここでは、ＢＧＡパッケージ１のピンが接合相手なので、パッド２，５は、ＢＧＡパッド２，５と称する。 Embodiment 1 FIG.
1 is a wiring pattern diagram for explaining wiring conditions of a wiring structure for inspecting a solder joint portion of a printed wiring board according to Embodiment 1 of the present invention. In FIG. 1, reference numeral 1 denotes, for example, a BGA package as an electronic component to be inspected. Reference numerals 2 and 5 are pads arranged on the mounting surface of the substrate, respectively. Here, since the pins of the BGA package 1 are mating counterparts, the pads 2 and 5 are referred to as BGA pads 2 and 5.

ＢＧＡパッケージ１の給電ピンには、多数のＶＣＣピン及びＧＮＤピンがある。図１では、代表例として、１つのＶＣＣピン及び１つのＧＮＤピンを取り上げ、１つのＶＣＣピンがＢＧＡパッド２にはんだ接合され、１つのＧＮＤピンがＢＧＡパッド５にはんだ接合される場合を示している。   The power supply pins of the BGA package 1 include a number of VCC pins and GND pins. FIG. 1 shows a case where one VCC pin and one GND pin are taken as a representative example, and one VCC pin is soldered to the BGA pad 2 and one GND pin is soldered to the BGA pad 5. Yes.

符号３と符号６は、それぞれ、基板における給電層である。これらの給電層は、導体プレーンによるベタ面を有するベタ層である。図示例では、給電層３はＶＣＣ用であり、給電層６はＧＮＤ用である。   Reference numerals 3 and 6 are power supply layers on the substrate, respectively. These power supply layers are solid layers having a solid surface formed by a conductor plane. In the illustrated example, the power feeding layer 3 is for VCC, and the power feeding layer 6 is for GND.

さて、図１（１）（２）に示すように、ＢＧＡパッド２とＶＣＣ給電層３との間を伝送遅延時間がＬｓである伝送線路４で接続し、ＢＧＡパッド５とＧＮＤ給電層６との間を伝送遅延時間がＬｓである伝送線路７で接続する。   As shown in FIGS. 1A and 1B, the BGA pad 2 and the VCC power supply layer 3 are connected by a transmission line 4 having a transmission delay time Ls, and the BGA pad 5 and the GND power supply layer 6 are connected. Are connected by a transmission line 7 having a transmission delay time Ls.

また、図１（１）に示すように、プロービング用のテストパッド８，９を伝送線路４，７上にそれぞれ配置する。この場合、ＢＧＡパッド２，５からテストパッド８，９までの伝送遅延時間Ｌｔは、伝送線路４，７での伝送遅延時間Ｌｓの１／２以下とする。   In addition, as shown in FIG. 1A, probing test pads 8 and 9 are arranged on the transmission lines 4 and 7, respectively. In this case, the transmission delay time Lt from the BGA pads 2 and 5 to the test pads 8 and 9 is set to ½ or less of the transmission delay time Ls in the transmission lines 4 and 7.

そして、図１（２）に示すように、テストパッド８，９を伝送線路４，７から離れた位置に配置する場合は、テストパッド８，９と伝送線路４，７との間を接続する分岐伝送線路１０，１１での伝送遅延時間ａは、「Ｌｓ−Ｌｔ」以下とする。   As shown in FIG. 1 (2), when the test pads 8 and 9 are arranged at positions away from the transmission lines 4 and 7, the test pads 8 and 9 and the transmission lines 4 and 7 are connected. The transmission delay time a in the branch transmission lines 10 and 11 is set to “Ls−Lt” or less.

多層構成の基板では、各層に各種材質の媒体が用いられるが、同一媒体の中での伝送遅延時間は、距離に正比例するので、伝送線路４，７や分岐伝送線路１０，１１の配線パターンを同一基材で構成した場合、伝送遅延時間Ｌｓ，Ｌｔ，ａは、それぞれ、伝送線路の長さと考えてよい。   In a multi-layered substrate, media of various materials are used for each layer, but the transmission delay time in the same medium is directly proportional to the distance, so the wiring patterns of the transmission lines 4 and 7 and the branch transmission lines 10 and 11 are used. When configured with the same base material, the transmission delay times Ls, Lt, and a may be considered as the lengths of the transmission lines.

これによって、給電層３，６から検査対象のはんだ接合部であるＢＧＡパッド２，５までの電流経路を確定することができる。また、複数の給電ピンがベタ面の給電層によって共通接続されず、その給電層からそれぞれの給電ピンまで伝送遅延時間の異なる伝送線路で接続されるので、複数の同機能給電ピンによる電気的な短絡点を時間的に分離することができる。   As a result, a current path from the power supply layers 3 and 6 to the BGA pads 2 and 5 which are solder joints to be inspected can be determined. In addition, since the plurality of power supply pins are not connected in common by the power supply layer on the solid surface, but are connected from the power supply layer to each power supply pin by transmission lines having different transmission delay times, The short-circuit points can be separated in time.

実施の形態２．
図２は、この発明の実施の形態２として、図１にて説明する配線条件を満たすはんだ接合部検査用配線構造を有するプリント配線板の具体的な構造例を説明する図である。図２（２）に示す断面図では、基板２０の層構成と、検査対象パッケージであるＢＧＡパッケージ２６の実装状態とが示されている。基板２０は、第３層に給電層２１を有する。なお、給電層２１は、説明の便宜から、ＶＣＣ給電層とＧＮＤ給電層との双方を一緒に示してある。以降、給電層２１は、ＶＣＣ／ＧＮＤベタ層２１と称する。 Embodiment 2. FIG.
FIG. 2 is a diagram illustrating a specific structural example of a printed wiring board having a solder joint inspection wiring structure that satisfies the wiring conditions described in FIG. 1 as Embodiment 2 of the present invention. In the cross-sectional view shown in FIG. 2B, the layer configuration of the substrate 20 and the mounting state of the BGA package 26 which is a package to be inspected are shown. The board | substrate 20 has the electric power feeding layer 21 in the 3rd layer. Note that the power feeding layer 21 shows both the VCC power feeding layer and the GND power feeding layer together for convenience of explanation. Hereinafter, the power feeding layer 21 is referred to as a VCC / GND solid layer 21.

ＢＧＡパッケージ２６は、信号ピン２３とＶＣＣ／ＧＮＤピン２４とが対応するＢＧＡパッドにはんだ接合される。ＶＣＣ／ＧＮＤピン２４がはんだ接合されるＢＧＡパッド２９の直近にはビア２７が設けられる。符号を付してないが信号ピン２３がはんだ接合されるＢＧＡパッドでも同様である。また、図２（１）に示す上面透視図では、基板２０の第１，第２の層を透かした第３層のＶＣＣ／ＧＮＤベタ層２１と、ＢＧＡパッケージ２６の実装位置直下における配線状態とが示されている。   The BGA package 26 is soldered to a BGA pad corresponding to the signal pin 23 and the VCC / GND pin 24. A via 27 is provided in the immediate vicinity of the BGA pad 29 to which the VCC / GND pin 24 is soldered. The same applies to a BGA pad to which the signal pin 23 is soldered, although not labeled. In the top perspective view shown in FIG. 2A, the third VCC / GND solid layer 21 through which the first and second layers of the substrate 20 are watermarked, and the wiring state immediately below the mounting position of the BGA package 26 are shown. It is shown.

さて、図２に示すように、ＢＧＡパッケージ２６の実装位置２２直下の給電層（図示例では第３層のＶＣＣ／ＧＮＤベタ層２１）をパッケージ外形形状でくり抜き、ＶＣＣ／ＧＮＤピン２４がはんだ接合されるＢＧＡパッド２９の直近に在るビア２７のＶＣＣ／ＧＮＤベタ層２１に対応する側部と、ＶＣＣ／ＧＮＤベタ層２１のくり抜き側端部とを引き出し配線２５で接続する。そして、ビア２７の下端を、プローブを接触させるテストパッド２８として使用できる形状にしておけば、実質的に図１にて説明した配線条件を満たすはんだ接合部検査用配線構造が構成される。   As shown in FIG. 2, the power supply layer (the third VCC / GND solid layer 21 in the illustrated example) immediately below the mounting position 22 of the BGA package 26 is cut out in the package outer shape, and the VCC / GND pin 24 is soldered. The side portion corresponding to the VCC / GND solid layer 21 of the via 27 immediately adjacent to the BGA pad 29 to be connected to the cut-out side end portion of the VCC / GND solid layer 21 is connected by the lead wiring 25. If the lower end of the via 27 is formed into a shape that can be used as a test pad 28 with which the probe is brought into contact, a solder joint inspection wiring structure that substantially satisfies the wiring conditions described in FIG. 1 is configured.

このように、図１にて説明した配線条件を満たすはんだ接合部検査用配線構造を組み込んだ基板２０では、ＶＣＣ／ＧＮＤベタ層２１から、検査対象のはんだ接合部（ＶＣＣ／ＧＮＤピン２４がはんだ接合されるＢＧＡパッド２９）までの電流経路が確定されているので、テストパッド２８にプローブを接触させてＴＤＲの測定を実施すると、検査対象のはんだ接合部からの反射波形を得ることができる。   As described above, in the board 20 incorporating the solder joint inspection wiring structure that satisfies the wiring conditions described in FIG. 1, the test target solder joint (VCC / GND pin 24 is soldered) from the VCC / GND solid layer 21. Since the current path to the BGA pad 29) to be joined is determined, when the probe is brought into contact with the test pad 28 and TDR measurement is performed, a reflected waveform from the solder joint portion to be inspected can be obtained.

このとき、ＶＣＣ／ＧＮＤベタ層２１までの伝送遅延時間によって、複数ある同機能ピンの影響が排除される。その結果、例えば図３に示すように、接合されているピンと接合されていないピンとでインピーダンスの相違を計測でき、接合状態を判断することが可能になる。   At this time, the influence of a plurality of the same function pins is eliminated by the transmission delay time to the VCC / GND solid layer 21. As a result, for example, as shown in FIG. 3, the difference in impedance can be measured between a pin that is joined and a pin that is not joined, and the joining state can be determined.

図３は、図１にて説明する配線条件を満たすはんだ接合部検査用配線構造を有するプリント配線板においてＴＤＲによる各種のはんだ接合部の電気接続検査を実施した場合のＴＤＲ計測波形を比較して示す波形図である。図３では、接合されているピンの波形３２と接合されていないピンの波形３１とが識別可能に得られることが示されている。接合されているピンの波形３２は既知の波形である。   FIG. 3 compares TDR measurement waveforms when electrical connection inspection of various solder joints by TDR is performed on a printed wiring board having a solder joint inspection wiring structure that satisfies the wiring conditions described in FIG. FIG. FIG. 3 shows that the waveform 32 of the pin that is joined and the waveform 31 of the pin that is not joined are identifiable. The waveform 32 of the pin being joined is a known waveform.

以上のように、この実施の形態によれば、検査対象に、元々検査可能な信号ピンに給電ピンが加わるので、実質的にＴＤＲによるＢＧＡパッケージの全ピンのはんだ接合検査を実施することが可能となり、Ｘ線撮影装置に対するＴＤＲの利点である低コストでの高速検査が実現できる。   As described above, according to this embodiment, since the power supply pin is added to the signal pin that can be inspected in the inspection object, it is possible to substantially perform the solder joint inspection of all the pins of the BGA package by TDR. Thus, high-speed inspection at low cost, which is an advantage of TDR over the X-ray imaging apparatus, can be realized.

なお、図２では、ピン数の多いＢＧＡパッケージとのはんだ接合部を検査することを目的に、プローブを接触させるテストパッドをビア２７で代用する構成例を示したが、テストパッドが予め設けられている場合や、基板２０の表層に給電層が設けられている場合でも、図１にて説明した配線条件で、引き出し配線とテストパッドとを形成すれば、同様に給電ピンの検査が可能である。   FIG. 2 shows a configuration example in which the test pad for contacting the probe is replaced by the via 27 for the purpose of inspecting the solder joint portion with the BGA package having a large number of pins. However, the test pad is provided in advance. Even if the power supply layer is provided on the surface layer of the substrate 20, if the lead-out wiring and the test pad are formed under the wiring conditions described in FIG. is there.

また、以上に示した実施の形態では、ＢＧＡパッケージを実装する基板に組み込んだはんだ接合部検査用配線構造の構成例を説明したが、半導体集積回路パッケージ以外の他のはんだ接合の検査にも利用できることはいうまでもない。   In the above-described embodiment, the configuration example of the wiring structure for inspecting the solder joint incorporated in the substrate on which the BGA package is mounted has been described. However, the embodiment is also used for inspecting other solder joints other than the semiconductor integrated circuit package. Needless to say, it can be done.

以上のように、この発明にかかるプリント配線板のはんだ接合部検査用配線構造は、はんだ接合部を有するプリント配線板において、ＴＤＲを用いて該はんだ接合部の接合状態に応じたインピーダンス差異を計測可能にするはんだ接合部検査用配線構造として有用であり、特に、ピン数の多い半導体集積回路パッケージとのはんだ接合部を検査するのに適している。   As described above, the printed wiring board solder joint inspection wiring structure according to the present invention uses the TDR to measure the impedance difference according to the joining state of the solder joint in the printed wiring board having the solder joint. This is useful as a wiring structure for inspecting solder joints, and is particularly suitable for inspecting solder joints with a semiconductor integrated circuit package having a large number of pins.

この発明の実施の形態１によるプリント配線板のはんだ接合部検査用配線構造の配線条件を説明する配線パターン図である。It is a wiring pattern figure explaining the wiring conditions of the wiring structure for a solder joint part inspection of the printed wiring board by Embodiment 1 of this invention. この発明の実施の形態２として、図１にて説明する配線条件を満たすはんだ接合部検査用配線構造を有するプリント配線板の具体的な構造例を説明する図である。As Embodiment 2 of this invention, it is a figure explaining the example of a specific structure of the printed wiring board which has the wiring structure for solder joint inspection which satisfy | fills the wiring condition demonstrated in FIG. 図１にて説明する配線条件を満たすはんだ接合部検査用配線構造を有するプリント配線板においてＴＤＲによる各種のはんだ接合部の電気接続検査を実施した場合のＴＤＲ計測波形を比較して示す波形図である。FIG. 2 is a waveform diagram showing a comparison of TDR measurement waveforms when various electrical connection inspections of various solder joints are performed by TDR on a printed wiring board having a solder joint inspection wiring structure that satisfies the wiring conditions described in FIG. is there.

符号の説明Explanation of symbols

１ 検査対象の電子部品（ＢＧＡパッケージ）
２，５，２９ パッド（ＢＧＡパッド）
３ ＶＣＣ給電層
４，７ 伝送線路
６ ＧＮＤ給電層
８，９ テストパッド
１０，１１ 分岐伝送線路
２０ プリント配線板（基板）
２１ 給電層（ＶＣＣ／ＧＮＤベタ層）
２２ ＢＧＡパッケージの実装位置
２３ 信号ピン
２４ ＶＣＣ／ＧＮＤピン
２５ 引き出し配線
２６ 検査対象パッケージ（ＢＧＡパッケージ）
２７ ビア
２８ ビア２７の下端に形成したテストパッド 1 Electronic components to be inspected (BGA package)
2,5,29 pad (BGA pad)
3 VCC feeding layer 4, 7 Transmission line 6 GND feeding layer 8, 9 Test pad 10, 11 Branch transmission line 20 Printed wiring board (board)
21 Power feeding layer (VCC / GND solid layer)
22 BGA package mounting position 23 Signal pin 24 VCC / GND pin 25 Lead-out wiring 26 Package to be inspected (BGA package)
27 Via 28 Test pad formed at the lower end of the via 27

Claims (3)

プリント配線板において、
実装される電子部品の給電用端子がはんだ接合されるパッドと、前記プリント配線板の主面に垂直な方向から透視した場合に前記プリント配線板に略均等な形状のベタ層が前記電子部品に重ならないようにくり抜かれた給電層との間を接続する伝送遅延時間Ｌｓの伝送線路と、
前記伝送線路上の前記パッドからの伝送遅延時間がＬｔ（Ｌｔ≦Ｌｓ／２）である位置から分岐する伝送遅延時間がａ（ａ≦Ｌｓ−Ｌｔ）である分岐伝送線路を介して前記伝送線路に接続されているテストパッドと、
を備えていることを特徴とするプリント配線板のはんだ接合検査用配線構造。 In printed wiring boards,
A pad to which a power feeding terminal of the electronic component to be mounted is soldered and a solid layer having a substantially uniform shape on the printed wiring board when seen through from a direction perpendicular to the main surface of the printed wiring board are formed on the electronic component. A transmission line having a transmission delay time Ls connecting between the feeding layers hollowed out so as not to overlap ,
The transmission line via the branch transmission line whose transmission delay time a (a ≦ Ls−Lt) branches from the position where the transmission delay time from the pad on the transmission line is Lt (Lt ≦ Ls / 2). A test pad connected to the
A printed wiring board solder joint inspection wiring structure characterized by comprising: 前記電子部品は、表面実装型パッケージで実装されており、  The electronic component is mounted in a surface mount type package,
ビアは、前記プリント配線板の主面に垂直な方向から透視した場合に表面実装型パッケージに重なる位置において、表面実装型パッケージ側の一端から表面実装型パッケージの反対側の他端まで前記プリント配線板を貫通しており、  The vias extend from the one end on the surface mounted package side to the other end on the opposite side of the surface mounted package at a position overlapping the surface mounted package when viewed from a direction perpendicular to the main surface of the printed wiring board. Through the board,
前記プリント配線板の内層には、前記給電層と、前記給電層をビアの一端及び他端の中間部に電気的に接続する引き出し配線とが設けられており、  The inner layer of the printed wiring board is provided with the power feeding layer and a lead-out wiring that electrically connects the power feeding layer to an intermediate portion between one end and the other end of the via.
前記ビアの一端は、はんだ接合されるパッドに電気的に接続され、  One end of the via is electrically connected to a solder bonded pad;
前記ビアの他端は、テストパッドに接続されている  The other end of the via is connected to a test pad
ことを特徴とする請求項１に記載のプリント配線板のはんだ接合検査用配線構造。  The printed wiring board solder joint inspection wiring structure according to claim 1. 前記表面実装型パッケージは、ＢＧＡパッケージである  The surface mount package is a BGA package.
ことを特徴とする請求項２に記載のプリント配線板のはんだ接合検査用配線構造。  The printed wiring board solder joint inspection wiring structure according to claim 2.
JP2008264429A 2008-10-10 2008-10-10 Wiring structure for solder joint inspection of printed wiring board Expired - Fee Related JP5258497B2 (en)

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CN113900008A (en) * 2021-09-15 2022-01-07 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） Test structure and test method

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