JP5203352B2 - エッチング停止層を用いてソース/ドレイン・ストレッサの形成を最適化する半導体の製造方法 - Google Patents
エッチング停止層を用いてソース/ドレイン・ストレッサの形成を最適化する半導体の製造方法 Download PDFInfo
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- JP5203352B2 JP5203352B2 JP2009503114A JP2009503114A JP5203352B2 JP 5203352 B2 JP5203352 B2 JP 5203352B2 JP 2009503114 A JP2009503114 A JP 2009503114A JP 2009503114 A JP2009503114 A JP 2009503114A JP 5203352 B2 JP5203352 B2 JP 5203352B2
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- 239000004065 semiconductor Substances 0.000 title claims description 39
- 238000005530 etching Methods 0.000 title claims description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 230000015572 biosynthetic process Effects 0.000 title description 6
- 238000000034 method Methods 0.000 claims description 32
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 19
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 description 13
- 238000010586 diagram Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000007943 implant Substances 0.000 description 5
- 239000010408 film Substances 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000010420 art technique Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
Claims (4)
- 半導体の製造方法であって、
埋め込み酸化物(BOX)層の上のエッチング停止層(ESL)の上の活性半導体層を含む集積回路ウエハを形成することと、
前記活性半導体層のトランジスタチャネルの上にゲート誘電体の上のゲート電極を含むゲート構造を形成することと、
トランジスタチャネルの両側面に退けられたソース/ドレイン領域のエッチングを行い、前記ESLを露出するソース/ドレイン空隙を形成することと、
ソース/ドレイン・ストレッサを用いて前記ESLの上の前記ソース/ドレイン空隙を充填することと、前記ソース/ドレイン・ストレッサの格子定数は活性半導体層の格子定数と異なることと、
を含み、
前記集積回路ウエハを形成することは、
ドナーウエハの半導体基板上に前記エッチング停止層を形成することと、
前記エッチング停止層上に誘電体層を堆積させることと、
前記ドナーウエハへ水素を注入し、前記ドナーウエハの前記半導体基板に損傷領域を形成することと、
ハンドルウエハの半導体基板上に誘電体層を堆積させることと、
ドナーウエハの誘電体層をハンドルウエハの誘電体層に接合することと、
前記損傷領域に沿って前記ドナーウエハを分断することと、
を含む方法。 - 前記活性半導体層を形成することはシリコンを含み、前記ESLは半導体化合物を含む請求項1に記載の方法。
- 前記半導体化合物は前記活性半導体層に擬似格子整合している請求項2に記載の方法。
- 前記半導体化合物はシリコンゲルマニウム化合物Si(1−X)GeXを含み、同シリコンゲルマニウム化合物中のゲルマニウムの百分率(X)は、5〜15%の範囲にある請求項3に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/393,340 | 2006-03-30 | ||
US11/393,340 US7494856B2 (en) | 2006-03-30 | 2006-03-30 | Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor |
PCT/US2007/062559 WO2007117775A2 (en) | 2006-03-30 | 2007-02-22 | Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor |
Publications (3)
Publication Number | Publication Date |
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JP2009532875A JP2009532875A (ja) | 2009-09-10 |
JP2009532875A5 JP2009532875A5 (ja) | 2010-03-18 |
JP5203352B2 true JP5203352B2 (ja) | 2013-06-05 |
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JP2009503114A Expired - Fee Related JP5203352B2 (ja) | 2006-03-30 | 2007-02-22 | エッチング停止層を用いてソース/ドレイン・ストレッサの形成を最適化する半導体の製造方法 |
Country Status (6)
Country | Link |
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US (1) | US7494856B2 (ja) |
EP (1) | EP2005477A4 (ja) |
JP (1) | JP5203352B2 (ja) |
KR (1) | KR20080108498A (ja) |
TW (1) | TWI447815B (ja) |
WO (1) | WO2007117775A2 (ja) |
Families Citing this family (51)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200802544A (en) * | 2006-04-25 | 2008-01-01 | Osram Opto Semiconductors Gmbh | Composite substrate and method for making the same |
KR100703986B1 (ko) * | 2006-05-22 | 2007-04-09 | 삼성전자주식회사 | 동작 특성과 플리커 노이즈 특성이 향상된 아날로그트랜지스터를 구비하는 반도체 소자 및 그 제조 방법 |
US20090289280A1 (en) * | 2008-05-22 | 2009-11-26 | Da Zhang | Method for Making Transistors and the Device Thereof |
US8003454B2 (en) * | 2008-05-22 | 2011-08-23 | Freescale Semiconductor, Inc. | CMOS process with optimized PMOS and NMOS transistor devices |
KR101797964B1 (ko) | 2010-10-01 | 2017-11-15 | 삼성전자주식회사 | 반도체 장치의 제조 방법 및 그 방법으로 제조된 반도체 장치 |
KR20120073727A (ko) * | 2010-12-27 | 2012-07-05 | 삼성전자주식회사 | 스트레인드 반도체 영역을 포함하는 반도체 소자와 그 제조방법, 및 그것을 포함하는 전자 시스템 |
US8466502B2 (en) | 2011-03-24 | 2013-06-18 | United Microelectronics Corp. | Metal-gate CMOS device |
US8445363B2 (en) | 2011-04-21 | 2013-05-21 | United Microelectronics Corp. | Method of fabricating an epitaxial layer |
US8324059B2 (en) | 2011-04-25 | 2012-12-04 | United Microelectronics Corp. | Method of fabricating a semiconductor structure |
US8426284B2 (en) | 2011-05-11 | 2013-04-23 | United Microelectronics Corp. | Manufacturing method for semiconductor structure |
US8481391B2 (en) | 2011-05-18 | 2013-07-09 | United Microelectronics Corp. | Process for manufacturing stress-providing structure and semiconductor device with such stress-providing structure |
US8431460B2 (en) | 2011-05-27 | 2013-04-30 | United Microelectronics Corp. | Method for fabricating semiconductor device |
US8946064B2 (en) | 2011-06-16 | 2015-02-03 | International Business Machines Corporation | Transistor with buried silicon germanium for improved proximity control and optimized recess shape |
WO2013025748A1 (en) * | 2011-08-15 | 2013-02-21 | King Abdullah University Of Science And Technology | Method for producing mechanically flexible silicon substrate |
US8609518B2 (en) * | 2011-07-22 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Re-growing source/drain regions from un-relaxed silicon layer |
US8716750B2 (en) | 2011-07-25 | 2014-05-06 | United Microelectronics Corp. | Semiconductor device having epitaxial structures |
US8575043B2 (en) | 2011-07-26 | 2013-11-05 | United Microelectronics Corp. | Semiconductor device and manufacturing method thereof |
US8647941B2 (en) | 2011-08-17 | 2014-02-11 | United Microelectronics Corp. | Method of forming semiconductor device |
US8674433B2 (en) | 2011-08-24 | 2014-03-18 | United Microelectronics Corp. | Semiconductor process |
US8476169B2 (en) | 2011-10-17 | 2013-07-02 | United Microelectronics Corp. | Method of making strained silicon channel semiconductor structure |
US8691659B2 (en) | 2011-10-26 | 2014-04-08 | United Microelectronics Corp. | Method for forming void-free dielectric layer |
US8754448B2 (en) | 2011-11-01 | 2014-06-17 | United Microelectronics Corp. | Semiconductor device having epitaxial layer |
US8647953B2 (en) | 2011-11-17 | 2014-02-11 | United Microelectronics Corp. | Method for fabricating first and second epitaxial cap layers |
US8709930B2 (en) | 2011-11-25 | 2014-04-29 | United Microelectronics Corp. | Semiconductor process |
US9059248B2 (en) * | 2012-02-09 | 2015-06-16 | International Business Machines Corporation | Junction butting on SOI by raised epitaxial structure and method |
US9136348B2 (en) | 2012-03-12 | 2015-09-15 | United Microelectronics Corp. | Semiconductor structure and fabrication method thereof |
US9202914B2 (en) | 2012-03-14 | 2015-12-01 | United Microelectronics Corporation | Semiconductor device and method for fabricating the same |
US8664069B2 (en) | 2012-04-05 | 2014-03-04 | United Microelectronics Corp. | Semiconductor structure and process thereof |
US8866230B2 (en) | 2012-04-26 | 2014-10-21 | United Microelectronics Corp. | Semiconductor devices |
US8835243B2 (en) | 2012-05-04 | 2014-09-16 | United Microelectronics Corp. | Semiconductor process |
KR101908451B1 (ko) | 2012-06-04 | 2018-10-16 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
US8951876B2 (en) | 2012-06-20 | 2015-02-10 | United Microelectronics Corp. | Semiconductor device and manufacturing method thereof |
US8796695B2 (en) | 2012-06-22 | 2014-08-05 | United Microelectronics Corp. | Multi-gate field-effect transistor and process thereof |
US8710632B2 (en) | 2012-09-07 | 2014-04-29 | United Microelectronics Corp. | Compound semiconductor epitaxial structure and method for fabricating the same |
US9117925B2 (en) | 2013-01-31 | 2015-08-25 | United Microelectronics Corp. | Epitaxial process |
US8753902B1 (en) | 2013-03-13 | 2014-06-17 | United Microelectronics Corp. | Method of controlling etching process for forming epitaxial structure |
US9034705B2 (en) | 2013-03-26 | 2015-05-19 | United Microelectronics Corp. | Method of forming semiconductor device |
US9064893B2 (en) | 2013-05-13 | 2015-06-23 | United Microelectronics Corp. | Gradient dopant of strained substrate manufacturing method of semiconductor device |
US8853060B1 (en) | 2013-05-27 | 2014-10-07 | United Microelectronics Corp. | Epitaxial process |
US9076652B2 (en) | 2013-05-27 | 2015-07-07 | United Microelectronics Corp. | Semiconductor process for modifying shape of recess |
US8765546B1 (en) | 2013-06-24 | 2014-07-01 | United Microelectronics Corp. | Method for fabricating fin-shaped field-effect transistor |
US8895396B1 (en) | 2013-07-11 | 2014-11-25 | United Microelectronics Corp. | Epitaxial Process of forming stress inducing epitaxial layers in source and drain regions of PMOS and NMOS structures |
US8981487B2 (en) | 2013-07-31 | 2015-03-17 | United Microelectronics Corp. | Fin-shaped field-effect transistor (FinFET) |
US9917189B2 (en) | 2015-07-31 | 2018-03-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for detecting presence and location of defects in a substrate |
US9831324B1 (en) | 2016-08-12 | 2017-11-28 | International Business Machines Corporation | Self-aligned inner-spacer replacement process using implantation |
US10461152B2 (en) | 2017-07-10 | 2019-10-29 | Globalfoundries Inc. | Radio frequency switches with air gap structures |
US10833153B2 (en) * | 2017-09-13 | 2020-11-10 | Globalfoundries Inc. | Switch with local silicon on insulator (SOI) and deep trench isolation |
US10446643B2 (en) | 2018-01-22 | 2019-10-15 | Globalfoundries Inc. | Sealed cavity structures with a planar surface |
US11410872B2 (en) | 2018-11-30 | 2022-08-09 | Globalfoundries U.S. Inc. | Oxidized cavity structures within and under semiconductor devices |
US10923577B2 (en) | 2019-01-07 | 2021-02-16 | Globalfoundries U.S. Inc. | Cavity structures under shallow trench isolation regions |
US11127816B2 (en) | 2020-02-14 | 2021-09-21 | Globalfoundries U.S. Inc. | Heterojunction bipolar transistors with one or more sealed airgap |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5218213A (en) * | 1991-02-22 | 1993-06-08 | Harris Corporation | SOI wafer with sige |
US6690043B1 (en) * | 1999-11-26 | 2004-02-10 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US6633066B1 (en) * | 2000-01-07 | 2003-10-14 | Samsung Electronics Co., Ltd. | CMOS integrated circuit devices and substrates having unstrained silicon active layers |
US6649480B2 (en) | 2000-12-04 | 2003-11-18 | Amberwave Systems Corporation | Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs |
US6940089B2 (en) * | 2001-04-04 | 2005-09-06 | Massachusetts Institute Of Technology | Semiconductor device structure |
JP2003078116A (ja) * | 2001-08-31 | 2003-03-14 | Canon Inc | 半導体部材の製造方法及び半導体装置の製造方法 |
WO2003025984A2 (en) | 2001-09-21 | 2003-03-27 | Amberwave Systems Corporation | Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same |
US20030230778A1 (en) * | 2002-01-30 | 2003-12-18 | Sumitomo Mitsubishi Silicon Corporation | SOI structure having a SiGe Layer interposed between the silicon and the insulator |
US7018910B2 (en) | 2002-07-09 | 2006-03-28 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Transfer of a thin layer from a wafer comprising a buffer layer |
US20040256671A1 (en) * | 2003-06-17 | 2004-12-23 | Kuo-Tai Huang | Metal-oxide-semiconductor transistor with selective epitaxial growth film |
US7045407B2 (en) * | 2003-12-30 | 2006-05-16 | Intel Corporation | Amorphous etch stop for the anisotropic etching of substrates |
US6881635B1 (en) * | 2004-03-23 | 2005-04-19 | International Business Machines Corporation | Strained silicon NMOS devices with embedded source/drain |
US6893936B1 (en) * | 2004-06-29 | 2005-05-17 | International Business Machines Corporation | Method of Forming strained SI/SIGE on insulator with silicon germanium buffer |
US7060579B2 (en) | 2004-07-29 | 2006-06-13 | Texas Instruments Incorporated | Increased drive current by isotropic recess etch |
US20060030093A1 (en) * | 2004-08-06 | 2006-02-09 | Da Zhang | Strained semiconductor devices and method for forming at least a portion thereof |
US7018901B1 (en) | 2004-09-29 | 2006-03-28 | Freescale Semiconductor, Inc. | Method for forming a semiconductor device having a strained channel and a heterojunction source/drain |
-
2006
- 2006-03-30 US US11/393,340 patent/US7494856B2/en not_active Expired - Fee Related
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2007
- 2007-02-22 EP EP07757316A patent/EP2005477A4/en not_active Withdrawn
- 2007-02-22 WO PCT/US2007/062559 patent/WO2007117775A2/en active Application Filing
- 2007-02-22 KR KR1020087023819A patent/KR20080108498A/ko not_active Application Discontinuation
- 2007-02-22 JP JP2009503114A patent/JP5203352B2/ja not_active Expired - Fee Related
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Also Published As
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JP2009532875A (ja) | 2009-09-10 |
WO2007117775A3 (en) | 2007-12-21 |
US20070238250A1 (en) | 2007-10-11 |
TW200802624A (en) | 2008-01-01 |
EP2005477A4 (en) | 2012-06-13 |
TWI447815B (zh) | 2014-08-01 |
KR20080108498A (ko) | 2008-12-15 |
US7494856B2 (en) | 2009-02-24 |
WO2007117775A2 (en) | 2007-10-18 |
EP2005477A2 (en) | 2008-12-24 |
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