JP5192825B2 - 半導体装置およびその製造方法、ならびに積層半導体装置の製造方法 - Google Patents
半導体装置およびその製造方法、ならびに積層半導体装置の製造方法 Download PDFInfo
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- JP5192825B2 JP5192825B2 JP2007554752A JP2007554752A JP5192825B2 JP 5192825 B2 JP5192825 B2 JP 5192825B2 JP 2007554752 A JP2007554752 A JP 2007554752A JP 2007554752 A JP2007554752 A JP 2007554752A JP 5192825 B2 JP5192825 B2 JP 5192825B2
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- semiconductor device
- connection terminal
- resin sealing
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- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
Claims (15)
- 基板上に半導体チップを搭載する工程と、
前記基板の前記半導体チップの搭載されるべき側に上部接続端子を形成する工程と、
前記上部接続端子の上面が露出するように、前記半導体チップおよび前記上部接続端子を封止し樹脂封止部を形成する工程と、
前記上部接続端子の上面が前記樹脂封止部の上面に設けられた開口部内において前記樹脂封止部の上面より低くなるように前記上部接続端子を成形する工程と、を有し、
前記開口部は、他の半導体装置に設けられた下部接続端子が嵌まり込むように設けられた半導体装置の製造方法。 - 前記上部接続端子を成形する工程は、前記上部接続端子に凸部を押圧する工程を含む請求項1記載の半導体装置の製造方法。
- 前記凸部を押圧する工程は、前記凸部を覆う前記樹脂封止部になるべき樹脂中に前記半導体チップおよび前記上部接続端子を配置する工程を含み、
前記樹脂封止部を形成する工程は、前記樹脂で前記半導体チップおよび前記上部接続端子を封止する工程を含む請求項2記載の半導体装置の製造方法。 - 前記上部接続端子を成形する工程は、前記上部接続端子の上面からブラスト処理する工程を含む請求項1記載の半導体装置の製造方法。
- 半導体チップを搭載する工程は複数の半導体チップを搭載する工程を含み、前記樹脂封止部を形成する工程は、前記複数の半導体チップを1つの前記樹脂封止部で封止する工程を含み、
前記基板および前記樹脂封止部を切断する工程を有する請求項1から4のいずれか一項記載の半導体装置の製造方法。 - 前記上部接続端子と上部半導体装置の下部接続端子とを接続する工程を有する請求項1から5のいずれか一項記載の半導体装置の製造方法。
- 前記上部接続端子上に絶縁膜を形成する工程を有する請求項6記載の半導体装置の製造方法。
- 基板と、
基板に搭載された半導体チップと、
前記基板の前記半導体チップの側に設けられた上部接続端子と、
前記上部接続端子が貫通し、前記半導体チップおよび前記上部接続端子を封止する樹脂封止部と、を具備し、
前記上部接続端子の上面は、前記樹脂封止部の上面よりも低くなるように、前記樹脂封止部の上面に設けられた開口部内に設けられ、
前記開口部は、他の半導体装置に設けられた下部接続端子が嵌まり込むように設けられた半導体装置。 - 前記上部接続端子の上面は前記上部接続端子間の前記樹脂封止部の上面よりも低く設けられた請求項8記載の半導体装置。
- 前記樹脂封止部は前記基板の全面に設けられた請求項8または9記載の半導体装置。
- 前記基板の前記半導体チップと反対の側に前記半導体チップおよび前記上部接続端子と接続する下部接続端子を具備する請求項8から10のいずれか一項記載の半導体装置。
- 前記上部接続端子上に絶縁膜を具備する請求項8から11のいずれか一項記載の半導体装置。
- 前記半導体チップは前記基板にフェースアップ実装されている請求項8から12いずれか一項記載の半導体装置。
- 前記半導体チップは前記基板にフェースダウン実装されている請求項8から12のいずれか一項記載の半導体装置。
- 請求項8〜14のいずれかに記載の半導体装置の前記開口部内に前記下部接続端子を嵌め込み、前記上部接続端子と前記下部接続端子とを接触させることにより、前記他の半導体装置と前記半導体装置とを電気的に接続する積層半導体装置の製造方法。
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