JP5173903B2 - 発光素子収納用パッケージおよび発光装置 - Google Patents
発光素子収納用パッケージおよび発光装置 Download PDFInfo
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- JP5173903B2 JP5173903B2 JP2009062964A JP2009062964A JP5173903B2 JP 5173903 B2 JP5173903 B2 JP 5173903B2 JP 2009062964 A JP2009062964 A JP 2009062964A JP 2009062964 A JP2009062964 A JP 2009062964A JP 5173903 B2 JP5173903 B2 JP 5173903B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Device Packages (AREA)
Description
っき層が露出するように被着されており、前記絶縁基体の下面に前記メタライズ配線層に電気的に接続された配線導体が形成されており、前記絶縁基体が、前記搭載部を有する下部絶縁層と、該下部絶縁層上に設けられており前記発光素子が収容される凹部を囲む内周面を有する上部絶縁層とを含んでおり、前記メタライズ金属層に電気的に接続された銀めっき層用導体が、前記絶縁基体において、前記配線導体、および前記メタライズ配線層に電気的に接続された金めっき層用導体よりも上方に設けられており、前記配線導体および前記金めっき層用導体とは異なる高さ位置において前記絶縁基体の側面に導出されており、前記メタライズ金属層が、前記上部絶縁層の前記内周面に形成されており、前記銀めっき層用導体が、前記下部絶縁層と前記上部絶縁層との間に設けられており、前記金めっき層用導体が、前記下部絶縁層の内部に形成されており、前記銀めっき層用導体とは異なる高さ位置に設けられている。
また、金めっき層は発光素子3が発光する光を反射するので、搭載部2より発光素子3が発光する光が絶縁基体1下面側に漏れるのを防止できる。よって、導体層から成る搭載部2の露出する表面に、厚さ1〜10μm程度のニッケルめっき層と厚さ0.1〜3μm程度の金めっき層9とが、電解めっき法や無電解めっき法により順次被着されていることがより好ましい。
3μmを超えると、凹部4内に収容された発光素子3の光が散乱し、反射光を高い反射率で外部に均一に放射することが困難になる。
2:搭載部
3:発光素子
4:凹部
5a,5b:配線層
9:金めっき層
10:銀めっき層
Claims (2)
- セラミックスからなる絶縁基体の上面に発光素子の搭載部が設けられ、
該搭載部に前記発光素子の電極が電気的に接続されるメタライズ配線層が形成されており、前記メタライズ配線層は、その表面に金めっき層が露出するように被着され、
前記搭載部の周囲にメタライズ金属層が形成されており、前記メタライズ金属層は、その表面に銀めっき層が露出するように被着されており、
前記絶縁基体の下面に前記メタライズ配線層に電気的に接続された配線導体が形成されており、
前記絶縁基体が、前記搭載部を有する下部絶縁層と、該下部絶縁層上に設けられており、前記発光素子が収容される凹部を囲む内周面を有する上部絶縁層とを含んでおり、
前記メタライズ金属層に電気的に接続された銀めっき層用導体が、前記絶縁基体において、前記配線導体、および前記メタライズ配線層に電気的に接続された金めっき層用導体よりも上方に設けられており、前記配線導体および前記金めっき層用導体とは異なる高さ位置において前記絶縁基体の側面に導出されており、
前記メタライズ金属層が、前記上部絶縁層の前記内周面に形成されており、
前記銀めっき層用導体が、前記下部絶縁層と前記上部絶縁層との間に設けられており、
前記金めっき層用導体が、前記下部絶縁層の内部に形成されており、前記銀めっき層用導体とは異なる高さ位置に設けられていることを特徴とする発光素子搭載用パッケージ。 - 請求項1に記載の発光素子搭載用パッケージと、
前記搭載部に搭載されるとともに前記メタライズ配線層に電極が電気的に接続された発光素子と、
該発光素子を覆う透明樹脂とを具備していることを特徴とする発光装置。
Priority Applications (1)
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JP2009062964A JP5173903B2 (ja) | 2003-02-25 | 2009-03-16 | 発光素子収納用パッケージおよび発光装置 |
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JP2003048084 | 2003-02-25 | ||
JP2003048084 | 2003-02-25 | ||
JP2009062964A JP5173903B2 (ja) | 2003-02-25 | 2009-03-16 | 発光素子収納用パッケージおよび発光装置 |
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JP2003116401A Division JP2004319939A (ja) | 2003-02-25 | 2003-04-21 | 発光素子収納用パッケージおよび発光装置 |
Publications (2)
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JP2009135536A JP2009135536A (ja) | 2009-06-18 |
JP5173903B2 true JP5173903B2 (ja) | 2013-04-03 |
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JP2009062964A Expired - Fee Related JP5173903B2 (ja) | 2003-02-25 | 2009-03-16 | 発光素子収納用パッケージおよび発光装置 |
JP2009062963A Pending JP2009135535A (ja) | 2003-02-25 | 2009-03-16 | 多数個取り基板、パッケージおよび発光装置 |
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Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2012074483A (ja) * | 2010-09-28 | 2012-04-12 | Toyoda Gosei Co Ltd | 発光素子収納用パッケージ |
CN102569540B (zh) * | 2010-12-25 | 2014-08-27 | 展晶科技(深圳)有限公司 | 发光二极管封装结构的制造方法 |
KR101764108B1 (ko) * | 2011-03-25 | 2017-08-02 | 엘지이노텍 주식회사 | 발광소자 패키지 및 조명시스템 |
BR102015027316B1 (pt) | 2014-10-31 | 2021-07-27 | Nichia Corporation | Dispositivo emissor de luz e sistema de lâmpada frontal de farol de acionamento adaptativo |
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JP2574388B2 (ja) * | 1988-05-10 | 1997-01-22 | 松下電器産業株式会社 | 発光ダイオードおよびその電極の形成方法 |
JP2001144333A (ja) * | 1999-11-10 | 2001-05-25 | Sharp Corp | 発光装置とその製造方法 |
JP4432275B2 (ja) * | 2000-07-13 | 2010-03-17 | パナソニック電工株式会社 | 光源装置 |
JP4737842B2 (ja) * | 2001-01-30 | 2011-08-03 | 京セラ株式会社 | 発光素子収納用パッケージの製造方法 |
JP2003046137A (ja) * | 2001-07-27 | 2003-02-14 | Matsushita Electric Ind Co Ltd | 半導体発光装置 |
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- 2009-03-16 JP JP2009062964A patent/JP5173903B2/ja not_active Expired - Fee Related
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JP2009135535A (ja) | 2009-06-18 |
JP2009135536A (ja) | 2009-06-18 |
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