JP5167203B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5167203B2 JP5167203B2 JP2009153458A JP2009153458A JP5167203B2 JP 5167203 B2 JP5167203 B2 JP 5167203B2 JP 2009153458 A JP2009153458 A JP 2009153458A JP 2009153458 A JP2009153458 A JP 2009153458A JP 5167203 B2 JP5167203 B2 JP 5167203B2
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
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Description
図1は本発明の実施の形態1の半導体装置の構造の一例を封止体を透過して示す部分平面図、図2は図1に示す半導体装置の構造の一例を示す断面図、図3は図1に示す半導体装置のシステムの一例を示すブロック構成図、図4は図1に示す半導体装置の組み立てに用いられるリードフレームの構造の一例を示す断面図、図5はダイボンディング完了時の構造の一例を示す断面図、図6はワイヤボンディング完了時の構造の一例を示す断面図、図7は樹脂封止完了時の構造の一例を示す断面図、図8はワイヤボンディングにおけるボンディング前の構造の一例を示す拡大部分平面図、図9はワイヤボンディングにおけるチップ間接続後の構造の一例を示す拡大部分平面図、図10はワイヤボンディングにおける第2のチップ−リード間接続後の構造の一例を示す拡大部分平面図、図11はワイヤボンディングにおける第1のチップ−リード間接続後の構造の一例を示す拡大部分平面図、図12はワイヤボンディングにおけるボンディング順の一例を示すフロー図と断面図、図13はワイヤボンディングにおける変形例のボンディング順を示すフロー図と断面図、図14は図1に示す半導体装置におけるチップ配置レイアウトの一例を示す平面図、図15および図16はそれぞれ実施の形態1の半導体装置の組み立てに用いられるリードフレームの変形例の構造を示す平面図、図17は本発明の実施の形態1の変形例の半導体装置の構造を示す断面図、図18は本発明の実施の形態1の変形例の半導体装置の組み立てにおけるワイヤボンディング時の構造を示す断面図である。
図19は本発明の実施の形態2の半導体装置の構造の一例を示す断面図、図20は図19に示す半導体装置の構造の一例を示す裏面図、図21は図19に示す半導体装置におけるリード配列と外部端子配列の関係の一例を示す部分平面図である。
Flat Non−leaded Package)型にしたことである。
図22は本発明の実施の形態3の半導体装置の全体構成を示す概念図、図23は本実施の形態3の半導体装置において、ASICとSDRAMのパッケージ内の配置を示す概念図である。
2 SDRAM(第2の半導体チップ)
2a 主面
2b 裏面
2c パッド(電極)
3 マイコンチップ(第1の半導体チップ)
3a 主面
3b 裏面
3c パッド(電極)
3d CPU
3e ロジック
3f アナログ
3g 内部メモリ
3h BIST回路(テスト回路)
3i メモリ接続用入出力回路
3j 外部接続用入出力回路
4 銀ペースト
5 リードフレーム
5a インナリード(リード)
5b アウタリード(リード)
5c タブ(チップ搭載部)
5d 第1のチップ搭載部
5e 第2のチップ搭載部
5f スリット
5g 吊りリード
5h 小タブ(第1のチップ搭載部)
5i リード部(リード)
5j 突出部
6a 第1のワイヤ
6b 第2のワイヤ
6c 第3のワイヤ
7 封止体
7a 裏面
8 金バンプ
9 ヒートステージ(加熱治具)
9a 平坦面
9b 凹部
9c 凸部
9d 排気口
10,11 SIP(半導体装置)
12 バンプ電極
13 補強用端子
100 ASIC(第1半導体チップ)
101 SDRAM(第2半導体チップ)
102 SIP
103 アナログ
104 内部メモリ
105 CPU
106 ロジック部
107 IO部
108 MBIST
109 SDRAMBIST
110 制御信号入力付き入出力バッファ
111 データ信号
112 アドレス信号
113 制御信号
114 クロック信号
115 端子(第1端子)
116 端子(第2端子)
117,123,127 出力バッファ
118,128 入力バッファ
119 プルアップ回路
120 スイッチ
121 FF
124 テスト回路
125,126 ピン
129 GND
130 イネーブルB/SR(バウンダリスキャンレジスタ)
131 アウトプットB/SR
132 インプットB/SR
Claims (13)
- チップ搭載部と、
第1辺、前記第1辺と交差する第2辺、および複数の第1パッドが配置された表面を有し、前記チップ搭載部上に搭載された第1半導体チップと、
第3辺、前記第3辺と交差し、前記第3辺よりも長さが短い第4辺、および複数の第2パッドが配置された表面を有し、前記チップ搭載部上に前記第1半導体チップの前記第1辺と前記第3辺とが対向するように前記第1半導体チップの横に並べて搭載された第2半導体チップと、
前記チップ搭載部の周囲に配置された複数のリードと、
前記第1半導体チップの前記複数の第1パッドの一部と前記第2半導体チップの前記複数の第2パッドの一部とを電気的に接続する第1ワイヤと、
前記第1半導体チップの前記複数の第1パッドの一部と前記複数のリードの一部とを電気的に接続する複数の第2ワイヤと、
前記チップ搭載部、前記第1半導体チップ、前記第2半導体チップ、前記複数のリードの一部、前記第1ワイヤ、および前記複数の第2ワイヤを封止する封止体と、を有する半導体装置であって、
前記第2半導体チップの前記第4辺が延在する方向に平行な方向において、前記第1半導体チップの平面方向の中心と前記半導体装置の平面方向の中心とのずれ量の絶対値は、前記第2半導体チップの前記第4辺の長さの半分よりも短いことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第1半導体チップの前記第1辺の長さは、前記第2辺の長さよりも長いことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第1半導体チップは四角形状であって、
前記第1半導体チップの前記複数の第1パッドの内、前記複数の第2ワイヤが接続されたパッドは、前記第1半導体チップの各辺に沿って配置されていることを特徴とする半導体装置。 - 請求項3に記載の半導体装置において、
前記第1半導体チップの前記複数の第1パッドの内、前記第1辺に沿って配置されたパッドに接続された前記第2ワイヤの一部は、平面視において前記第2半導体チップと重なっていることを特徴とする半導体装置。 - 請求項3に記載の半導体装置において、
前記半導体装置の外観形状はQuad Flat Packageであることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第1半導体チップの前記表面とは反対側の裏面は、その一部が前記封止体の一部と密着していることを特徴とする半導体装置。 - 請求項6に記載の半導体装置において、
前記チップ搭載部の前記第1半導体チップが搭載される部分には開口部が形成されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第2半導体チップの前記表面とは反対側の裏面は、その一部が前記封止体の一部と密着していることを特徴とする半導体装置。 - 請求項8に記載の半導体装置において、
前記第2半導体チップの一部は、前記チップ搭載部から迫り出していることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第1および第2半導体チップのいずれか一方もしくは両方が、銀ペーストを介して前記チップ搭載部に搭載されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記チップ搭載部は、銅合金からなる薄板材により形成されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記封止体は、熱硬化性のエポキシ樹脂によって形成されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第1半導体チップは演算処理機能を備え、前記第2半導体チップは、メモリ回路を有することを特徴とする半導体装置。
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