CN107706170A - 垂直半导体装置 - Google Patents

垂直半导体装置 Download PDF

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Publication number
CN107706170A
CN107706170A CN201610647054.6A CN201610647054A CN107706170A CN 107706170 A CN107706170 A CN 107706170A CN 201610647054 A CN201610647054 A CN 201610647054A CN 107706170 A CN107706170 A CN 107706170A
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China
Prior art keywords
bare chip
semiconductor bare
major surfaces
naked core
semiconductor
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Pending
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CN201610647054.6A
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English (en)
Inventor
S.乌巴德许阿尤拉
叶宁
邱进添
H.塔基娅
陈鹏
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SanDisk Information Technology Shanghai Co Ltd
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SanDisk Information Technology Shanghai Co Ltd
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Application filed by SanDisk Information Technology Shanghai Co Ltd filed Critical SanDisk Information Technology Shanghai Co Ltd
Priority to CN201610647054.6A priority Critical patent/CN107706170A/zh
Priority to US15/620,331 priority patent/US10325881B2/en
Priority to KR1020170077899A priority patent/KR101903541B1/ko
Publication of CN107706170A publication Critical patent/CN107706170A/zh
Pending legal-status Critical Current

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Abstract

本发明公开了一种垂直地安装在介质(诸如印刷电路板，PCB)上的半导体装置及其制造方法。该半导体装置包含具有接触垫的半导体裸芯的堆叠体，该接触垫延伸到对齐在该堆叠体的一个侧面上的裸芯的有效边缘。该裸芯的有效边缘固定到该PCB，并且在有效边缘处的接触垫电耦合到PCB。该配置提供在装置中的半导体裸芯的最佳的、高密度的配置，可以在没有基板、不交错半导体裸芯、不使用引线键合体的情况下，将大量的半导体裸芯安装到并且直接电耦合到该PCB。

Description

垂直半导体装置
技术领域
本发明涉及一种半导体装置。
背景技术
便携消费性电子产品需求的强劲增长驱使对高容量存储装置的需求。非易失性半导体存储器装置(诸如闪存存储卡)逐渐被广泛使用，以满足数字化信息存储和交换的日益增长的需求。它们的便携性、多功能性和坚固设计，连同它们的高可靠性和大容量，已使得这样的存储器装置理想地应用在各种电子装置中，包含例如数码照相机、数码音乐播放器、视频游戏机、PDA和移动电话。
尽管已知多种不同的封装配置，闪存储存卡通常可以被制造为***级封装(SiP)或多芯片模块(MCM)，其中多个裸芯被安装并且互连在小足印(footprint)基板上。基板通常可以包含刚性的、介电基部，该基部具有蚀刻在一个侧面或两个侧面上的导电层。电连接形成在裸芯和(多个)导电层之间，并且(多个)导电层提供用于将裸芯连接到主机装置的电导线结构。裸芯与基板之间的电连接一经建立，组装件则典型地被封裹在提供保护性封装体的模塑料中。
常规半导体封装体20的截面侧视图和俯视图如图1和图2所示。典型的封装体包含被支承在基板26上的多个半导体裸芯，诸如闪存裸芯22和控制器裸芯24。基板26包含用于在半导体裸芯22，24以及设置封装体的主机装置之间传输信号的通孔、电迹线和接触垫。裸芯接合垫28可以形成在半导体裸芯22、24的表面上，以通过将各自的裸芯接合垫与接触垫之间的引线键合体32固定，来将半导体裸芯电耦合到基板。全部的电连接一经建立，裸芯和引线键合体可以被包封在模塑料34中，以密封封装体，并且保护裸芯和引线键合体。
在更小的封装体中提供更大的存储容量的动机始终存在的情况下，需要重新思考基板的使用以及如何在半导体封装体之内布置半导体裸芯。
发明内容
概括起来，本技术的示例涉及一种半导体装置，包括：用于安装到介质上的半导体装置，其包括：多个半导体裸芯，每个半导体裸芯包括：主要表面，与主要表面成非零度角的有效边缘，以及形成在主要表面中的电接触，与半导体裸芯的有效边缘相邻，该多个半导体裸芯配置为表面安装到介质，每个半导体裸芯的有效边缘面对介质有效。
在其他示例中，本技术涉及一种半导体装置，包括：多个半导体裸芯，每个半导体裸芯包括：具有长度和宽度的第一主要表面；具有长度和宽度的第二主要表面，其长度和宽度对应于第一主要表面的长度和宽度；有效边缘，其在第一主要表面与第二主要表面之间延伸；电接触，其形成在第一主要表面中，与半导体裸芯的有效边缘相邻，并且在长度方向上延伸；以及裸芯贴附膜(DAF)，其在第二主要表面上，用于将第二主要表面固定到另一表面，DAF延伸跨过第二主要表面的宽度，并且小于第二主要表面的整个长度；堆叠为块的多个半导体裸芯，在每个半导体裸芯上被DAF分隔开，并且DAF在块中彼此相邻的第一半导体裸芯与第二半导体裸芯之间的电接触之上留下空间。
在另一个示例中，本技术涉及一种电子部件，包括：多个半导体裸芯，每个半导体裸芯包括：第一主要表面，第二主要表面，在第一与第二主要表面之间延伸的有效边缘，以及形成在第一主要表面中的电接触，其与半导体裸芯的有效边缘相邻；以及包括多个导电接触的介质，该导电接触在介质的表面上方延伸，多个半导体裸芯表面安装到介质，通过多个半导体裸芯的有效边缘面对介质有效，并且多个电接触电耦合到多个导电接触。
在另一个示例中，本技术涉及一种电子部件，包括：电子部件，其包括：多个半导体裸芯，每个半导体裸芯包括：第一主要表面，第二主要表面，在第一主要表面与第二主要表面之间延伸的有效边缘，以及形成在第一主要表面中的电接触装置，其与半导体裸芯的有效边缘相邻；以及包括多个导电接触装置的印刷电路板装置，该多个导电接触装置在印刷电路板装置的表面上方延伸，多个半导体裸芯被表面安装到印刷电路板装置，多个半导体裸芯的有效边缘面对介质有效，并且多个电接触装置电耦合到多个导电接触装置。
附图说明
图1是包含安装在基板上的半导体裸芯的常规半导体装置的现有技术的边视图。
图2是包含安装在基板上的半导体裸芯的常规半导体装置的现有技术的俯视图。
图3是根据本发明的实施例形成半导体裸芯的流程图。
图4是示出晶片的第一主要表面的半导体晶片的正视图。
图5是来自晶片的单个半导体裸芯的正视立体图。
图6是来自晶片的单个半导体裸芯的正视立体图，示出延伸到某位置的裸芯接合垫，该位置一经将半导体裸芯从晶片切片，将成为半导体裸芯的边缘。
图7是半导体晶片的后视图，示出包含DAF层的晶片的第二主要表面。
图8是来自包含DAF层的晶片的单个半导体裸芯的后视立体图。
图9是来自包含DAF层的晶片的单个半导体裸芯的正视立体图。
图10是从晶片切片的半导体裸芯的堆叠体的立体图。
图11是印刷电路板的立体图，该印刷电路板上可以布置半导体裸芯的堆叠体。
图12是印刷电路板的立体图，该印刷电路板上垂直地布置半导体裸芯的堆叠体。
图13是印刷电路板的立体图，该印刷电路板上布置半导体裸芯的堆叠体，树脂底部填充该半导体裸芯的堆叠体中的间隙。
具体实施方式
现将参考附图描述本技术，其在实施例中，涉及垂直地安装在介质(诸如印刷电路板，PCB)上的半导体装置。半导体装置包括具有接触垫的半导体裸芯的堆叠体，该接触垫延伸到对齐到堆叠体一个侧面上的裸芯的有效边缘。裸芯的有效边缘被固定到PCB，并且在有效边缘处的接触垫被电耦合到PCB。此配置提供在装置中半导体裸芯的最佳的、高密度的布置，其中可以在没有基板、不交错半导体裸芯、不使用引线键合体的情况下，将大量的半导体裸芯安装并且直接电耦合到PCB。
应当理解，本发明可以以多种不同形式实施，而不应理解为限于本文所阐述的实施例。相反地，提供这些实施例使得本公开透彻而完整，并且将本发明充分地传达给本领域技术人员。事实上，本发明意图涵盖这些实施例的替代、修改和等同，这些实施例的替代、修改和等同被包含在由所附权利要求限定的本发明的范围和精神之内。此外，在本发明的以下详细描述中，提出许多具体细节以便提供本发明的透彻理解。然而，对本领域普通技术人员将清楚的是，本发明可以在没有这些具体细节的情况下来实践。
如本文中可能使用的术语“顶部”和“底部”、“上部”和“下部”以及“垂直”和“水平”以及其形式，仅为示例和说明性的目的，并非意味着限制本发明的描述，因为所引用的项可以在位置和取向上交换。同样，如本文中使用的术语“实质上”和/或“大约”是指对于给定的应用，具体的尺寸或参数可以在可接受的制造公差中变动。在一个实施例中，可接受的制造公差是±25％。
现将参考图3的流程图和图4–图13的视图来进行解释本发明的实施例。初始地参考图3的流程图，半导体晶片100可以开始于作为晶片材料的铸锭，其可以在步骤200中形成。在一个示例中，形成晶片100的铸锭可以是单晶硅，其根据直拉法(Czochralski,CZ)工艺或浮区法(floating zone，FZ)工艺两者中的一个生长。然而，晶片100在其他实施例中可以由其他材料且通过其他的工艺形成。
在步骤204中，半导体晶片100可以被从铸锭切割并且在第一主要表面102(图4)和与表面102相反的第二主要表面104(图7)两者上都抛光，以提供光滑的表面。在步骤206中，第一主要表面102可以经受各种处理步骤，以将晶片100分为各自的半导体裸芯106(其中之一如图4所示)，并且在第一主要表面102上和第一主要表面102中形成各自的半导体裸芯106的集成电路。这些各种处理步骤可以包含沉积金属接触的金属化步骤，该金属接触用于与集成电路往复传输信号。电接触可以包含暴露在第一主要表面102上的裸芯接合垫108(其中之一在图4和图5的每一个中编号)。示出的接合垫108的数量是为了简单，而每个裸芯105可以包含远多于所示的裸芯接合垫。在实施例中，裸芯接合垫108可以由铝或其合金形成，但在其他实施例中垫108可以由其他材料形成。在实施例中，集成电路可以作为NAND闪存半导体裸芯运行，但可以预期其他类型的集成电路。
在下面解释的切片之后，若干半导体裸芯106可以沿着边缘110(本文中称为有效边缘110)被堆叠，并且电连接到诸如PCB的介质诸如(图5)。有效边缘可以相对于第一主要表面成非零度角(典型地成90°或大约90°)形成。为了允许有效边缘处的电连接，在步骤208中，裸芯接合垫108可以在有效边缘110处延伸或以其他方式在有效边缘110处形成。在一个实施例中，裸芯接合垫108可以通过具有电迹线112的重新分配层延伸到并且终止于每个半导体裸芯106的有效边缘110(图6)，镍和金的该电迹线112从每个裸芯接合垫108延伸到有效边缘110。
在一个示例中，可以通过在晶片100的第一主要表面102之上首先施加介电材料的钝化层来形成迹线112。然后可以在光刻工艺中蚀刻钝化层以暴露每个裸芯接合垫108。然后可以在钝化层之上施加各种金属层，例如通过溅射或其他薄膜沉积工艺。金属层可以例如包含钛、铜、镍和金。应理解的是，在其他实施例中，可以使用少于全部这些金属层，或者可以使用其他的或附加的金属层。然后可以光刻法处理和蚀刻金属层，以限定迹线112，其从裸芯接合垫108延伸到每个半导体裸芯的有效边缘110。迹线112可以从接合垫108直线延伸出来(垂直于接合垫108的行)。然而在其他实施例中，迹线可以将接合垫108以图案重分配到有效边缘110，该图案不从接合垫直线延伸出来。
应理解的是，在其他实施例中，从裸芯接合垫108延伸到有效边缘110的迹线112可以由其他材料或通过其他工艺形成。此外，当形成迹线112时，裸芯尚未被从晶片切片，且各自的裸芯的有效边缘110尚不存在。迹线112形成在晶片上，以从裸芯接合垫108延伸一定距离，使得当从晶片切片裸芯时，(下面解释的)切割机制将沿着它们的长度割断迹线112，以留下暴露在有效边缘110处的迹线112的端部。应理解的是，在迹线112终止得足够接近有效边缘，从而在下面解释的回流工艺中在PCB上与焊料球连接前提下，迹线112实际上可以终止于接近有效边缘110，而并不完全在有效边缘110处。
在其他实施例中，迹线112可以完全省去。在这样的实施例中，切割机构可以将裸芯接合垫自身割断，以留下暴露在有效边缘110处的裸芯接合垫的一部分。
在步骤212中，晶片可以针对第二主要表面104经受背面研磨工艺，以将晶片从例如大约775微米(μm)减薄至大约25μm到100μm的范围中。应理解的是，在其他实施例中，在背面研磨步骤之后，晶片100可能比此范围更薄或更厚。
在步骤214中，可以将裸芯贴附膜(DAF)114的层施加到晶片100的第二主要表面104，如图7至图9所示。根据本技术的一方面，可以以如图7所示的条状图案将DAF 114施加到晶片100，该条状图案被不具有DAF 114的裸露间隔116分隔开。以受控方式施加或处理DAF 114，使得晶片100的第二主要表面104上的裸露间隔116与晶片100的第一主要表面102上的迹线112对齐。如本文后面解释的，在将半导体裸芯106切片之后，可以将它们堆叠在一起，其中一个裸芯106的第二主要表面104上的DAF 114靠着下一个裸芯106的第一主要表面102。提供DAF 114中的裸露间隔116，使得一个裸芯的DAF 114不覆盖下一个相邻裸芯的迹线112。
如图8和图9所示，可以提供裸露间隔116，使得当将半导体裸芯106从晶片100切片时，每个裸芯具有距不含DAF 114的有效边缘110距离d的裸露间隔。距离d至少等长于迹线112的长度L。可想而知，在其他实施例中，在如下面解释的迹线112的足够部分被留下暴露以用于连接到PCB的前提下，距离d小于长度L。
可以将DAF 114施加到整个第二主要表面104之上，并且之后选择性地移除以在合适位置中限定裸露间隔116。在其他的实施例中，DAF 114可以被施加在限定裸露间隔116的条带中。作为一个示例，DAF 114可以是来自汉高公司(Henkel Corp，在美国加利福尼亚州具有办公室)的8988UV环氧树脂。
DAF 114可以具有3μm至30μm的厚度，但是其在其他的实施例中可以比该厚度更薄或更厚。如下面解释的，堆叠的半导体裸芯(被DAF 114的厚度彼此间隔开)的块可以被安装到PCB上，使得每个裸芯上的迹线112与提供在PCB上的焊料球对齐。DAF 114的厚度限定堆叠体中的半导体裸芯之间的间隔，并且可以提供DAF的厚度以确保每个裸芯之间的间隔与每行焊料球的间隔匹配。在上面的描述中，在施加DAF 114之前形成迹线112。应理解的是，这些步骤在其他实施例中可以转换。
接下来在步骤216中，可以将半导体裸芯106从晶片100切片。在一个实施例中，可以使用隐形激光(stealth lasing)工艺将晶片100切片。晶片100可以被支承在夹盘(chuck)或其他支承表面(未示出)上，使集成电路在面对支承表面的第一主要表面102和背对支承表面的第二主要表面104上。然后激光器可以在传输穿过晶片100的第二主要表面104的波长处(例如在红外波长或近红外波长处)发射脉冲激光束。可以使用光学***将脉冲激光束聚焦到晶片的表面104之下的点，该光学***例如包含一个或多个准直透镜(collimating lens)。当激光束在焦点处达到峰值功率密度时，晶片吸收能量，并且在晶片的表面之下形成定位孔(pinpoint hole)。
激光器可以沿晶片100的划线移动，并且在若干点处激发，使得若干紧密布置的定位孔形成在晶片的中间深度(在晶片的第一主要表面102和第二主要表面104之间)处。定位孔的行和列限定要从晶片100切片的每个半导体裸芯106的最终形状。激光可以在单一深度处形成定位孔的单个层，或者在多个深度处形成定位孔的多个(两个或更多)层。
定位孔可以在晶片中产生裂缝，其向着第一主要表面102和第二主要表面104传播，以完成晶片的切片。在其他实施例中，在激光产生定位孔之后，可以在晶片中引起附加的机械应力以促进定位孔裂缝的传播。例如，在激光工艺之后，晶片可以被翻面，并且将第二主要表面104固定在胶带上。然后沿着正交轴拉伸胶带。这样在晶片内部产生应力，其导致定位孔处的裂缝传播到晶片100的第一主要表面102和第二主要表面104，以完成晶片100的切片。拉伸还在胶带上展开切片的半导体裸芯106。取放机器人可以将切片的半导体裸芯106转移到支承表面，以进行如下面解释的进一步处理。可替换地，在切片之后，取放机器人可以将半导体裸芯直接转移到如下面解释的PCB之上。
隐形激光以及随后的裂缝的传播可以导致晶片100沿穿过迹线112的线(或在不具有迹线112的实施例中穿过裸芯接合垫108)的切片。特别地，沿着与迹线112或裸芯接合垫108交叉的线施加激光，使得随着裂缝传播到第一主要表面102，迹线或接合垫在有效边缘110处被割断。从而，如图9所示的切片的半导体裸芯106，迹线112终止于每个半导体裸芯的有效边缘110处。在其他实施例中，可以通过除了隐形激光外的其他技术将晶片100切片。这样的附加的切片技术包含刀片切割(blade cutting)和水射流切割(waterjet cutting)。
可以根据上面解释的步骤200-216制造多个晶片100。其后，在如图10所示的步骤218中，取放机器人可以将来自相同晶片或不同晶片的半导体裸芯106拾取，并且将他们堆叠为半导体裸芯106的堆叠块130。堆叠块130在本文中也可以称为半导体装置130。裸芯106可以被水平地堆叠为块130。即，第一裸芯的DAF 114可以被支承在中间支承台132的水平的x-y平面上，并且块130中其余的裸芯106可以在z方向上在其上水平地向上堆叠。每个裸芯可以被DAF 114的厚度彼此分隔开，如图10所示。迹线112终止处的有效边缘110可以沿着堆叠块130共有的侧面对齐。
在实施例中，单个堆叠块130中的半导体裸芯106的数量可以变化，包含例如2、4、8、16、32、64或128个半导体裸芯。在其他实施例中，堆叠块130中可以有更多或其他数量的半导体裸芯。
在实施例中，堆叠块130一经形成，其可以作为块被转移到诸如图11所示的PCB140的介质之上。PCB 140可以是例如高密度互联(HDI)PCB。在其他实施例中，可能是其他PCB和其他介质，诸如基板。PCB 140可以包含细间距焊料球142的图案。焊料球的图案布置为若干行(一行指定为142a)。在实施例中，至少有与块130中的裸芯一样多的焊料球的行142a(在y方向上)。每一行142a之中，至少有与块130中的裸芯106上的迹线112一样多的焊料球(在x方向上)。可以使用各种技术(包含例如柱凸块制作(stud bumping))以所需的图案将焊料球142施加到PCB 140。PCB 140还可以包含电导体144，用于将信号和其他电压传输到焊料球142或从焊料球142传输。示出的电导体144的图案仅是示例性的，并且在其他实施例中可以变化。
尽管在图11中示出了焊料球，应理解的是，在其他实施例中，可以使用焊膏或其他导电接触代替焊料球。导电接触可以在PCB 140的表面之上充分地延伸，以使得导电接触一经回流，就粘接到迹线112。
在如图12所示的步骤222中，半导体装置130可以被垂直地表面安装在PCB 140上。即，装置130可以被表面安装，装置130中每个半导体裸芯106的有效边缘110和迹线112的端部抵靠(或非常接近于)PCB 140。装置130中的裸芯106的主要表面位于垂直于x-y平面中的PCB 140表面的x-z平面中(应理解的是，为易于理解，提供x-y-z轴，而在其他实施例中，裸芯和PCB可以位于其他平面中)。
如指出的，焊料球142的行142a之间在y方向上的间隔与装置130中的每个半导体裸芯106中的迹线112之间的间隔相匹配。当装置130被降低到PCB 140之上时，焊料球实际上可以将装置130中各自的裸芯106在焊料球142的行上在y方向上居中。如上面指出的，装置130中每个半导体裸芯106之间的间隔可以是3μm到30μm，但是在其他实施例中，该间隔可以比此更大或更小。
x方向上的每一行142a中的焊料球142之间的间隔也与装置130中的每个裸芯106上的迹线112之间的间隔匹配。如指出的，迹线112的数量以及相应的焊料球142的数量是示例性的，而可以有更少的或(很可能是)更多得多的迹线112以及在焊料球的行中的焊料球142。从而，一经被降低到PCB之上并定位，半导体装置130中的每个裸芯106上的每个迹线112可以与焊料球142对齐并且抵靠焊料球142。
在上面描述的实施例中，半导体裸芯106在焊料球142的每个行之间被组装到块130之中，并且然后作为块130安装到PCB 140上。在其他实施例中，第一单独的半导体裸芯106可以被垂直地设置在PCB 140上，其有效边缘110抵靠PCB 140。然后第二半导体裸芯106可以抵靠第一半导体裸芯被垂直地堆叠，其有效边缘110在PCB 140上。然后第三半导体裸芯可以抵靠第二半导体裸芯被垂直地堆叠在PCB上，并且以此类推直到块130中的全部半导体裸芯被垂直地堆叠在PCB 140上。半导体裸芯106也可以在(例如，四个或八个裸芯的)子块中组装到一起，在连续的步骤中，子块被安装到PCB 140之上，直到完成完整的块130。
在步骤226中，半导体装置130和PCB 140可以被加热，以将抵靠迹线112中的每一个的焊料球回流，来融化抵靠迹线112中的每一个并且与迹线112中的每一个良好电接触的焊料球。随着焊料球抵靠迹线112熔化、回流和然后固化，表面粘接和毛细作用(wicking)将确保与抵靠迹线112的焊料球的良好接触。然而，在其他实施例中，支承臂(未示出)可以在箭头A的方向上施加抵靠块130的轻力，以在回流过程中支承块130，并且推着迹线112抵靠焊料球142。
在步骤226的回流工艺之后，在PCB 140上的半导体装置130的制造可能完成。然而，在其他实施例中，可以在底部填充步骤230中将环氧树脂或其他树脂或聚合物146施加到装置130中的未覆盖的(前方)裸芯上的迹线112，并且注入到内部裸芯上的DAF 114和PCB140之间的间隔之中。聚合物146可以被作为液体施加，然后其固化为固体层。该底部填充步骤保护每个迹线112处的电连接，并且还将半导体装置130固定到PCB 140之上。各种聚合物可以被用作聚合物146，但在实施例中，其可以是来自汉高公司(在美国加利福尼亚州具有办公室)的Hysol环氧树脂。
在底部填充步骤230之后，PCB 140上的半导体装置130可以在步骤232中经受最终阶段测试。一种这样的测试可以是坠落测试，其中装置130和PCB 140从一定高度坠落，然后测试运行。另一个这样的测试可以是热循环测试，其中装置130和PCB 140在高温(例如，85℃或125℃)到低温(-40℃)之间被循环高达1000次，并且然后测试运行。可以进行其他测试。在最终阶段测试中，底部填充聚合物146可以保护装置130不受坠落测试的冲击，以及在热循环测试过程中由于裸芯106和PCB 114之间的热不匹配的应力。
相似地，可以在制造工艺的更早的阶段测试裸芯106，在组装到块130中之前或之后，以及在回流之前和/或之后。如果半导体裸芯被识别为有缺陷或无功能，通过半导体装置130的***级编程，可以将该裸芯从半导体装置130的运行排除。
垂直半导体装置130和PCB 140可以一同包括可以被实现在主机装置中的电子部件。根据本技术的垂直半导体装置130提供若干优点。例如，它以类同于常规水平倒装芯片的方式贴附到PCB 140上的焊料球的阵列。然而，在常规水平倒装芯片可以将单个裸芯固定到焊料球的阵列的情况下，垂直半导体装置130可以固定垂直地定向的半导体裸芯的整个块。
此外，在不需要常规地用来在PCB和半导体裸芯之间通信信号的基板的情况下，垂直半导体装置130可以直接耦合到PCB。此外，垂直半导体装置130可以在不使用引线键合体的情况下直接耦合。引线键合体增加附加的成本和处理步骤。此外，由于性能问题(诸如随着堆叠体中裸芯数量的增加而增加的噪音、电短路和寄生RCL)，引线键合到裸芯堆叠体中的裸芯限制了堆叠体中可以提供的裸芯的数量。在本技术中，块中的每个裸芯被直接固定到PCB，并且可以在不增长任何上面提及的性能问题的情况下，将裸芯加入到块。
此外，垂直半导体装置130提供在最小化的整体形状系数中大量的裸芯。裸芯可以布置在块之内并耦合到PCB，而不需要在块内交错裸芯，或在裸芯之间提供间隔层，另外需要该两种配置中的一种以允许引线键合体接入到(access to)接合垫。交错裸芯、或通过间隔层分隔裸芯，增加半导体装置的形状系数。垂直半导体装置130具有最小化的整体尺寸，同时块130具有不大于裸芯106和DAF 114一起的尺寸的形状系数。此外，块中的每个裸芯抵靠另一裸芯被支撑，从而使装置比PCB上的或封装体之内的单独的裸芯能够更好地承受机械冲击和热应力。
为了说明和描述的目的，已经呈现本发明的前面的详细描述。它不旨在穷尽或限制本发明为公开的精确形式。根据上述教导的许多修改和变化是可能的。选择所描述的实施例是为了最好地解释本发明的原理及其实际应用，从而使得本领域的技术人员能够最好地利用各种实施例中的发明且各种修改适合于设想的特定用途。本发明的范围由所附的权利要求限定。

Claims (20)

1.一种用于安装到介质的半导体装置，包括：
多个半导体裸芯，每个半导体裸芯包括：
主要表面，
有效边缘，与所述主要表面成非零度角，以及
电接触，形成在所述主要表面中，与所述半导体裸芯的有效边缘相邻，
所述多个半导体裸芯配置为表面安装到所述介质，每个半导体裸芯的有效边缘面对所述介质有效。
2.如权利要求1所述的半导体装置，其中所述多个半导体裸芯被堆叠在块中，每个裸芯由裸芯贴附膜彼此分隔开。
3.如权利要求2所述的半导体装置，其中所述块中的第一半导体裸芯的所述裸芯贴附膜抵靠所述块中的第二半导体裸芯的所述主要表面，所述第一半导体裸芯的裸芯贴附膜不接触所述第二半导体裸芯的电接触。
4.如权利要求2所述的半导体装置，其中所述块中第一半导体裸芯的所述裸芯贴附膜抵靠所述块中的第二半导体裸芯的所述主要表面，所述第一半导体裸芯的裸芯贴附膜形成为，所述第一半导体裸芯在所述第一半导体裸芯的所述有效边缘附近不含裸芯贴附膜，从而在所述电接触的区域中的所述第一半导体裸芯与所述第二半导体裸芯之间限定空间。
5.如权利要求1所述的半导体装置，其中所述电接触包括所述多个半导体裸芯的所述主要表面中的裸芯接合垫。
6.如权利要求1所述的半导体装置，其中所述电接触包括所述多个半导体裸芯的所述主要表面中的裸芯接合垫以及形成在所述裸芯接合垫上的电迹线。
7.一种半导体装置，包括：
多个半导体裸芯，每个半导体裸芯包括：
第一主要表面，具有长度和宽度，
第二主要表面，具有与所述第一主要表面的所述长度和所述宽度对应的长度和宽度，
有效边缘，在所述第一主要表面与所述第二主要表面之间延伸，
电接触，形成在所述第一主要表面中，与所述半导体裸芯的所述有效边缘相邻，并且在所述长度方向上延伸，以及
裸芯贴附膜，在所述第二主要表面上，用于将所述第二主要表面固定到另一表面，所述裸芯贴附膜延伸跨过所述第二主要表面的所述宽度，并且小于所述第二主要表面的整个长度；
堆叠为块的所述多个半导体裸芯由每个半导体裸芯上的所述裸芯贴附膜分隔开，并且所述裸芯贴附膜在所述块中彼此相邻的第一半导体裸芯与第二半导体裸芯之间的电接触之上留下空间。
8.如权利要求7所述的半导体装置，其中所述电接触从所述有效边缘延伸第一长度，所述第二主要表面从所述有效边缘的第二长度不含有有效裸芯贴附膜，所述第一长度等于所述第二长度。
9.如权利要求7所述的半导体装置，其中所述电接触从所述有效边缘延伸第一长度，所述第二主要表面有效从所述有效边缘的第二长度不含有裸芯贴附膜，所述第一长度小于所述第二长度。
10.如权利要求7所述的半导体装置，其中所述电接触从所述有效边缘延伸第一长度，所述第二主要表面从所述有效边缘的第二长度不含有裸芯贴附膜有效，所述第一长度大于所述第二长度。
11.如权利要求7所述的半导体装置，其中所述裸芯贴附膜以3μm与30μm之间的距离将两个相邻的半导体裸芯彼此间隔开。
12.如权利要求7所述的半导体装置，其中所述电接触包括所述多个半导体裸芯的所述主要表面中的裸芯接合垫。
13.如权利要求7所述的半导体装置，其中所述电接触包括所述多个半导体裸芯的所述主要表面中的裸芯接合垫以及形成在所述裸芯接合垫上的电迹线。
14.一种电子部件，包括：
多个半导体裸芯，每个半导体裸芯包括：
第一主要表面，
第二主要表面，
有效边缘，在所述第一主要表面与所述第二主要表面之间延伸，以及
形成在所述第一主要表面中的电接触，与所述半导体裸芯的所述有效边缘相邻；以及
介质，包括在所述介质的表面上方延伸的多个导电接触，所述多个半导体裸芯表面安装到所述介质。所述多个半导体裸芯的所述有效边缘面对所述介质有效，并且所述多个电接触电耦合到所述多个导电接触。
15.如权利要求14所述的电子部件，其中所述多个半导体裸芯被堆叠为块，每个裸芯由裸芯贴附膜彼此分隔开。
16.如权利要求15所述的电子部件，其中所述块中的第一半导体裸芯的所述第二主要表面上的所述裸芯贴附膜抵靠所述块中的第二半导体裸芯的所述第一主要表面，所述第一半导体裸芯的所述裸芯贴附膜形成为，所述第一半导体裸芯在所述第一半导体裸芯的所述有效边缘附近不含有裸芯贴附膜，从而在所述电接触的区域中的所述第一半导体裸芯与第二半导体裸芯之间限定空间。
17.如权利要求14所述的电子部件，其中所述电接触包括所述多个半导体裸芯的所述第一主要表面中的裸芯接合垫。
18.如权利要求14所述的电子部件，其中所述电接触包括所述多个半导体裸芯的所述第一主要表面中的裸芯接合垫，以及形成在所述裸芯接合垫上的电迹线。
19.如权利要求14所述的电子部件，其中所述导电接触包括焊料球。
20.一种电子部件，包括：
多个半导体裸芯，每个半导体裸芯包括：
第一主要表面，
第二主要表面，
有效边缘，在所述第一主要表面与第二主要表面之间延伸，以及
电接触装置，形成在所述第一主要表面中，与所述半导体裸芯的所述有效边缘相邻；以及
印刷电路板装置，包括在所述印刷电路板装置的表面上方延伸的多个导电接触装置，所述多个半导体裸芯表面安装到所述印刷电路板装置，所述多个半导体裸芯的所述有效边缘面对所述印刷电路板机构有效，并且所述多个电接触装置电耦合到所述多个导电接触装置。
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