JP5141084B2 - Electronic component mounting wiring board and method for preventing peeling of electronic component in electronic component mounting wiring board - Google Patents

Electronic component mounting wiring board and method for preventing peeling of electronic component in electronic component mounting wiring board Download PDF

Info

Publication number
JP5141084B2
JP5141084B2 JP2007110575A JP2007110575A JP5141084B2 JP 5141084 B2 JP5141084 B2 JP 5141084B2 JP 2007110575 A JP2007110575 A JP 2007110575A JP 2007110575 A JP2007110575 A JP 2007110575A JP 5141084 B2 JP5141084 B2 JP 5141084B2
Authority
JP
Japan
Prior art keywords
electronic component
wiring patterns
insulating member
wiring
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007110575A
Other languages
Japanese (ja)
Other versions
JP2008270479A (en
Inventor
賢司 笹岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP2007110575A priority Critical patent/JP5141084B2/en
Publication of JP2008270479A publication Critical patent/JP2008270479A/en
Application granted granted Critical
Publication of JP5141084B2 publication Critical patent/JP5141084B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Description

本発明は、配線パターンに対してアクティブ面が下向きとなるようにしてフェイスダウンの状態で電気的に接続されてなる電子部品を、前記配線パターン間に介在する絶縁部材中に埋設するとともに実装されてなる電子部品実装配線板、及びその電子部品実装配線板内に実装されてなる前記電子部品の剥離を防止する方法に関する。   The present invention embeds and mounts an electronic component electrically connected in a face-down state with an active surface facing downward with respect to a wiring pattern in an insulating member interposed between the wiring patterns. The present invention relates to an electronic component mounting wiring board and a method for preventing peeling of the electronic component mounted in the electronic component mounting wiring board.

近年の電子機器の高性能化・小型化の流れの中、回路部品の高密度、高機能化が一層求められている。かかる観点より、回路部品を搭載したモジュールにおいても、高密度、高機能化への対応が要求されている。このような要求に答えるべく、現在では配線板を多層化することが盛んに行われている。   In recent years, electronic devices are required to have higher density and higher functionality in the trend of higher performance and smaller size. From this point of view, even modules with circuit components are required to support high density and high functionality. In order to meet such demands, multilayering of wiring boards is currently being actively performed.

このような多層化配線板においては、複数の配線パターンを互いに略平行となるようにして配置し、前記配線パターン間に絶縁部材を配し、半導体部品などの電子部品は前記絶縁部材中に前記配線パターンの少なくとも１つに電気的に接続するようにして埋設するとともに、前記絶縁部材間を厚さ方向に貫通した層間接続体（ビア）を形成し、前記複数の配線パターンを互いに電気的に接続するようにしている（例えば、特許文献１参照）。
特開２００３−１９７８４９号 In such a multilayer wiring board, a plurality of wiring patterns are arranged so as to be substantially parallel to each other, an insulating member is disposed between the wiring patterns, and an electronic component such as a semiconductor component is placed in the insulating member. It is embedded so as to be electrically connected to at least one of the wiring patterns, and an interlayer connection body (via) that penetrates between the insulating members in the thickness direction is formed, and the plurality of wiring patterns are electrically connected to each other. The connection is made (see, for example, Patent Document 1).
JP 2003-197849 A

しかしながら、このような電子部品内蔵配線板においては、その製造工程におけるリフローなどの加熱処理中に発生する応力などによって、前記電子部品が破壊したり、前記絶縁部材が破壊したりするという問題が生じていた。この結果、前記電子部品内蔵配線板の歩留まりが低下してしまっていた。   However, in such a wiring board with a built-in electronic component, there arises a problem that the electronic component is broken or the insulating member is broken due to stress generated during heat treatment such as reflow in the manufacturing process. It was. As a result, the yield of the electronic component built-in wiring board has been reduced.

本発明は、配線パターンに対してアクティブ面が下向きとなるようにしてフェイスダウンの状態で電気的に接続されてなる電子部品を、前記配線パターン間に介在する絶縁部材中に埋設するとともに実装されてなる電子部品実装配線板において、加熱処理などに伴って発生する応力に起因して前記電子部品や前記絶縁部材が破壊してしまうのを防止し、前記電子部品内蔵配線板の歩留まりを向上させることを目的とする。   The present invention embeds and mounts an electronic component electrically connected in a face-down state with an active surface facing downward with respect to a wiring pattern in an insulating member interposed between the wiring patterns. In the electronic component mounting wiring board, the electronic component and the insulating member are prevented from being destroyed due to stress generated due to heat treatment or the like, and the yield of the electronic component built-in wiring board is improved. For the purpose.

上記目的を達成すべく、本発明は、
少なくとも一対の配線パターンと、
前記少なくとも一対の配線パターン間に介在する絶縁部材と、
前記少なくとも一対の配線パターン間において、前記絶縁部材中に埋設されるとともに、アクティブ面が下向きとなるようなフェイスダウンの状態で、前記少なくとも一対の配線パターンに対して電気的に接続されてなる電子部品と、
前記電子部品の、前記アクティブ面と相対向して位置する裏面の少なくとも一部に形成された、前記少なくとも一対の配線パターンを構成する材料と同じ材料からなる密着層と、
を具えることを特徴とする、電子部品実装配線板に関する。 In order to achieve the above object, the present invention provides:
At least a pair of wiring patterns;
An insulating member interposed between the at least one pair of wiring patterns;
Electrons that are embedded in the insulating member between the at least one pair of wiring patterns and are electrically connected to the at least one pair of wiring patterns in a face-down state with the active surface facing downward. Parts,
An adhesion layer made of the same material as that constituting the at least one pair of wiring patterns, formed on at least a part of the back surface of the electronic component facing the active surface;
It is related with the electronic component mounting wiring board characterized by comprising.

また、本発明は、
少なくとも一対の配線パターンと、この一対の配線パターン間に介在する絶縁部材中に埋設されるようにしてアクティブ面が下向きとなるようにしてフェイスダウンの状態で電気的に接続されてなる電子部品とを具える電子部品実装配線板において、
前記電子部品の、前記アクティブ面と相対向して位置する裏面の少なくとも一部に、前記少なくとも一対の配線パターンを構成する材料と同じ材料からなる密着層を形成し、前記電子部品及び前記絶縁部材間の密着性を向上させることを特徴とする、電子部品実装配線板における電子部品の剥離防止方法に関する。 The present invention also provides:
At least a pair of wiring patterns and an electronic component electrically connected in a face-down state with the active surface facing downward so as to be embedded in an insulating member interposed between the pair of wiring patterns In an electronic component mounting wiring board comprising:
An adhesion layer made of the same material as the material constituting the at least one pair of wiring patterns is formed on at least a part of the back surface of the electronic component located opposite to the active surface, and the electronic component and the insulating member It is related with the peeling prevention method of the electronic component in the electronic component mounting wiring board characterized by improving the adhesiveness between.

本発明者は、上記課題を解決すべく鋭意検討を実施した。その結果、配線パターンに対してアクティブ面が下向きとなるようにしてフェイスダウンの状態で電気的に接続されてなる電子部品を、前記配線パターン間に介在する絶縁部材中に埋設するとともに実装されてなる電子部品実装配線板において、加熱処理などに伴って発生する応力に起因して前記電子部品や前記絶縁部材が破壊してしまう原因が、前記電子部品と前記絶縁部材との密着力不足であることを見出した。   The present inventor has intensively studied to solve the above problems. As a result, an electronic component electrically connected in a face-down state with the active surface facing downward with respect to the wiring pattern is embedded and mounted in an insulating member interposed between the wiring patterns. In the electronic component mounting wiring board, the cause of the destruction of the electronic component and the insulating member due to the stress generated due to the heat treatment or the like is insufficient adhesion between the electronic component and the insulating member I found out.

すなわち、前記電子部品は例えば主としてシリコンからなる半導体部品であるような場合でも、この半導体部品を埋設して実装するために使用する前記絶縁部材は、シリコンなどとの密着性を全く考慮することなく、前記電子部品実装配線板全体の強度のみを考慮することによって、例えばエポキシ樹脂、ポリイミド樹脂、フェノール系樹脂などにガラス繊維やアラミド繊維などを含有させたものを用いていた。したがって、前記半導体部品などの電子部品と前記絶縁部材との密着性が十分でなく、上述した加熱処理などが施されると、それによって前記電子部品と前記絶縁部材との間に界面剥離が生じてしまい、この剥離部分に対して水分が吸着するとともに膨張し、完全なデラミ状態となってしまうことを見出した。   That is, even when the electronic component is a semiconductor component mainly made of silicon, for example, the insulating member used for embedding and mounting the semiconductor component is not considered at all with respect to adhesion with silicon or the like. Considering only the strength of the entire electronic component mounting wiring board, for example, epoxy resin, polyimide resin, phenol resin, or the like containing glass fiber or aramid fiber has been used. Therefore, the adhesion between the electronic component such as the semiconductor component and the insulating member is not sufficient, and when the above-described heat treatment or the like is performed, interface peeling occurs between the electronic component and the insulating member. As a result, it was found that moisture adsorbs to the peeled portion and expands, resulting in a complete delamination state.

この結果、上述したように電子部品の破壊や絶縁破壊を生ぜしめる結果となるとともに、その周辺に存在する層間接続部の破壊をも生ぜしめる結果となってしまい、目的とする電子部品実装配線板の製造歩留まりを低下させてしまう原因となっていた。   As a result, as described above, the electronic component is destroyed and the dielectric breakdown is caused, and the interlayer connection portion existing in the periphery thereof is also destroyed. This has been a cause of lowering the manufacturing yield.

そこで、本発明者は、上述したような原因を鑑みて、電子部品内蔵配線板における電子部品とそれを埋設している絶縁部材との密着力を向上させるべく鋭意検討した。その結果、前記電子部品内蔵配線板を構成する配線パターンは、同じく前記電子部品内蔵配線板を構成する絶縁部材に接触して保持されていることから、前記配線パターン及び前記絶縁部材間は本来的にある程度高い密着力を介して接触しているという事実を見出し、さらに着目するに至った。   In view of the above-described causes, the present inventor has intensively studied to improve the adhesion between the electronic component in the electronic component built-in wiring board and the insulating member in which the electronic component is embedded. As a result, the wiring pattern constituting the electronic component built-in wiring board is also held in contact with the insulating member constituting the electronic component built-in wiring board. The fact that they are in contact with each other through a relatively high adhesion force has led to further attention.

したがって、上述した事実に鑑み、本発明者は電子部品内蔵配線板を構成する電子部品において、同じく前記電子部品内蔵配線板を構成する絶縁部材と特に接触する面積が大きい、前記電子部品の、前記アクティブ面と相対向して位置する裏面の少なくとも一部に配線パターンを構成する材料と同じ材料からなる層を形成することによって、前記層が密着層として機能し、前記電子部品と前記絶縁部材との密着性が向上することを見出した。   Therefore, in view of the facts described above, the present inventor of the electronic component constituting the electronic component built-in wiring board has a large area especially in contact with the insulating member constituting the electronic component built-in wiring board. By forming a layer made of the same material as the material constituting the wiring pattern on at least a part of the back surface located opposite to the active surface, the layer functions as an adhesion layer, and the electronic component and the insulating member It has been found that the adhesion of is improved.

換言すれば、本発明では、前記電子部品の、前記アクティブ面と相対向して位置する裏面の少なくとも一部に、前記少なくとも一対の配線パターンを構成する材料と同じ材料からなる密着層を形成するようにしているので、前記電子部品及び前記絶縁部材間の密着性を向上させることができ、これによって、前記電子部品及び前記絶縁部材間の密着力不足によって生じていた電子部品の破壊や絶縁破壊、及び層間接続体の破壊などを防止することができる。したがって、前記電子部品内蔵配線板の製造歩留まりを向上させることができる。   In other words, in the present invention, an adhesion layer made of the same material as the material constituting the at least one pair of wiring patterns is formed on at least a part of the back surface of the electronic component located opposite to the active surface. As a result, the adhesion between the electronic component and the insulating member can be improved, whereby the destruction of the electronic component and the dielectric breakdown caused by insufficient adhesion between the electronic component and the insulating member. And destruction of the interlayer connection body can be prevented. Therefore, the manufacturing yield of the electronic component built-in wiring board can be improved.

なお、本発明の一態様においては、前記電子部品の前記裏面上において、前記電子部品と前記密着層との間に形成された接着層を具えるようにすることができる。これによって、前記電子部品と前記密着層との密着性を向上させることができる。   In one aspect of the present invention, an adhesive layer formed between the electronic component and the adhesion layer can be provided on the back surface of the electronic component. Thereby, the adhesion between the electronic component and the adhesion layer can be improved.

また、本発明の一態様においては、前記密着層の、前記電子部品側に向いた面と相対向する面を粗化する。この場合、前記密着層の前記絶縁部材との接触面積が実質的に増大するので、前記密着層を介した前記電子部品と前記絶縁部材との密着性をさらに向上させることができる。したがって、上述した破壊や絶縁破壊、及び層間接続体の破壊などを防止することができ、前記電子部品内蔵配線板の製造歩留まりを向上させることができる。   In one embodiment of the present invention, a surface of the adhesion layer that is opposite to the surface facing the electronic component is roughened. In this case, since the contact area of the adhesion layer with the insulating member is substantially increased, the adhesion between the electronic component and the insulating member via the adhesion layer can be further improved. Therefore, it is possible to prevent the above-described breakdown, dielectric breakdown, and breakdown of the interlayer connection body, and the manufacturing yield of the electronic component built-in wiring board can be improved.

さらに、本発明の一態様においては、上記電子部品内蔵配線板は、前記少なくとも一対の配線パターンは複数の配線パターンであり、前記複数の配線パターンの内、一対の配線パターンがそれぞれ前記絶縁部材の表面及び裏面上に設けられ、残りの配線パターンが前記絶縁部材中に埋設され、前記複数の配線パターンの少なくとも一部同士及び前記複数配線パターンの少なくとも一部と前記電子部品とが複数の層間接続体で電気的機械的に接続されてなるように構成することができる。この場合においては、多層構造の電子部品内蔵配線板を提供することができ、このような構造において、前記電子部品及び前記絶縁部材の密着性を向上させることができる。   Furthermore, in one aspect of the present invention, in the electronic component built-in wiring board, the at least one pair of wiring patterns is a plurality of wiring patterns, and each of the plurality of wiring patterns is a pair of wiring patterns. Provided on the front and back surfaces, the remaining wiring pattern is embedded in the insulating member, and at least a part of the plurality of wiring patterns and at least a part of the plurality of wiring patterns and the electronic component are connected to each other by a plurality of layers. It can be configured to be electrically and mechanically connected by the body. In this case, an electronic component built-in wiring board having a multilayer structure can be provided, and in such a structure, the adhesion between the electronic component and the insulating member can be improved.

さらに、本発明の一態様においては、前記密着層をグランド電位とし、前記密着層に対して電磁シールド機能を付与する。この場合、前記密着層は電磁シールド層として機能するようになるので、前記電子部品が発生する電磁ノイズ及び外部からの電磁ノイズの影響を除去することができるようになる。   Furthermore, in one embodiment of the present invention, the adhesion layer is set to a ground potential, and an electromagnetic shielding function is imparted to the adhesion layer. In this case, since the adhesion layer functions as an electromagnetic shield layer, the influence of electromagnetic noise generated by the electronic component and external electromagnetic noise can be removed.

以上、本発明によれば、配線パターンに対してアクティブ面が下向きとなるようにしてフェイスダウンの状態で電気的に接続されてなる電子部品を、前記配線パターン間に介在する絶縁部材中に埋設するとともに実装されてなる電子部品実装配線板において、加熱処理などに伴って発生する応力に起因して前記電子部品や前記絶縁部材が破壊してしまうのを防止し、前記電子部品内蔵配線板の歩留まりを向上させることができる。   As described above, according to the present invention, the electronic component electrically connected face-down with the active surface facing downward with respect to the wiring pattern is embedded in the insulating member interposed between the wiring patterns. In addition, in the electronic component mounting wiring board that is mounted, the electronic component and the insulating member are prevented from being destroyed due to stress generated due to heat treatment or the like. Yield can be improved.

以下、本発明のその他の特徴及び利点について、発明を実施するための最良の形態に基づいて説明する。   Hereinafter, other features and advantages of the present invention will be described based on the best mode for carrying out the invention.

図１は、本発明の電子部品内蔵配線板の一例を示す断面構成図である。図１に示す電子部品内蔵配線板１０は、その表面及び裏面に位置し、互いに略平行な第１の配線パターン１１及び第２の配線パターン１２を有するとともに、その内側において、互いに略平行であるとともに、第１の配線パターン１１及び第２の配線パターンとも略平行な関係を保持する第３の配線パターン１３及び第4の配線パターン１４を有している。   FIG. 1 is a cross-sectional configuration diagram showing an example of an electronic component built-in wiring board according to the present invention. An electronic component built-in wiring board 10 shown in FIG. 1 has first and second wiring patterns 11 and 12 which are located on the front and back surfaces thereof and are substantially parallel to each other, and are substantially parallel to each other on the inside thereof. In addition, a third wiring pattern 13 and a fourth wiring pattern 14 that maintain a substantially parallel relationship with the first wiring pattern 11 and the second wiring pattern are provided.

第１の配線パターン１１及び第３の配線パターン１３の間には、第１の絶縁部材２１が配置され、第２の配線パターン１２及び第４の配線パターン１４の間には、第２の絶縁部材２２が配置されている。また、第３の配線パターン１３及び第４の配線パターン１４の間には、第３の絶縁部材２３が配置されている。さらに、第３の絶縁部材２３中には、電子部品３１が埋設され、接続部材３１Ａを介して第４の配線パターン１４に電気的に接続されている。   A first insulating member 21 is disposed between the first wiring pattern 11 and the third wiring pattern 13, and a second insulating member is disposed between the second wiring pattern 12 and the fourth wiring pattern 14. A member 22 is arranged. Further, a third insulating member 23 is disposed between the third wiring pattern 13 and the fourth wiring pattern 14. Further, an electronic component 31 is embedded in the third insulating member 23 and is electrically connected to the fourth wiring pattern 14 via the connection member 31A.

また、電子部品３１はアクティブ面３１１が下側を向くようにしていわゆるフェイスダウン方式で接続されている。電子部品３１と第３の絶縁部材２２との間にはアンダーフィル３３が充填されている。   The electronic component 31 is connected by a so-called face-down method with the active surface 311 facing downward. An underfill 33 is filled between the electronic component 31 and the third insulating member 22.

また、図１に示す電子部品内蔵配線板１０においては、第３の絶縁部材２３中に第４の絶縁部材２４が介在している。そして、第４の絶縁部材２４の表面には第５の配線パターン１５が形成され、第４の絶縁部材２４の裏面には第６の配線パターン１６が形成されている。   In the electronic component built-in wiring board 10 shown in FIG. 1, a fourth insulating member 24 is interposed in the third insulating member 23. A fifth wiring pattern 15 is formed on the surface of the fourth insulating member 24, and a sixth wiring pattern 16 is formed on the back surface of the fourth insulating member 24.

第１の配線パターン１１と第３の配線パターン１３とは、第１の絶縁部材２１中を貫通するようにして形成されたバンプ４１によって電気的に接続され、第２の配線パターン１２と第４の配線パターン１４とは、第２の絶縁部材２２中を貫通するようにして形成されたバンプ４２によって電気的に接続されている。また、第３の配線パターン１３と第５の配線パターン１５とは、第３の絶縁部材２３の、前記パターン間に位置する部分を貫通するようにして形成されたバンプ４３によって電気的に接続され、第４の配線パターン１４と第６の配線パターン１６とは、第３の絶縁部材２３の、前記パターン間に位置する部分を貫通するようにして形成されたバンプ４４によって電気的に接続されている。   The first wiring pattern 11 and the third wiring pattern 13 are electrically connected by a bump 41 formed so as to penetrate through the first insulating member 21, and the second wiring pattern 12 and the fourth wiring pattern 12 are connected to each other. The wiring pattern 14 is electrically connected by a bump 42 formed so as to penetrate through the second insulating member 22. The third wiring pattern 13 and the fifth wiring pattern 15 are electrically connected by a bump 43 formed so as to penetrate a portion of the third insulating member 23 located between the patterns. The fourth wiring pattern 14 and the sixth wiring pattern 16 are electrically connected by a bump 44 formed so as to penetrate a portion of the third insulating member 23 located between the patterns. Yes.

また、第５の配線パターン１５と第６の配線パターン１６とは、第４の絶縁部材２４に形成されたスルーホールの内壁部分に形成された内部導電体４５によって電気的に接続されている。これによって、第１の配線パターン１１〜第６の配線パターン１６は、バンプ４１〜４４及び内部導電体４５によって互いに電気的に接続されることになる。さらに、第４の配線パターン１４を介して、電子部品３１も前述した配線パターンと電気的に接続されることになる。   The fifth wiring pattern 15 and the sixth wiring pattern 16 are electrically connected by an internal conductor 45 formed on the inner wall portion of the through hole formed in the fourth insulating member 24. Thus, the first wiring pattern 11 to the sixth wiring pattern 16 are electrically connected to each other by the bumps 41 to 44 and the internal conductor 45. Further, the electronic component 31 is also electrically connected to the above-described wiring pattern via the fourth wiring pattern 14.

なお、バンプ４１〜４４及び内部導電体４５は、それぞれ層間接続体を構成する。   The bumps 41 to 44 and the internal conductor 45 each constitute an interlayer connection body.

また、図１に示す電子部品内蔵配線板１０においては、電子部品３１のアクティブ面３１１と相対向する裏面３１２を覆うようにして密着層３２が形成されている。密着層３２は、上述した第１の配線パターン１１〜第６の配線パターン１６を構成する材料と同じ材料から構成する。特に、電子部品３１は、第３の絶縁部材２３中に埋設されているので、前述した配線パターンの内、特に第３の絶縁部材２３と接触した第３の配線パターン１３〜第６の配線パターン１６を構成する材料と同じ材料から構成する。   Further, in the electronic component built-in wiring board 10 shown in FIG. 1, the adhesion layer 32 is formed so as to cover the back surface 312 facing the active surface 311 of the electronic component 31. The adhesion layer 32 is made of the same material as that of the first wiring pattern 11 to the sixth wiring pattern 16 described above. In particular, since the electronic component 31 is embedded in the third insulating member 23, the third wiring pattern 13 to the sixth wiring pattern in contact with the third insulating member 23 among the above-described wiring patterns. 16 is made of the same material as that constituting the material 16.

第１の配線パターン１１〜第６の配線パターン１６は、電子部品内蔵配線板１０を構成する各絶縁部材に対して接触し密着保持されているので、前記配線パターンを構成する材料と前記各絶縁部材とは相互にある程度高い密着性を有する。特に、第３の配線パターン１３〜第６の配線パターン１６は、電子部品３１が埋設されている絶縁部材２３と接触しており、これら配線パターンを構成する材料と絶縁部材２３を構成する材料とは相互に高い密着性を有する。   Since the first wiring pattern 11 to the sixth wiring pattern 16 are in contact with and held in close contact with the respective insulating members constituting the electronic component built-in wiring board 10, the materials constituting the wiring pattern and the respective insulations The members have high adhesion to each other to some extent. In particular, the third wiring pattern 13 to the sixth wiring pattern 16 are in contact with the insulating member 23 in which the electronic component 31 is embedded, and the material constituting the wiring pattern and the material constituting the insulating member 23 are Have high adhesion to each other.

したがって、密着層３２の構成材料を第１の配線パターン１１〜第６の配線パターン１６、特に第３の配線パターン１３〜第６の配線パターン１６と同じ材料から構成することによって、密着層３２の、絶縁部材２１〜２４、特に第３の絶縁部材２３に対する密着力が向上する。結果として、電子部品３１は密着層３２を介して各絶縁部材、特に第３の絶縁部材２３との密着性が向上するようになる。このため、電子部品３１及び特に絶縁部材２３間の密着力不足によって生じていた電子部品３１の破壊や絶縁破壊、及び層間接続体４３の破壊などを防止することができ、電子部品内蔵配線板１０の製造歩留まりを向上させることができる。   Therefore, the constituent material of the adhesion layer 32 is made of the same material as that of the first wiring pattern 11 to the sixth wiring pattern 16, particularly the third wiring pattern 13 to the sixth wiring pattern 16. Further, the adhesion to the insulating members 21 to 24, particularly the third insulating member 23 is improved. As a result, the electronic component 31 is improved in adhesion to each insulating member, particularly the third insulating member 23 via the adhesion layer 32. For this reason, it is possible to prevent the electronic component 31 and especially the electronic component 31 from being broken due to insufficient adhesion between the insulating member 23, the dielectric breakdown, and the interlayer connector 43, and the electronic component built-in wiring board 10 can be prevented. The production yield can be improved.

一般に、第１の配線パターン１１〜第６の配線パターン１６を構成する材料は、銅、銀、金やアルミニウムなどの電気的良導体から構成される。また、第１の絶縁部材２１〜第４の絶縁部材２４を構成する材料は、エポキシ樹脂、ポリイミド樹脂、フェノール系樹脂などにガラス繊維やアラミド繊維などを含有させたものを用いることができる。上述のように、各配線パターンと各絶縁部材との密着保持の関係から、上述した材料同士は互いにある程度の密着性を有するようになるので、密着層３２を上述した配線パターンと同じ銅などから構成することによって、密着層３２と各絶縁部材、特に第３の絶縁部材２３との密着性が向上する。   In general, the material constituting the first wiring pattern 11 to the sixth wiring pattern 16 is composed of a good electrical conductor such as copper, silver, gold or aluminum. Moreover, the material which comprises the glass fiber, an aramid fiber, etc. to the epoxy resin, a polyimide resin, a phenol resin etc. can be used for the material which comprises the 1st insulating member 21-the 4th insulating member 24. FIG. As described above, since the materials described above have a certain degree of adhesion to each other due to the close contact relationship between each wiring pattern and each insulating member, the contact layer 32 is made of the same copper as the wiring pattern described above. By comprising, the adhesiveness of the contact | adherence layer 32 and each insulating member, especially the 3rd insulating member 23 improves.

なお、密着層３２は上述したような作用効果を奏すればその厚さなどについては特に限定されるものではないが、例えば０．１μｍ〜３５μｍとすることができる。さらに、密着層３２は、スパッタリング法や蒸着法、メッキ法などの汎用の膜形成手段を用いて形成することができる。   The thickness of the adhesion layer 32 is not particularly limited as long as it exhibits the above-described effects, but may be, for example, 0.1 μm to 35 μm. Furthermore, the adhesion layer 32 can be formed using a general-purpose film forming means such as a sputtering method, a vapor deposition method, or a plating method.

また、本例では、密着層３２を電子部品３１の裏面３１２の全体を覆うようにして形成しているが、上述した作用効果を奏する限り、必ずしも裏面３１２の全体を覆う必要はなく、その一部を覆うようにして形成することができる。なお、密着層３２を電子部品３１の裏面３１２上において形成するのは、（第３の）絶縁部材（２３）に対する電子部品３１２の接触が裏面３１２において大きくなり、かかる部分での剥離が顕著となるために、その分、密着力の向上が要求されるためである。   In this example, the adhesion layer 32 is formed so as to cover the entire back surface 312 of the electronic component 31. However, as long as the above-described effects are exhibited, it is not always necessary to cover the entire back surface 312. It can be formed so as to cover the part. The reason why the adhesion layer 32 is formed on the back surface 312 of the electronic component 31 is that the contact of the electronic component 312 with the (third) insulating member (23) becomes large on the back surface 312 and the peeling at this portion is remarkable. This is because an improvement in adhesion is required accordingly.

なお、特に電子部品３１を、シリコンを主原料とする半導体部品とする場合においては、上述した配線材料の内、特に銅などを好ましく用いることができる。   In particular, in the case where the electronic component 31 is a semiconductor component mainly made of silicon, among the above-described wiring materials, copper or the like can be preferably used.

また、特に図中には示していないが、電子部品３１と密着層３２との間には、接着層を設けることもできる。密着層３２の特に第３の絶縁部材２３との密着力が向上しても、電子部品３１の構成材料と密着層３２の構成材料との相違によって、密着層２３と電子部品３１との密着力が低い場合は、密着層３２を設けたことによる上述した作用効果を十分に奏しない場合がある。しかしながら、上記接着層を設けることによって、電子部品３１と密着層３２との密着力を確保することができるので、上述したような不利益を被ることはない。   Although not particularly shown in the drawing, an adhesive layer may be provided between the electronic component 31 and the adhesion layer 32. Even if the adhesion of the adhesion layer 32 to the third insulating member 23 is improved, the adhesion force between the adhesion layer 23 and the electronic component 31 depends on the difference between the constituent material of the electronic component 31 and the constituent material of the adhesion layer 32. Is low, the above-described operational effects due to the provision of the adhesion layer 32 may not be sufficiently exhibited. However, since the adhesive force between the electronic component 31 and the adhesive layer 32 can be ensured by providing the adhesive layer, there is no disadvantage as described above.

なお、前記接着層の厚さは、０．０１μｍ〜１５μｍとすることができる。また、前記接着層を構成する材料としては、Ｔｉ、Ｎｉ及びＣｒの少なくとも一種を用いることができる。   In addition, the thickness of the said adhesive layer can be 0.01 micrometer-15 micrometers. Moreover, as a material which comprises the said contact bonding layer, at least 1 type of Ti, Ni, and Cr can be used.

また、密着層３２の、電子部品３１側に向いた面と相対向する面３２Ａに対して粗化処理を行い、面３２Ａを粗化するようにすることができる。この場合、密着層３２の第３の絶縁部材２３との接触面積が実質的に増大するので、密着層３２を介した電子部品３１と第３の絶縁部材２３との密着性をさらに向上させることができる。したがって、上述した破壊や絶縁破壊、及び層間接続体の破壊などをさらに効果的に防止することができ、前記電子部品内蔵配線板の製造歩留まりをさらに向上させることができる。   Further, it is possible to roughen the surface 32 </ b> A by performing a roughening process on the surface 32 </ b> A facing the surface facing the electronic component 31 of the adhesion layer 32. In this case, since the contact area of the adhesion layer 32 with the third insulating member 23 is substantially increased, the adhesion between the electronic component 31 and the third insulation member 23 via the adhesion layer 32 is further improved. Can do. Therefore, it is possible to more effectively prevent the above-mentioned breakdown, dielectric breakdown, and breakdown of the interlayer connection, and the manufacturing yield of the electronic component built-in wiring board can be further improved.

なお、上記粗化処理は、例えばエッチング処理や黒化還元処理などを用いて実施することができる。エッチング処理を用いた粗化処理の場合は、たとえばメック（株）のＣＺ処理やアトテック社のマルチボンド処理などにより実施することが出来る。また、黒化還元処理は、所定の黒化還元処理剤を用いて行う。この場合、密着層３２の表面は酸化されて所定の酸化物からなる凹凸部が形成されるとともに、後の還元処理によって前記酸化物が還元され、前記凹凸部は元の密着層３２の構成材料から構成されることになる。結果として、密着層３２の表面が粗化されることになる。   The roughening treatment can be performed using, for example, an etching treatment or a blackening reduction treatment. In the case of the roughening process using the etching process, for example, the CZ process of MEC Co., Ltd. or the multi-bond process of Atotech can be used. Further, the blackening reduction treatment is performed using a predetermined blackening reduction treatment agent. In this case, the surface of the adhesion layer 32 is oxidized to form an uneven portion made of a predetermined oxide, and the oxide is reduced by a subsequent reduction treatment. The uneven portion is a constituent material of the original adhesion layer 32. It will consist of As a result, the surface of the adhesion layer 32 is roughened.

上記のような操作を経ることにより、密着層３２の表面にはサブミクロンオーダの凹凸部が形成されることになり、粗化されることになる。   As a result of the operation as described above, an uneven portion of the order of submicron is formed on the surface of the adhesion layer 32 and roughened.

図２は、図１に示す電子部品内蔵配線板１０の変形例を示す断面構成図である。本例においては、図１に示す電子部品内蔵配線板１０の、密着層３２の面３２Ａが層間接続体４３を介して第３の配線パターン１３のグランドパターンに電気的に接続され、密着層３２の電位がグランド電位に保持されている。したがって、密着層３２に対して電磁シールド機能を付与することができ、密着層３２は電磁シールド層として機能するようになるので、電子部品３１が発生する電磁ノイズ及び外部からの電磁ノイズの影響を除去することができるようになる。   FIG. 2 is a cross-sectional configuration diagram showing a modification of the electronic component built-in wiring board 10 shown in FIG. In this example, the surface 32A of the adhesion layer 32 of the electronic component built-in wiring board 10 shown in FIG. 1 is electrically connected to the ground pattern of the third wiring pattern 13 via the interlayer connector 43, and the adhesion layer 32 is obtained. Is held at the ground potential. Therefore, an electromagnetic shielding function can be imparted to the adhesion layer 32, and the adhesion layer 32 functions as an electromagnetic shielding layer. Therefore, the influence of electromagnetic noise generated by the electronic component 31 and electromagnetic noise from the outside is affected. Can be removed.

したがって、図２に示す電子部品内蔵配線板１０において、電子部品３１は、半導体部品、特にはＧＨｚ以上の周波数で駆動させる高周波ＩＣ部品などの、内外の電磁ノイズの影響を比較的顕著に受けやすい半導体部品において好適に用いることができる。   Therefore, in the electronic component built-in wiring board 10 shown in FIG. 2, the electronic component 31 is relatively easily affected by internal and external electromagnetic noise such as a semiconductor component, particularly a high frequency IC component driven at a frequency of GHz or higher. It can be suitably used in semiconductor components.

なお、本例では、密着層３２を第３の配線パターン１３のグランドパターンに接続することによってグランド電位に保持しているが、グランド電位に保持するに際してはその他の任意の方法を用いることができる。   In this example, the adhesion layer 32 is held at the ground potential by connecting to the ground pattern of the third wiring pattern 13. However, any other method can be used for holding the adhesion layer 32 at the ground potential. .

また、本例においても電子部品３２の裏面３１２に密着層３２を設けているので、図１に関する例と同様に、密着層３２を設けたことによる作用効果を享受することができる。   Also, in this example, since the adhesion layer 32 is provided on the back surface 312 of the electronic component 32, the effect of providing the adhesion layer 32 can be enjoyed as in the example relating to FIG.

次に、図１に示す電子部品内蔵配線板の製造方法について説明する。図３〜図１１は、図１に示す電子部品内蔵配線板の製造方法を示す工程図である。   Next, the manufacturing method of the electronic component built-in wiring board shown in FIG. 1 will be described. 3 to 11 are process diagrams showing a method of manufacturing the electronic component built-in wiring board shown in FIG.

最初に、図３に示すように、金属（例えば銅）箔５３上に例えばスクリーン印刷により、導電性材料からなる円錐状のバンプ６１を形成する。次いで、図４に示すように、バンプ６１が貫通するようにして絶縁層７１を形成する。次いで、図５に示すように、プリプレグ７１上に金属（例えば銅）箔５１を配置し、その後、加熱加圧プレスを実施してプリプレグ７１を硬化し、両面金属（銅）箔張り板を形成する。なお硬化したプリプレグ７１は、後の工程により図１に示す部品を内蔵した多層配線板の絶縁部材２１を構成する材料となる。   First, as shown in FIG. 3, conical bumps 61 made of a conductive material are formed on a metal (for example, copper) foil 53 by, for example, screen printing. Next, as shown in FIG. 4, an insulating layer 71 is formed so that the bumps 61 penetrate therethrough. Next, as shown in FIG. 5, a metal (for example, copper) foil 51 is placed on the prepreg 71, and then the prepreg 71 is cured by performing a heating and pressing press to form a double-sided metal (copper) foil-clad plate. To do. The cured prepreg 71 becomes a material constituting the insulating member 21 of the multilayer wiring board incorporating the components shown in FIG.

次いで、金属箔５３に対してフォトリソグラフィによるパターニングを施し、図６に示すように第３の配線パターン１３を形成する。次いで、図７に示すように、第３の配線パターン１３上に円錐状のバンプ６３を形成するとともに、バンプ６３が貫通するとともにそれを埋設するようにしてプリプレグ７３を形成する。   Next, the metal foil 53 is patterned by photolithography to form a third wiring pattern 13 as shown in FIG. Next, as shown in FIG. 7, a conical bump 63 is formed on the third wiring pattern 13, and a prepreg 73 is formed so that the bump 63 penetrates and is embedded.

なお、上記工程におけるプリプレグ７３は後の加圧下による加熱操作において硬化して絶縁部材２３となり、バンプ６１及び６３は層間接続体４１及び４３となる。   In addition, the prepreg 73 in the above process is cured by a heating operation under pressure later to become the insulating member 23, and the bumps 61 and 63 become the interlayer connectors 41 and 43.

さらに、図３〜図７と同様な工程を経ることにより、図８に示すような、硬化したプリプレグ７２の主面上に金属箔５２及び第４の配線パターン１４が形成されるとともに、プリプレグ７２を貫通するように設けられたバンプ６２が形成された積層体を作製する。なお硬化したプリプレグ７２は、後の工程により図１に示す部品を内蔵した多層配線板の絶縁部材２２を構成する材料となる。   Further, the metal foil 52 and the fourth wiring pattern 14 are formed on the main surface of the cured prepreg 72 as shown in FIG. A laminated body in which the bumps 62 provided so as to penetrate through are formed. The cured prepreg 72 becomes a material constituting the insulating member 22 of the multilayer wiring board incorporating the components shown in FIG.

次いで、図８で得た積層体に対して、図９に示すように、第４の配線パターン１４上にアンダーフィル樹脂３３をディスペンサーなどにより塗布し、図１０に示すように、例えばフリップチップボンダーにより、予め接続用のバンプの形成された電子部品３２を搭載し、アンダーフィル樹脂３３を硬化させて、電子部品３２を第４の配線パターン１４上に電気的機械的に接続する。なお、電子部品３２の裏面３１２には予め上述したような汎用の膜形成手段によって、密着層３２を形成しておく。また、接着層を形成する場合においても、電子部品３２の裏面３１２と密着層３２との間に前記接着層を予め形成しておく。   Next, as shown in FIG. 9, an underfill resin 33 is applied on the fourth wiring pattern 14 by a dispenser or the like to the laminate obtained in FIG. 8, and as shown in FIG. 10, for example, a flip chip bonder Thus, the electronic component 32 on which the bumps for connection are formed in advance is mounted, the underfill resin 33 is cured, and the electronic component 32 is electrically and mechanically connected to the fourth wiring pattern 14. Note that the adhesion layer 32 is formed in advance on the back surface 312 of the electronic component 32 by a general-purpose film forming means as described above. Further, when forming the adhesive layer, the adhesive layer is formed in advance between the back surface 312 of the electronic component 32 and the adhesion layer 32.

また、密着層３２の面３２Ａに対して粗化処理を施す場合は、図１０に示すような状態で粗化処理を実施する。したがって、この場合においては、密着層３２の面３２Ａと同時に第４の配線パターン１４も粗化処理がなされることになる。   Further, when the roughening process is performed on the surface 32A of the adhesion layer 32, the roughening process is performed in a state as shown in FIG. Therefore, in this case, the fourth wiring pattern 14 is also roughened simultaneously with the surface 32A of the adhesion layer 32.

次いで、図１１に示すように、図７の工程で得た積層体および図１０の工程で得た積層体を、第５の配線パターン１５及び第６の配線パターン１６が形成されるとともに、スルーホール４５が形成された絶縁層７４及びこれと密着するようにして設けられるとともに、バンプ６４が貫通するようにして設けられたプリプレグ７３を介して、上下方向に加圧下加熱する。   Next, as shown in FIG. 11, the fifth wiring pattern 15 and the sixth wiring pattern 16 are formed on the laminate obtained in the process of FIG. 7 and the laminate obtained in the process of FIG. The insulating layer 74 in which the holes 45 are formed and the prepreg 73 provided so as to be in close contact with the insulating layer 74 and through which the bump 64 penetrates are heated under pressure in the vertical direction.

この際、上述したプリプレグ７３は硬化して絶縁部材２３となるとともに、バンプ６１、６２、６３及び６４は層間接続体４１、４２、４３及び４４として形成される。また、絶縁層７４は絶縁部材２４となる。なお、プリプレグ７３の一部は流動化し、電子部品３２の周囲の空間を埋設して密着する状態で硬化することになる。   At this time, the above-described prepreg 73 is cured to become the insulating member 23, and the bumps 61, 62, 63 and 64 are formed as the interlayer connectors 41, 42, 43 and 44. The insulating layer 74 becomes the insulating member 24. A part of the prepreg 73 is fluidized and cured in a state in which the space around the electronic component 32 is buried and closely adhered.

次いで、金属箔５１及び５２をフォトリソグラフィでパターニングし、第１の配線パターン１１及び第２の配線パターン１２を形成する。結果として、上述した工程を経ることにより、図１に電子部品内蔵配線板１０が形成されることになる。   Next, the metal foils 51 and 52 are patterned by photolithography to form the first wiring pattern 11 and the second wiring pattern 12. As a result, the electronic component built-in wiring board 10 is formed in FIG. 1 through the above-described steps.

なお、上述した製造方法はあくまで図１に示す電子部品内蔵配線板の一例を示したものであり、その他の方法を用いても同様に製造することができる。例えばＡＬＩＶＨなどの方法を当然に用いることもできる。ＡＬＩＶＨは、例えば「ビルドアップ多層プリント配線板技術（２０００年６月２０日、日刊工業新聞社発行）」などに記載されている公知の技術である。   Note that the manufacturing method described above is merely an example of the electronic component built-in wiring board shown in FIG. 1 and can be manufactured in the same manner by using other methods. For example, a method such as ALIVH can be naturally used. ALIVH is a well-known technique described in, for example, “Build-up multilayer printed wiring board technology (issued by Nikkan Kogyo Shimbun, June 20, 2000)”.

以上、本発明を上記具体例に基づいて詳細に説明したが、本発明は上記具体例に限定されるものではなく、本発明の範疇を逸脱しない限りにおいて、あらゆる変形や変更が可能である。   The present invention has been described in detail based on the above specific examples. However, the present invention is not limited to the above specific examples, and various modifications and changes can be made without departing from the scope of the present invention.

例えば、上記具体例においては、絶縁部材を合計４層としているが、埋設すべき電子部品の数などに応じて適宜変化させることができる。例えば、２層とすることもできるし、５層以上とすることもできる。この場合、配線パターンの数は前記絶縁部材の数に応じて適宜に設定する。また、層間接続体に関しても上述したバンプや内部導電体などを適宜組み合わせて使用することができる。   For example, in the above specific example, the insulating member has a total of four layers, but can be appropriately changed according to the number of electronic components to be embedded. For example, the number of layers can be two, or five or more. In this case, the number of wiring patterns is appropriately set according to the number of the insulating members. In addition, the above-described bumps and internal conductors can be used in appropriate combinations for the interlayer connection.

本発明の電子部品内蔵配線板の一例を示す断面構成図である。It is a section lineblock diagram showing an example of a wiring board with a built-in electronic component of the present invention. 図１に示す電子部品内蔵配線板１０の変形例を示す断面構成図である。It is a cross-sectional block diagram which shows the modification of the electronic component built-in wiring board 10 shown in FIG. 図１に示す電子部品内蔵配線板の製造方法における一工程を示す図である。It is a figure which shows one process in the manufacturing method of the electronic component built-in wiring board shown in FIG. 同じく、図１に示す電子部品内蔵配線板の製造方法における一工程を示す図である。Similarly, it is a figure which shows one process in the manufacturing method of the electronic component built-in wiring board shown in FIG. 同じく、図１に示す電子部品内蔵配線板の製造方法における一工程を示す図である。Similarly, it is a figure which shows one process in the manufacturing method of the electronic component built-in wiring board shown in FIG. 同じく、図１に示す電子部品内蔵配線板の製造方法における一工程を示す図である。Similarly, it is a figure which shows one process in the manufacturing method of the electronic component built-in wiring board shown in FIG. 同じく、図１に示す電子部品内蔵配線板の製造方法における一工程を示す図である。Similarly, it is a figure which shows one process in the manufacturing method of the electronic component built-in wiring board shown in FIG. 同じく、図１に示す電子部品内蔵配線板の製造方法における一工程を示す図である。Similarly, it is a figure which shows one process in the manufacturing method of the electronic component built-in wiring board shown in FIG. 同じく、図１に示す電子部品内蔵配線板の製造方法における一工程を示す図である。Similarly, it is a figure which shows one process in the manufacturing method of the electronic component built-in wiring board shown in FIG. 同じく、図１に示す電子部品内蔵配線板の製造方法における一工程を示す図である。Similarly, it is a figure which shows one process in the manufacturing method of the electronic component built-in wiring board shown in FIG. 同じく、図１に示す電子部品内蔵配線板の製造方法における一工程を示す図である。Similarly, it is a figure which shows one process in the manufacturing method of the electronic component built-in wiring board shown in FIG.

符号の説明Explanation of symbols

１０ 電子部品内蔵配線板
１１ 第１の配線パターン
１２ 第２の配線パターン
１３ 第３の配線パターン
１４ 第４の配線パターン
１５ 第５の配線パターン
１６ 第６の配線パターン
２１ 第１の絶縁部材
２２ 第２の絶縁部材
２３ 第３の絶縁部材
２４ 第４の絶縁部材
３１ 電子部品
３２ 密着層
３３ アンダーフィル樹脂 DESCRIPTION OF SYMBOLS 10 Electronic component built-in wiring board 11 1st wiring pattern 12 2nd wiring pattern 13 3rd wiring pattern 14 4th wiring pattern 15 5th wiring pattern 16 6th wiring pattern 21 1st insulating member 22 1st 2 Insulating Member 23 Third Insulating Member 24 Fourth Insulating Member 31 Electronic Component 32 Adhesive Layer 33 Underfill Resin

Claims (8)

少なくとも一対の配線パターンと、
前記少なくとも一対の配線パターン間に介在する絶縁部材と、
前記少なくとも一対の配線パターン間において、前記絶縁部材中に埋設されるとともに、アクティブ面が下向きとなるようなフェイスダウンの状態で、前記少なくとも一対の配線パターンに対して電気的に接続されてなる電子部品と、
前記電子部品の、前記アクティブ面と相対向して位置する裏面の少なくとも一部に形成された、前記少なくとも一対の配線パターンを構成する材料と同じ材料からなる密着層と、
前記電子部品の前記裏面上において、前記電子部品と前記密着層との間に形成された、Ｔｉ、Ｎｉ、及びＣｒからなる群より選ばれる少なくとも一種を含む接着層とを具え、
前記電子部品はシリコンを主原料とする半導体部品であり、
前記密着層の、前記電子部品側に向いた面と相対向する面が粗化されていることを特徴とする、電子部品実装配線板。 At least a pair of wiring patterns;
An insulating member interposed between the at least one pair of wiring patterns;
Electrons that are embedded in the insulating member between the at least one pair of wiring patterns and are electrically connected to the at least one pair of wiring patterns in a face-down state with the active surface facing downward. Parts,
An adhesion layer made of the same material as that constituting the at least one pair of wiring patterns, formed on at least a part of the back surface of the electronic component facing the active surface;
On the back surface of the electronic component, comprising an adhesive layer that is formed between the electronic component and the adhesion layer and includes at least one selected from the group consisting of Ti, Ni, and Cr ,
The electronic component is a semiconductor component mainly made of silicon,
An electronic component mounting wiring board, wherein a surface of the adhesion layer facing the surface facing the electronic component is roughened. 前記少なくとも一対の配線パターンは複数の配線パターンであり、前記複数の配線パターンの内、一対の配線パターンがそれぞれ前記絶縁部材の表面及び裏面上に設けられ、残りの配線パターンが前記絶縁部材中に埋設され、前記複数の配線パターンの少なくとも一部同士及び前記複数配線パターンの少なくとも一部と前記電子部品とが複数の層間接続体で電気的機械的に接続されてなることを特徴とする、請求項１に記載の電子部品実装配線板。 The at least one pair of wiring patterns is a plurality of wiring patterns, and among the plurality of wiring patterns, a pair of wiring patterns are respectively provided on the front surface and the back surface of the insulating member, and the remaining wiring patterns are in the insulating member. It is embedded, and at least a part of the plurality of wiring patterns and at least a part of the plurality of wiring patterns and the electronic component are electrically and mechanically connected by a plurality of interlayer connectors. Item 2. The electronic component mounting wiring board according to Item 1 . 前記複数の層間接続体の少なくとも１つは、前記絶縁部材の厚さ方向に一致する軸を有し、前記軸方向の径が前記絶縁部材の厚さ方向で変化することを特徴とする、請求項２に記載の電子部品実装配線板。   At least one of the plurality of interlayer connectors has an axis that coincides with the thickness direction of the insulating member, and the diameter in the axial direction varies in the thickness direction of the insulating member. Item 3. The electronic component mounting wiring board according to Item 2. 前記密着層をグランド電位とし、前記密着層に対して電磁シールド機能を付与したことを特徴とする、請求項１〜３のいずれか一に記載の電子部品実装配線板。   The electronic component mounting wiring board according to any one of claims 1 to 3, wherein the adhesion layer is set to a ground potential and an electromagnetic shielding function is imparted to the adhesion layer. 前記配線パターン及び前記密着層を構成する前記材料は銅であることを特徴とする、請求項１〜４のいずれか一に記載の電子部品実装配線板。 The material is characterized in that a copper, an electronic component mounting circuit board according to any one of claims 1 to 4 constituting the wiring pattern and the adhesive layer. 少なくとも一対の配線パターンと、この一対の配線パターン間に介在する絶縁部材中に埋設されるようにしてアクティブ面が下向きとなるようにしてフェイスダウンの状態で電気的に接続されてなる電子部品とを具える電子部品実装配線板において、
前記電子部品はシリコンを主原料とする半導体部品とし、
前記電子部品の、前記アクティブ面と相対向して位置する裏面の少なくとも一部に、前記少なくとも一対の配線パターンを構成する材料と同じ材料からなる密着層を形成するとともに、前記密着層の、前記電子部品側に向いた面と相対向する面を粗化し、前記電子部品の前記裏面上において、前記電子部品と前記密着層との間にＴｉ、Ｎｉ、及びＣｒからなる群より選ばれる少なくとも一種を含む接着層を形成して、前記電子部品及び前記絶縁部材間の密着性を向上させることを特徴とする、電子部品実装配線板における電子部品の剥離防止方法。 At least a pair of wiring patterns and an electronic component electrically connected in a face-down state with the active surface facing downward so as to be embedded in an insulating member interposed between the pair of wiring patterns In an electronic component mounting wiring board comprising:
The electronic component is a semiconductor component mainly made of silicon,
Forming an adhesion layer made of the same material as the material constituting the at least one pair of wiring patterns on at least a part of the back surface of the electronic component located opposite to the active surface; At least one selected from the group consisting of Ti, Ni, and Cr between the electronic component and the adhesion layer on the back surface of the electronic component is roughened on the surface facing the electronic component side. A method for preventing peeling of an electronic component on an electronic component-mounted wiring board, comprising: forming an adhesive layer containing the material to improve adhesion between the electronic component and the insulating member. 前記少なくとも一対の配線パターンは複数の配線パターンであり、前記複数の配線パターンの内、一対の配線パターンがそれぞれ前記絶縁部材の表面及び裏面上に設けられ、残りの配線パターンが前記絶縁部材中に埋設され、前記複数の配線パターンの少なくとも一部同士及び前記複数配線パターンの少なくとも一部と前記電子部品とが複数の層間接続体で電気的機械的に接続されてなることを特徴とする、請求項６に記載の電子部品実装配線板における電子部品の剥離防止方法。 The at least one pair of wiring patterns is a plurality of wiring patterns, and among the plurality of wiring patterns, a pair of wiring patterns are respectively provided on the front surface and the back surface of the insulating member, and the remaining wiring patterns are in the insulating member. It is embedded, and at least a part of the plurality of wiring patterns and at least a part of the plurality of wiring patterns and the electronic component are electrically and mechanically connected by a plurality of interlayer connectors. Item 7. A method for preventing peeling of electronic components in an electronic component-mounted wiring board according to Item 6 . 前記配線パターン及び前記密着層を構成する前記材料は銅であることを特徴とする、請求項６又は７に記載の電子部品実装配線板における電子部品の剥離防止方法。 The method of preventing peeling of an electronic component in an electronic component mounting wiring board according to claim 6 or 7 , wherein the material constituting the wiring pattern and the adhesion layer is copper.
JP2007110575A 2007-04-19 2007-04-19 Electronic component mounting wiring board and method for preventing peeling of electronic component in electronic component mounting wiring board Expired - Fee Related JP5141084B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007110575A JP5141084B2 (en) 2007-04-19 2007-04-19 Electronic component mounting wiring board and method for preventing peeling of electronic component in electronic component mounting wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007110575A JP5141084B2 (en) 2007-04-19 2007-04-19 Electronic component mounting wiring board and method for preventing peeling of electronic component in electronic component mounting wiring board

Publications (2)

Publication Number Publication Date
JP2008270479A JP2008270479A (en) 2008-11-06
JP5141084B2 true JP5141084B2 (en) 2013-02-13

Family

ID=40049602

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007110575A Expired - Fee Related JP5141084B2 (en) 2007-04-19 2007-04-19 Electronic component mounting wiring board and method for preventing peeling of electronic component in electronic component mounting wiring board

Country Status (1)

Country Link
JP (1) JP5141084B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104813753A (en) * 2012-11-29 2015-07-29 株式会社村田制作所 High frequency module

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010267845A (en) * 2009-05-15 2010-11-25 Dainippon Printing Co Ltd Component built-in wiring board and method of manufacturing the component built-in wiring board
JP5609037B2 (en) * 2009-07-31 2014-10-22 大日本印刷株式会社 Semiconductor package built-in wiring board and manufacturing method of semiconductor package built-in wiring board
JP5459134B2 (en) * 2009-07-31 2014-04-02 大日本印刷株式会社 Semiconductor package built-in wiring board and manufacturing method of semiconductor package built-in wiring board
JP5590097B2 (en) * 2012-10-29 2014-09-17 大日本印刷株式会社 Component built-in wiring board

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001332866A (en) * 2000-05-24 2001-11-30 Matsushita Electric Ind Co Ltd Circuit board and method of production
JP4089273B2 (en) * 2002-04-18 2008-05-28 ソニー株式会社 Manufacturing method of component-embedded substrate
JP2005223223A (en) * 2004-02-06 2005-08-18 Tdk Corp Semiconductor ic built-in substrate, its manufacturing method, and semiconductor ic built-in module
JP4457779B2 (en) * 2004-06-30 2010-04-28 Ｔｄｋ株式会社 Semiconductor IC built-in substrate
JP5100989B2 (en) * 2005-08-01 2012-12-19 大日本印刷株式会社 Component built-in wiring board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104813753A (en) * 2012-11-29 2015-07-29 株式会社村田制作所 High frequency module
CN104813753B (en) * 2012-11-29 2016-08-24 株式会社村田制作所 High-frequency model

Also Published As

Publication number Publication date
JP2008270479A (en) 2008-11-06

Similar Documents

Publication Publication Date Title
KR101475109B1 (en) Multilayer Wiring Substrate and Method of Manufacturing the Same
US9793219B2 (en) Semiconductor element built-in wiring board and method for manufacturing the same
US8737085B2 (en) Wiring board with a built-in component and method for manufacturing the same
US9554462B2 (en) Printed wiring board
KR20120022593A (en) Multilayer wiring substrate
JP2008198999A (en) Printed circuit board with built-in electronic device and method of manufacturing the same
US20140116759A1 (en) Printed wiring board and method for manufacturing printed wiring board
JP2016063130A (en) Printed wiring board and semiconductor package
JP2011138868A (en) Multilayer wiring substrate
JP2005142178A (en) Multilayer printed wiring board with built-in electronic component
JP5141084B2 (en) Electronic component mounting wiring board and method for preventing peeling of electronic component in electronic component mounting wiring board
JP2008124247A (en) Substrate with built-in component and its manufacturing method
JP6669330B2 (en) Printed circuit board with built-in electronic components and method of manufacturing the same
KR101905879B1 (en) The printed circuit board and the method for manufacturing the same
WO2014125567A1 (en) Substrate with built-in component, and manufacturing method for same
JP2010123829A (en) Printed wiring board and manufacturing method thereof
JP5886335B2 (en) Manufacturing method of electronic component built-in substrate and electronic component built-in substrate
JP2009054930A (en) Multi-layer printed wiring board having built-in parts and method of manufacturing the same
JP5367306B2 (en) Manufacturing method of ceramic parts
KR101204083B1 (en) Active IC chip embedded multilayer flexible printed circuit board and Method of making the same
JP2013219204A (en) Core board for wiring board manufacturing and wiring board
JP2010123830A (en) Printed wiring board and manufacturing method thereof
JP2008283114A (en) Electronic component mounting wiring board, and electromagnetic noise removal method of electronic component mounting wiring board
JP2009130095A (en) Part built-in wiring board, and manufacturing method for part built-in wiring board
JP2008078573A (en) Multi-layer printed wiring board having built-in parts

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100205

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110908

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110920

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111121

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20120529

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120824

A911 Transfer of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20120831

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20121023

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20121105

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20151130

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees