JP5122818B2 - 薄膜半導体装置の製造方法 - Google Patents
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Description
本発明者は、TFTを製造するに際して、半導体薄膜、例えばポリシリコン薄膜に歪み(ポリシリコン薄膜の面方向の格子定数を増加させる歪み)を加えるための工程を付加することなく、ゲート電極の形成工程のみにより、即ちゲート電極を形成することにより当該ゲート電極の残留応力(面内方向において格子定数を増加させる方向の残留応力)を利用してポリシリコン薄膜に歪みを加えることに想到し、これを実現すべく具体的手法について鋭意検討した。
以下、本発明をポリシリコンTFTの構成及び製造方法に適用した具体的な諸実施形態について、図面を参照しながら詳細に説明する。なお説明の便宜上、ポリシリコンTFTの構成をその製造方法と共に述べる。
図5A〜図5Fは、第1の実施形態によるCMOS型のポリシリコンTFT(以下、単にCMOSTFTと記す)の製造方法を工程順に示す概略断面図である。
先ず、図5Aに示すように、透明絶縁基板、例えばガラス基板1上に膜厚400nm程度のSiO2からなるバッファー層2を介して、プラズマCVD法によりアモルファスシリコン薄膜3を例えば膜厚65nm程度に成膜する。ここで、成膜時に成膜チャンバー内に例えばB2H6 ガスを混入させることにより、アモルファスシリコン薄膜3中にホウ素(B)をドープしている。
本実施形態では、第1の実施形態とほぼ同様のCMOSTFTの構成及び製造方法を開示するが、nチャネルTFTのゲート電極の膜厚をpチャネルTFTのそれよりも薄く形成する点で相違する。図6A〜図6Gは、第2の実施形態によるCMOS型のポリシリコンTFT(以下、単にCMOSTFTと記す)の製造方法を工程順に示す概略断面図である。なお、第1の実施形態と共通する構成部材等については同符号を記す。
ここで、第2の実施形態の変形例について説明する。
図7A,図7Bは、本変形例の主要工程を示す概略断面図である。
先ず、図6A〜図6Eと同様の諸工程を実行する。
本実施形態では、第2の実施形態とほぼ同様のCMOSTFTの構成及び製造方法を開示するが、nチャネルTFTのゲート電極の膜厚をpチャネルTFTのそれよりも薄くするに際して、pチャネルTFTのゲート電極を2層に形成する点で相違する。図8A〜図8Gは、第3の実施形態によるCMOS型のポリシリコンTFT(以下、単にCMOSTFTと記す)の製造方法を工程順に示す概略断面図である。なお、第2の実施形態と共通する構成部材等については同符号を記す。
ここで、第3の実施形態の変形例について説明する。
図9A,図9Bは、本変形例の主要工程を示す概略断面図である。
先ず、図8A〜図8Eと同様の諸工程を実行する。
Claims (2)
- 絶縁基板上に半導体薄膜をパターン形成する工程と、
前記半導体薄膜上に第1のゲート絶縁膜を介して高融点金属からなる第1のゲート電極をパターン形成してnチャネルTFTを形成し、前記半導体薄膜上に第2のゲート絶縁膜を介して高融点金属からなる第2のゲート電極をパターン形成してpチャネルTFTを形成する工程と
を含み、
前記第1のゲート電極を、前記第2のゲート電極の膜厚と同じになるように、前記第2のゲート電極と同時形成し、前記第1のゲート電極の形成された前記半導体薄膜に不純物を導入した後、前記第1のゲート電極のみをエッチングして薄く加工して、前記第2のゲート電極よりも薄く形成し、
前記第1のゲート電極の膜厚を100nm〜500nmの範囲内の値に調節して、その残留応力が前記半導体薄膜の面内方向において前記半導体薄膜の格子定数を増加させる方向に300MPa以上となるように形成し、前記半導体薄膜に前記残留応力に起因した引張り応力を与え、その面方向の格子定数を前記引張り応力のない状態に比して増加した状態に制御することを特徴とする薄膜半導体装置の製造方法。 - 絶縁基板上に半導体薄膜をパターン形成する工程と、
前記半導体薄膜上に第1のゲート絶縁膜を介して高融点金属からなる第1のゲート電極をパターン形成してnチャネルTFTを形成し、前記半導体薄膜上に第2のゲート絶縁膜を介して高融点金属からなる第2のゲート電極をパターン形成してpチャネルTFTを形成する工程と
を含み、
前記第1のゲート電極を、前記第2のゲート電極の膜厚と同じになるように複数の金属層を積層して、前記第2のゲート電極と同時形成し、前記第1のゲート電極の形成された前記半導体薄膜に不純物を導入した後、前記第1のゲート電極のみについて少なくとも最上層の前記金属層をエッチングして薄く加工して、前記第2のゲート電極よりも薄く形成し、
前記第1のゲート電極の膜厚を100nm〜500nmの範囲内の値に調節して、その残留応力が前記半導体薄膜の面内方向において前記半導体薄膜の格子定数を増加させる方向に300MPa以上となるように形成し、前記半導体薄膜に前記残留応力に起因した引張り応力を与え、その面方向の格子定数を前記引張り応力のない状態に比して増加した状態に制御することを特徴とする薄膜半導体装置の製造方法。
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PCT/JP2004/013676 WO2006030522A1 (ja) | 2004-09-17 | 2004-09-17 | 薄膜半導体装置及びその製造方法 |
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JP5122818B2 true JP5122818B2 (ja) | 2013-01-16 |
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TW200611413A (en) | 2006-04-01 |
US20080185667A1 (en) | 2008-08-07 |
JPWO2006030522A1 (ja) | 2008-05-08 |
WO2006030522A1 (ja) | 2006-03-23 |
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