JP5114858B2 - 多層配線基板およびその作製方法 - Google Patents
多層配線基板およびその作製方法 Download PDFInfo
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- JP5114858B2 JP5114858B2 JP2006087431A JP2006087431A JP5114858B2 JP 5114858 B2 JP5114858 B2 JP 5114858B2 JP 2006087431 A JP2006087431 A JP 2006087431A JP 2006087431 A JP2006087431 A JP 2006087431A JP 5114858 B2 JP5114858 B2 JP 5114858B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 24
- 239000002184 metal Substances 0.000 claims description 77
- 229910052751 metal Inorganic materials 0.000 claims description 77
- 238000002844 melting Methods 0.000 claims description 43
- 239000002923 metal particle Substances 0.000 claims description 40
- 230000008018 melting Effects 0.000 claims description 38
- 239000010949 copper Substances 0.000 claims description 32
- 239000010931 gold Substances 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 27
- 239000002245 particle Substances 0.000 claims description 27
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 13
- 229910052718 tin Inorganic materials 0.000 claims description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 229910052709 silver Inorganic materials 0.000 claims description 7
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 150000002739 metals Chemical class 0.000 claims description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- 239000004332 silver Substances 0.000 claims description 4
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims 5
- 238000000576 coating method Methods 0.000 claims 5
- 239000013528 metallic particle Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 72
- 239000000758 substrate Substances 0.000 description 17
- 229910000679 solder Inorganic materials 0.000 description 13
- 238000010586 diagram Methods 0.000 description 10
- 238000003475 lamination Methods 0.000 description 10
- 238000007747 plating Methods 0.000 description 9
- 238000010030 laminating Methods 0.000 description 7
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 6
- 229910020830 Sn-Bi Inorganic materials 0.000 description 5
- 229910018728 Sn—Bi Inorganic materials 0.000 description 5
- 238000005304 joining Methods 0.000 description 5
- 229920002799 BoPET Polymers 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229910052797 bismuth Inorganic materials 0.000 description 3
- 229910002092 carbon dioxide Inorganic materials 0.000 description 3
- 239000001569 carbon dioxide Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910016331 Bi—Ag Inorganic materials 0.000 description 2
- 229910018104 Ni-P Inorganic materials 0.000 description 2
- 229910018536 Ni—P Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052745 lead Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 239000003351 stiffener Substances 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- 101710108306 Bifunctional dihydroflavonol 4-reductase/flavanone 4-reductase Proteins 0.000 description 1
- 229910017755 Cu-Sn Inorganic materials 0.000 description 1
- 229910017927 Cu—Sn Inorganic materials 0.000 description 1
- 101710170824 Dihydroflavonol 4-reductase Proteins 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000004873 anchoring Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- FBAFATDZDUQKNH-UHFFFAOYSA-M iron chloride Chemical compound [Cl-].[Fe] FBAFATDZDUQKNH-UHFFFAOYSA-M 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
- H05K3/4617—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
- H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0206—Materials
- H05K2201/0215—Metallic fillers
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10378—Interposers
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3473—Plating of solder
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
(a)第1の金属粒子の集合体である内部導体と、
(b)前記内部導体を覆う第2の金属膜と
で構成される。
(a)第1の絶縁層上に配線パターンを形成する工程と、
(b)前記配線パターンのうち、ビア接続されるランド部分に、低融点金属膜を形成する工程と、
(c)第2の絶縁層にビア孔を形成し、前記ビア孔に金属粒子を充填する工程と、
前記第1の絶縁層と第2の絶縁層を重ね合わせて、前記ビア孔に充填された金属粒子とランド上の低融点金属膜とを接触させ、前記低融点金属を前記ビア孔内の金属粒子表面に拡散させることによって、前記配線パターンを前記ビア孔に接続する工程と、
を含む。
その後、図5(c)に示すように、真空プレスを用いて200℃、3MPaで本積層して、多層配線基板1Aを完成する。この低温真空プレスで、ランド52p、62上に形成されたSn−Biはんだ63が、Cu粒子22の表面に拡散して、Cu粒子間を密着接合するとともに、ランド52p、62を電気接続する接合ビア65が形成される。接合ビア65の内部はCu粒子であるが、その表面は、Au中にSn、Biが拡散した低融点金属膜である。
(付記1) 少なくとも第1配線層と第2配線層が絶縁層を介して積層された多層配線層と、
前記第1配線層と第2配線層を電気的に接続する接続ビアと
を有し、前記接続ビアは、第1の金属粒子の集合体である内部導体と、前記内部導体を覆う第2の金属膜とで構成されることを特徴とする多層配線基板。
(付記2) 前記第2の金属膜の融点は、前記第1の金属粒子の融点よりも低いことを特徴とする付記1に記載の多層配線基板。
(付記3) 前記第1の金属粒子は、銅(Cu)または銅合金であり、前記第2の金属膜は、錫(Sn)または錫合金を主成分とすることを特徴とする付記1に記載の多層配線基板。
(付記4) 前記第2の金属膜を構成する錫合金は、錫(Sn)に、Bi,Pb,Zn,Agの少なくとも1種類の金属元素が添加されていることを特徴とする付記3に記載の多層配線基板。
(付記5) 前記第1の金属粒子の直径は、5μm〜15μmであることを特徴とする付記1に記載の多層配線基板。
(付記6) 前記第2の金属膜には、金(Au)が拡散していることを特徴とする付記1〜5のいずれかに記載の多層配線基板。
(付記7) 前記絶縁層は、樹脂絶縁層であることを特徴とする付記1に記載の多層配線基板。
(付記8) 第1の絶縁層上に配線パターンを形成する工程と、
前記配線パターンのうち、ビア接続されるランド部分に、低融点金属膜を形成する工程と、
第2の絶縁層にビア孔を形成し、前記ビア孔に金属粒子を充填する工程と、
前記第1の絶縁層と第2の絶縁層を重ね合わせて、前記ビア孔に充填された金属粒子とランド上の低融点金属膜とを接触させ、前記低融点金属を前記ビア孔内の金属粒子表面に拡散させることによって、前記配線パターンを前記ビア孔に接続する工程と、
を含むことを特徴とする多層配線基板の作製方法。
(付記9) 前記金属粒子は、その表面に金(Au)または銀(Ag)の皮膜を有することを特徴とする付記8に記載の多層配線基板の作製方法。
(付記10) 前記低融点金属膜を、錫または錫合金で形成することを特徴とする付記8に記載の多層配線基板の作製方法。
(付記11) 前記拡散接続する工程は、200℃での真空プレスを含むことを特徴とする付記8に記載の多層配線基板の作製方法。
(付記12) 前記第1の絶縁膜上の配線パターンは片面配線パターンであり、
前記第1の絶縁層に、前記ランド部分に到達する第2のビア孔を形成する工程と、
前記第2のビア孔に、前記金属粒子を充填する工程と
をさらに含むことを特徴とする付記8に記載の多層配線基板の作製方法。
(付記13) 前記金属粒子の平均直径は10μm以下であることを特徴とする付記8に記載の多層配線基板の作製方法。
10、30 多層配線層
11、21、31、51,71 絶縁層
12、32、52p、62、72p 配線パターン(ランド)
13、33、63、73 低融点金属
20 接着層
22 AuコードCu粒子(金属粒子)
25、65、75 接合ビア
Claims (10)
- 少なくとも第1配線層と第2配線層が絶縁層を介して積層された多層配線層と、
前記第1配線層と第2配線層を電気的に接続する接続ビアと
を有し、前記接続ビアは、第1金属の粒子の集合体である内部導体と、前記接続ビアの長さの全体にわたって前記内部導体を覆う第2金属の接合膜とを含み、
前記第2金属は、前記第1金属の粒子の表面皮膜を構成していた前記第1金属と異なる種類の金属と、前記第1金属の融点よりも低くかつ前記第1金属と異なる種類の金属の融点よりも低い融点の低融点金属とが拡散した膜である
ことを特徴とする多層配線基板。 - 前記第2金属の融点は、前記第1金属の融点よりも低いことを特徴とする請求項1に記載の多層配線基板。
- 前記第1金属は、銅(Cu)または銅合金であり、前記第2金属は、錫(Sn)または錫合金を主成分とすることを特徴とする請求項1に記載の多層配線基板。
- 前記第1金属の粒子の直径は、5μm〜15μmであることを特徴とする請求項1に記載の多層配線基板。
- 前記第1金属と異なる種類の金属として、金(Au)または銀(Ag)が前記第2金属の接合膜中に拡散していることを特徴とする請求項1〜4のいずれかに記載の多層配線基板。
- 第1の絶縁層上に配線パターンを形成する工程と、
前記配線パターンのうち、ビア接続されるランド部分に、低融点金属膜を形成する工程と、
第2の絶縁層に第1のビア孔を形成し、前記第1のビア孔に、第1金属の粒子の表面を前記第1金属と異なる金属で皮膜した金属粒子を充填する工程と、
前記第1の絶縁層と前記第2の絶縁層を重ね合わせて、前記第1のビア孔に充填された前記金属粒子と前記ランド上の前記低融点金属膜とを接触させ、前記低融点金属を前記第1のビア孔の長さ全体にわたって前記金属粒子の前記皮膜中に拡散させることによって、前記配線パターンを前記第1のビア孔に接続する工程と、
を含み、前記低融点金属の融点は、前記第1金属の融点及び前記皮膜を構成する前記第1金属と異なる金属の融点よりも低いことを特徴とする多層配線基板の作製方法。 - 前記金属粒子の前記皮膜は、金(Au)または銀(Ag)の皮膜であることを特徴とする請求項6に記載の多層配線基板の作製方法。
- 前記低融点金属膜を、錫または錫合金で形成することを特徴とする請求項6に記載の多層配線基板の作製方法。
- 前記拡散接続する工程は、200℃での真空プレスを含むことを特徴とする請求項6に記載の多層配線基板の作製方法。
- 前記第1の絶縁層上の配線パターンは片面配線パターンであり、
前記第1の絶縁層に、前記ランド部分に到達する第2のビア孔を形成する工程と、
前記第2のビア孔に、前記金属粒子を充填する工程と
をさらに含むことを特徴とする請求項6に記載の多層配線基板の作製方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2006087431A JP5114858B2 (ja) | 2006-03-28 | 2006-03-28 | 多層配線基板およびその作製方法 |
US11/474,453 US8158503B2 (en) | 2006-03-28 | 2006-06-26 | Multilayer interconnection substrate and method of manufacturing the same |
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Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006087431A JP5114858B2 (ja) | 2006-03-28 | 2006-03-28 | 多層配線基板およびその作製方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007266183A JP2007266183A (ja) | 2007-10-11 |
JP5114858B2 true JP5114858B2 (ja) | 2013-01-09 |
Family
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-
2006
- 2006-03-28 JP JP2006087431A patent/JP5114858B2/ja not_active Expired - Fee Related
- 2006-06-26 US US11/474,453 patent/US8158503B2/en not_active Expired - Fee Related
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JP2007266183A (ja) | 2007-10-11 |
US20070232059A1 (en) | 2007-10-04 |
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