JP5108489B2 - プラズマ処理方法 - Google Patents
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- JP5108489B2 JP5108489B2 JP2007327345A JP2007327345A JP5108489B2 JP 5108489 B2 JP5108489 B2 JP 5108489B2 JP 2007327345 A JP2007327345 A JP 2007327345A JP 2007327345 A JP2007327345 A JP 2007327345A JP 5108489 B2 JP5108489 B2 JP 5108489B2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Description
Claims (6)
- 半導体基板上に積層された複数層の薄膜と、積層化された薄膜の上に設けたフォトレジストマスクパターンとを有する被処理材を、ゲート電極を形成するためにプラズマエッチング装置を用いてプラズマ処理する方法において、
窒素の元素を含むガスをプラズマ化することによって前記フォトレジストマスクパターンにプラズマキュア処理を行いフォトレジストマスクパターンの表面と側面の凹凸を減少させるキュア処理工程と、
表面と側面の凹凸を減少させたフォトレジストマスクパターンを用いて該フォトレジストマスクパターンの下に設けた積層化された薄膜層をプラズマエッチング処理するエッチング処理工程とを備え、
前記窒素の元素を含むガスは、窒素ガス(N2)であり、
前記キュア処理工程は、処理圧力を0.1Pa以上100Pa以下、前記被処理材に印加するRFバイアス電力を0W以上100W以下とし、さらに前記窒素の元素を含むガスに堆積性ガスを混合させた混合ガスをプラズマ化することによってフォトレジストマスクパターンの縦エッチングレートを抑制しながらフォトレジストマスクパターンの表面と側面の凹凸を減少させ、
前記堆積性ガスは、メタン(CH 4 )ガスとトリフルオロメタン(CHF 3 )ガスとジフルオロメタン(CH 2 F 2 )ガスとフルオロメタン(CH 3 F)ガスとを除くフルオロカーボンガス(C X F Y )、四フッ化ケイ素(SiF 4 )ガスの中から少なくとも1種以上のガスであることを特徴とするプラズマ処理方法。 - 請求項1記載のプラズマ処理方法において、
前記キュア処理工程に用いられる前記混合ガスに臭化水素または希ガス元素もしくはハロゲン元素のガスの内の少なくともいずれか1以上のガスを添加し、前記フォトレジストマスクパターンにプラズマキュア処理を行い、前記フォトレジストマスクパターンの表面と側面の凹凸を減少させることを特徴とするプラズマ処理方法。 - 請求項1記載のプラズマ処理方法において、
前記積層化された薄膜は、MOS(Metal Oxide Semiconductor)トランジスタのゲート電極を形成する層を少なくとも1層以上含むことを特徴とするプラズマ処理方法。 - 請求項1記載のプラズマ処理方法において、
前記キュア処理工程における前記被処理材に印加するRFバイアス電力を0Wとすることを特徴とするプラズマ処理方法。 - 請求項1記載のプラズマ処理方法において、
前記キュア処理工程における被処理材の処理温度と前記エッチング処理工程における被処理材の処理温度を異ならせることを特徴とするプラズマ処理方法。 - 請求項1記載のプラズマ処理方法において、
前記プラズマエッチング装置は、ECR(Electron Cyclotron Resonance)エッチング装置であることを特徴とするプラズマ処理方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007327345A JP5108489B2 (ja) | 2007-01-16 | 2007-12-19 | プラズマ処理方法 |
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Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007007437 | 2007-01-16 | ||
JP2007007437 | 2007-01-16 | ||
JP2007327345A JP5108489B2 (ja) | 2007-01-16 | 2007-12-19 | プラズマ処理方法 |
Publications (2)
Publication Number | Publication Date |
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JP2008198988A JP2008198988A (ja) | 2008-08-28 |
JP5108489B2 true JP5108489B2 (ja) | 2012-12-26 |
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Country Status (4)
Country | Link |
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US (1) | US8497213B2 (ja) |
JP (1) | JP5108489B2 (ja) |
KR (1) | KR100918864B1 (ja) |
TW (1) | TW200845185A (ja) |
Families Citing this family (352)
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JP2010062212A (ja) * | 2008-09-01 | 2010-03-18 | Oki Semiconductor Co Ltd | 半導体装置の製造方法 |
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JP5063626B2 (ja) * | 2009-02-19 | 2012-10-31 | 株式会社日立ハイテクノロジーズ | プラズマ処理装置 |
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US8529776B2 (en) * | 2011-07-25 | 2013-09-10 | Applied Materials, Inc. | High lateral to vertical ratio etch process for device manufacturing |
US8609550B2 (en) | 2011-09-08 | 2013-12-17 | Synopsys, Inc. | Methods for manufacturing integrated circuit devices having features with reduced edge curvature |
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US20130267097A1 (en) * | 2012-04-05 | 2013-10-10 | Lam Research Corporation | Method and apparatus for forming features with plasma pre-etch treatment on photoresist |
JP6008608B2 (ja) * | 2012-06-25 | 2016-10-19 | 東京エレクトロン株式会社 | レジストマスクの処理方法 |
JP6030886B2 (ja) * | 2012-08-09 | 2016-11-24 | 東京エレクトロン株式会社 | プラズマエッチング方法及びプラズマエッチング装置 |
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