JP5022652B2 - Circuit module manufacturing method and circuit module - Google Patents

Circuit module manufacturing method and circuit module Download PDF

Info

Publication number
JP5022652B2
JP5022652B2 JP2006238242A JP2006238242A JP5022652B2 JP 5022652 B2 JP5022652 B2 JP 5022652B2 JP 2006238242 A JP2006238242 A JP 2006238242A JP 2006238242 A JP2006238242 A JP 2006238242A JP 5022652 B2 JP5022652 B2 JP 5022652B2
Authority
JP
Japan
Prior art keywords
circuit module
width
substrate
insulating layer
shield layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2006238242A
Other languages
Japanese (ja)
Other versions
JP2008042152A (en
Inventor
雅哉 島村
穂 湯浅
岳彦 甲斐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP2006238242A priority Critical patent/JP5022652B2/en
Publication of JP2008042152A publication Critical patent/JP2008042152A/en
Application granted granted Critical
Publication of JP5022652B2 publication Critical patent/JP5022652B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Description

本発明は、基板上に半導体素子やチップ状電子部品を搭載するとともに、搭載された部品を覆う第一層の絶縁層と該絶縁層を覆う第二層のシールド層とを有する平板状の回路モジュールの製造方法に関し、前記平板状の回路モジュールの端面において前記基板と前記シールド層との境界に隙間を生じないようにした回路モジュールの製造方法、及び回路モジュールに関する。  The present invention provides a flat circuit having a first layer insulating layer covering a mounted component and a second layer shielding layer covering the mounted component while mounting a semiconductor element or a chip-shaped electronic component on a substrate. The present invention relates to a module manufacturing method, and more particularly to a circuit module manufacturing method and a circuit module in which no gap is formed at the boundary between the substrate and the shield layer at an end face of the flat circuit module.

従来、基板上に複数の要素部品を搭載するとともに、搭載された部品を樹脂モールドにより被覆したものや、搭載された部品を被覆するように金属製のキャップを被せたものが存在する。
また、特許文献１に示すように、基板上に搭載された部品を絶縁性樹脂層からなる第一層で被覆し、さらに導電性樹脂からなる第二層で被覆してシールド層を形成し、さらに小型化を可能とした回路モジュールが提案されている。
上記背景技術の回路モジュールは、図５に示されるように、内部及びその表面に回路配線２ａ，２ｂ，２ｃ，２ｄ，２ｅ，２ｆを備えた基板１の一方の主面上に半導体素子やチップ状の電子部品等の部品３が搭載されるとともに、導電ワイヤや、ハンダや導電性接着剤等の接合材からなる接続手段４により図示省略した前記基板の表面の回路配線２に接続されている。
上記部品及び上記接続手段を被覆するように絶縁性樹脂からなる第一層の絶縁層５が形成された後、該絶縁層５を分断するとともに先端が前記基板１に至る切り溝６が形成され、少なくとも該切り溝６に充填されるように前記絶縁層５を被覆する導電性樹脂からなる第二層のシールド層７と、が順次形成され、さらに前記切り溝６に充填された導電性樹脂７ｂを分割するように分割溝９により分割され、回路モジュール８が得られる。
尚、上記背景技術の回路モジュールの製造方法においては、例えば減圧室中にて導電性樹脂の塗料を塗布したのちに常圧に戻すことにより、基板１上に搭載された部品３を被覆する絶縁層５に該絶縁層５を分断するように形成された切り溝６の内部に前記導電性樹脂の塗料が充填される。Conventionally, a plurality of component parts are mounted on a substrate, and the mounted parts are covered with a resin mold, or a metal cap is applied so as to cover the mounted parts.
Moreover, as shown in Patent Document 1, a component mounted on a substrate is covered with a first layer made of an insulating resin layer, and further covered with a second layer made of a conductive resin to form a shield layer, Further, circuit modules that can be miniaturized have been proposed.
As shown in FIG. 5, the circuit module of the above-described background art has a semiconductor element and a chip on one main surface of a substrate 1 provided with circuit wirings 2a, 2b, 2c, 2d, 2e, and 2f inside and on the surface thereof. A component 3 such as an electronic component is mounted and connected to the circuit wiring 2 on the surface of the substrate (not shown) by connection means 4 made of a bonding material such as a conductive wire or solder or conductive adhesive. .
After the first insulating layer 5 made of an insulating resin is formed so as to cover the parts and the connecting means, the insulating layer 5 is divided, and a kerf 6 whose tip reaches the substrate 1 is formed. And a second shield layer 7 made of a conductive resin covering the insulating layer 5 so as to fill at least the cut groove 6, and the conductive resin further filled in the cut groove 6. The circuit module 8 is obtained by dividing by the dividing groove 9 so as to divide 7b.
In the method of manufacturing the circuit module according to the background art, for example, an insulating material that covers the component 3 mounted on the substrate 1 is obtained by applying a conductive resin coating in a decompression chamber and then returning to normal pressure. The conductive resin coating is filled in the kerf 6 formed to divide the insulating layer 5 into the layer 5.

特開２００４−１７２１７６号公報JP 2004-172176 A

しかしながら、上記背景技術の回路モジュールの製造方法においても、前記切り溝の内部に導電性樹脂の塗料を充填する際に、該溝の内部に残存する気体をゼロにすることはできず、前記基板１の切り溝６の底面と前記導電性樹脂からなるシールド層７の縁部の先端との間に空気溜まり６ｃが生じてしまう。
この状態で前記導電性樹脂が硬化され、前記切り溝に沿って分割されると、前記基板のの端面と前記シールド層の端面とが同一平面上に位置するとともに、該平面上において前記絶縁層を覆うシールド層の縁部の下端とこれに対向する前記切り溝の内面との境界に隙間が生じ、前記シールド層の剥がれ落ちが生じて外部からの電磁界や静電気の影響を受け易くなり回路モジュールの電気的特性が変動しやすいという課題があった。However, even in the method of manufacturing the circuit module according to the background art, when the conductive resin paint is filled in the cut groove, the gas remaining in the groove cannot be reduced to zero. An air pocket 6c is generated between the bottom surface of one kerf 6 and the edge of the edge of the shield layer 7 made of the conductive resin.
When the conductive resin is cured in this state and divided along the kerf, the end surface of the substrate and the end surface of the shield layer are located on the same plane, and the insulating layer is on the plane. A gap is generated at the boundary between the lower end of the edge of the shield layer covering the inner surface of the shield layer and the inner surface of the kerf facing the shield layer, and the shield layer is peeled off so that it is easily affected by an external electromagnetic field or static electricity. There was a problem that the electrical characteristics of the module were likely to fluctuate.

本発明の目的は、上記課題を解決して、平板状の回路モジュールの端面において絶縁層を覆うシールド層の縁部の下端とこれに対向する切り溝の内面との境界に隙間が生じない回路モジュールの製造方法を提供することにある。
また本発明の目的は、前記シールド層の縁部の剥がれ落ちが防止され、電気的特性の変動が生じにくい回路モジュールを提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and a circuit in which no gap is generated at the boundary between the lower end of the edge of the shield layer covering the insulating layer and the inner surface of the kerf facing the end of the flat circuit module. It is to provide a method for manufacturing a module.
Another object of the present invention is to provide a circuit module in which the edge of the shield layer is prevented from being peeled off and the electrical characteristics are not easily changed.

上記目的を達成するため、本発明の回路モジュールの製造方法は、
（１） 基板上に複数の部品を配置する工程と、前記各部品を被覆する絶縁層を形成する工程と、前記絶縁層を被覆する導電性樹脂からなるシールド層を形成する工程と、前記シールド層が形成された基板を分割する工程と、を有する回路モジュールの製造方法であって、前記絶縁層を被覆するシールド層を形成する前に予め深さ方向の基端部の幅Ｗ１に比べて先端部の幅Ｗ２が小さい切り溝を少なくとも前記絶縁層に形成し、少なくとも前記切り溝内に充填されるように導電性樹脂を塗布してシールド層を形成した後、前記切り溝の先端部に沿って前記先端部の幅Ｗ２より大きく前記き基端部の幅Ｗ１より小さい幅Ｗ３で切削して前記基板を分割するものである。（・・・以下、第１の課題解決手段と称する。）In order to achieve the above object, a method for manufacturing a circuit module of the present invention includes:
(1) A step of disposing a plurality of components on a substrate, a step of forming an insulating layer covering each of the components, a step of forming a shield layer made of a conductive resin covering the insulating layer, and the shield Dividing the substrate on which the layer is formed, and a method of manufacturing the circuit module, wherein the width of the base end portion W1 in the depth direction is previously set before forming the shield layer covering the insulating layer. A kerf having a small width W2 at the tip is formed in at least the insulating layer, and a shield layer is formed by applying a conductive resin so as to fill at least the kerf. The substrate is divided by cutting along a width W3 that is larger than the width W2 of the distal end portion and smaller than the width W1 of the proximal end portion. (... hereinafter referred to as first problem solving means)

また、上記回路モジュールの製造方法の主要な形態の一つは、
（２）前記切り溝が段付溝である。（・・・以下、第２の課題解決手段と称する。）One of the main forms of the circuit module manufacturing method is:
(2) The kerf is a stepped groove. (Hereinafter referred to as second problem solving means)

また、上記回路モジュールの製造方法の形態の一つは、
（３）前記段付溝が異なる複数の切削手段で形成されるものである。（・・・以下、第３の課題解決手段と称する。）One of the forms of the circuit module manufacturing method is as follows:
(3) The stepped groove is formed by a plurality of cutting means different from each other. (Hereinafter referred to as third problem solving means)

また、上記回路モジュールの製造方法の主要な形態の一つは、
（４）前記切り溝がテーパ付溝である。（・・・以下、第４の課題解決手段と称する。）One of the main forms of the circuit module manufacturing method is:
(4) The kerf is a tapered groove. (Hereinafter referred to as fourth problem solving means)

上記第１の課題解決手段による作用は次の通りである。すなわち、
前記絶縁層を被覆するシールド層を形成する前に予め深さ方向の基端部の幅Ｗ１に比べて先端部の幅Ｗ２が小さい切り溝を少なくとも前記絶縁層に形成し、少なくとも前記切り溝内に充填されるように導電性樹脂を塗布してシールド層を形成した後、前記切り溝の先端部に沿って前記先端部の幅Ｗ２より大きく前記き基端部の幅Ｗ１より小さい幅Ｗ３で切削して前記基板を分割する。これにより、前記切り溝に導電性樹脂を充填する際に発生する空気溜まりが切り溝の先端付近に寄せ集められ、切削による分割の際に切り代として取り除かれるため、前記回路モジュールの端面において、前記絶縁層を覆うシールド層の縁部の下端とこれに対向する前記切り溝の内面とが密着している。The operation of the first problem solving means is as follows. That is,
Before forming the shield layer covering the insulating layer, a kerf having a width W2 at the distal end smaller than the width W1 at the base end in the depth direction is formed in the insulating layer at least in advance. After forming a shield layer by applying a conductive resin so as to be filled, the width W3 is larger than the width W2 of the distal end portion and smaller than the width W1 of the proximal end portion along the distal end portion of the kerf. The substrate is divided by cutting. Thereby, air pockets generated when filling the kerf with conductive resin are gathered near the tip of the kerf, and are removed as a cutting allowance when divided by cutting, so at the end face of the circuit module, The lower end of the edge of the shield layer covering the insulating layer is in close contact with the inner surface of the kerf facing the edge.

上記第２の課題解決手段による作用は次の通りである。すなわち、前記切り溝が段付溝であるので、絶縁層の端面を覆うシールド層の縁部の厚みが厚く形成され、シールド層の剥離が生じにくい。  The operation of the second problem solving means is as follows. That is, since the kerf is a stepped groove, the edge of the shield layer covering the end face of the insulating layer is formed thick, and the shield layer hardly peels off.

上記第３の課題解決手段による作用は次の通りである。すなわち、前記段付溝が異なる複数の切削手段で形成されるので、発生する空気溜まりの量に応じて、空気溜まりを収容するための溝の深さを任意に設定することができるとともに、切り溝形成時の基板や搭載部品へのダメージの発生を抑制することができる。  The operation of the third problem solving means is as follows. That is, since the stepped groove is formed by a plurality of different cutting means, the depth of the groove for accommodating the air pool can be arbitrarily set according to the amount of the air pool generated, and It is possible to suppress the occurrence of damage to the substrate and the mounted component when forming the groove.

上記第４の課題解決手段による作用は次の通りである。すなわち、前記切り溝がテーパ付溝であるので、空気溜まりの量がばらついた場合であっても分割カット時のブレード厚みを選択することにより前記空気溜まりを確実に除去することができる。  The operation of the fourth problem solving means is as follows. That is, since the kerf is a tapered groove, the air stagnation can be surely removed by selecting the blade thickness at the time of split cutting even when the amount of air stagnation varies.

本発明の回路モジュールの製造方法は、シールド層の縁部のはがれ落ちが防止され、回路モジュールの電気的特性の変動が抑制される。         According to the method for manufacturing a circuit module of the present invention, peeling of the edge of the shield layer is prevented, and fluctuations in the electrical characteristics of the circuit module are suppressed.

以下、本発明の回路モジュールの製造方法の第１の実施形態について、図１を参照して説明する。図１は本実施形態の回路モジュールの製造方法を説明するための図であり、図１（Ａ）〜図１（Ｅ）は、本実施形態の回路モジュールの製造方法の各ステップを示す部分拡大断面図である。  Hereinafter, a first embodiment of a circuit module manufacturing method of the present invention will be described with reference to FIG. FIG. 1 is a diagram for explaining a circuit module manufacturing method according to the present embodiment. FIGS. 1A to 1E are partially enlarged views showing respective steps of the circuit module manufacturing method according to the present embodiment. It is sectional drawing.

本実施形態の回路モジュールの製造方法は、基板１１上に複数の部品１３を配置する工程と、前記各部品１３を被覆する絶縁層１５を形成する工程と、該絶縁層１５を被覆する導電性樹脂からなるシールド層１７を形成する工程と、前記シールド層１７が形成された基板を分割する工程と、を有する回路モジュール１８の製造方法であって、
前記絶縁層１５を被覆するシールド層１７を形成する前に予め深さ方向の基端部１６ｂの幅Ｗ１に比べて先端部１６ａの幅Ｗ２が小さい切り溝１６を少なくとも前記絶縁層１５に形成し、少なくとも前記切り溝１６内に充填されるように導電性樹脂を塗布してシールド層１７を形成した後、前記切り溝１６の先端部１６ａに沿って前記先端部１６ａの幅Ｗ２より大きく前記基端部１６ｂの幅Ｗ１より小さい幅Ｗ３で切削して前記基板１１を分割するものである。The circuit module manufacturing method of the present embodiment includes a step of disposing a plurality of components 13 on a substrate 11, a step of forming an insulating layer 15 that covers each of the components 13, and a conductive property that covers the insulating layer 15. A method of manufacturing a circuit module 18 comprising: a step of forming a shield layer 17 made of resin; and a step of dividing a substrate on which the shield layer 17 is formed,
Before forming the shield layer 17 that covers the insulating layer 15, at least the kerf 16 having a width W2 of the distal end portion 16a smaller than the width W1 of the proximal end portion 16b in the depth direction is previously formed in the insulating layer 15. After forming a shield layer 17 by applying a conductive resin so as to fill at least the cut groove 16, the base is larger than the width W2 of the front end portion 16a along the front end portion 16a of the cut groove 16. The substrate 11 is divided by cutting with a width W3 smaller than the width W1 of the end portion 16b.

また、本実施形態においては、前記切り溝１６が前記基端部１６ｂの幅Ｗ１が前記先端部１６ａの幅Ｗ２よりも広くなっている段付溝として形成されている。  Further, in the present embodiment, the kerf 16 is formed as a stepped groove in which the width W1 of the base end portion 16b is wider than the width W2 of the tip end portion 16a.

具体的には、上記基板１１は、（例えば厚み１ｍｍの）セラミック基板からなり、該基板１１に内蔵された配線パターン１２ａ，１２ｃと、該基板１１の底面に形成された配線パターン１２ｅ及び１２ｆと、これら配線パターン間を接続するスルーホール導体１２ｂ及び１２ｄとを備えるとともに、該基板の上面側には図示省略した部品搭載用ランドが形成されている。
まず、図１（Ａ）に示すように、上記基板１１の上面側の部品搭載ランド上に半導体素子やチップ状電子部品等からなる部品１３を搭載するとともに、導電ワイヤや、ハンダや導電性接着剤等の接合剤からなる接続手段１４により前記部品１３の電極と前記部品搭載ランドとを導電接続する。
次に、図１（Ｂ）に示すように、上記基板１１上に搭載された部品１３及び前記接続手段１４を被覆するように真空印刷法を用いて絶縁性樹脂の塗料を塗布し、硬化して絶縁層１５を形成する。
次に、図１（Ｃ）に示すように、上記絶縁層１５から前記基板１１に亘って段付の切り溝１６を形成する。このとき、該切り溝１６は、前記基板１１に切り込む深さ方向の先端部１６ａの幅Ｗ２が前記基端部１６ｂの幅Ｗ１よりも小さくなるように、先端に段付の切削ブレードを切削手段に用いて形成する。
次に、図１（Ｄ）に示すように、上記切り溝１６の内部に導電性樹脂１７ｂが充填されるように上記絶縁層と同様に、真空印刷法を用いて導電性樹脂の塗料を塗布し硬化して、前記絶縁層１５を覆うシールド層１７を形成する。このとき、前記切り溝１６の深さ方向の先端部１６ａには空気溜まり１６ｃが形成されるものの、該先端部１６ａを除く切り溝１６の内面には前記シールド層１７を形成する導電性樹脂１７ｂが密着して、隙間が存在しない。
次に、図１（Ｄ）に示すように、前記切り溝１６の先端部１６ａに沿って前記切り溝１６の先端部１６ａの幅Ｗ２より大きく該切り溝１６の基端部１６ｂの幅Ｗ１より小さい幅Ｗ３で公知のダイシング装置等の切削手段により切削して前記基板を分割し、図１（Ｅ）に示すように、シールド層１７の端面と基板１１の端面とが同一平面上に位置するとともに、該平面上において前記絶縁層１５を覆うシールド層１７の縁部１７ｂの下端とこれに対向する前記切り溝１６の内面とが密着している（例えば厚み４ｍｍの）回路モジュール１８を得る。Specifically, the substrate 11 is made of a ceramic substrate (for example, having a thickness of 1 mm), wiring patterns 12a and 12c built in the substrate 11, and wiring patterns 12e and 12f formed on the bottom surface of the substrate 11. The circuit board includes through-hole conductors 12b and 12d for connecting the wiring patterns, and a component mounting land (not shown) is formed on the upper surface of the substrate.
First, as shown in FIG. 1A, a component 13 made of a semiconductor element, a chip-shaped electronic component, or the like is mounted on a component mounting land on the upper surface side of the substrate 11, and a conductive wire, solder, or conductive adhesive is mounted. The electrode of the component 13 and the component mounting land are conductively connected by connecting means 14 made of a bonding agent such as an agent.
Next, as shown in FIG. 1B, an insulating resin coating is applied and cured by vacuum printing so as to cover the component 13 mounted on the substrate 11 and the connecting means 14. Thus, the insulating layer 15 is formed.
Next, as shown in FIG. 1C, a stepped kerf 16 is formed from the insulating layer 15 to the substrate 11. At this time, the kerf 16 has a cutting means having a stepped cutting blade at the tip so that the width W2 of the tip portion 16a in the depth direction cut into the substrate 11 is smaller than the width W1 of the base end portion 16b. Used to form.
Next, as shown in FIG. 1D, a conductive resin coating is applied using a vacuum printing method in the same manner as the insulating layer so that the inside of the cut groove 16 is filled with the conductive resin 17b. Then, a shield layer 17 covering the insulating layer 15 is formed. At this time, an air reservoir 16c is formed at the front end portion 16a in the depth direction of the cut groove 16, but the conductive resin 17b that forms the shield layer 17 on the inner surface of the cut groove 16 excluding the front end portion 16a. Are closely attached and there is no gap.
Next, as shown in FIG. 1D, the width W2 of the base end portion 16b of the cut groove 16 is larger than the width W2 of the front end portion 16a of the cut groove 16 along the front end portion 16a of the cut groove 16. The substrate is divided by a cutting means such as a known dicing apparatus with a small width W3, and the end surface of the shield layer 17 and the end surface of the substrate 11 are positioned on the same plane as shown in FIG. At the same time, the circuit module 18 is obtained in which the lower end of the edge portion 17b of the shield layer 17 covering the insulating layer 15 and the inner surface of the kerf 16 opposed thereto are in close contact with each other (for example, 4 mm thick).

次に、本実施形態の回路モジュール１８の第１の実施形態について説明する。本実施形態の回路モジュール１８は、図１（Ｅ）に示されるように、基板１１上に複数の部品１３が搭載され該各部品１３が絶縁層１５で被覆され該絶縁層１５がシールド層１７で被覆された回路モジュール１８であって、前記基板１１の端面と前記シールド層１７の端面とが同一平面上に位置するとともに、該平面上において前記絶縁層１５を覆うシールド層１７の縁部１７ｂの下端とこれと対向する前記切り溝１６の内面とが密着しているので、前記シールド層の縁部の剥がれ落ちが防止され、電気的特性の変動が生じにくいというメリットを有する。  Next, a first embodiment of the circuit module 18 of the present embodiment will be described. In the circuit module 18 of the present embodiment, as shown in FIG. 1 (E), a plurality of components 13 are mounted on a substrate 11, each component 13 is covered with an insulating layer 15, and the insulating layer 15 is shield layer 17. The end surface of the substrate 11 and the end surface of the shield layer 17 are located on the same plane, and the edge portion 17b of the shield layer 17 covers the insulating layer 15 on the plane. Since the lower end of the shield layer and the inner surface of the kerf 16 facing this are in close contact with each other, the edge of the shield layer is prevented from being peeled off, and there is an advantage that the electrical characteristics hardly change.

上記基板１１としては、セラミック基板、樹脂基板等のうちから用途に応じて適宜選択して用いることができる。
セラミック基板としては、アルミナ基板、その他の高温で焼結するもののほか、所謂ＬＴＣＣ基板を用いることもできる。
樹脂基板としては、ガラス・エポキシ樹脂等が用いられる。As the substrate 11, a ceramic substrate, a resin substrate, or the like can be appropriately selected and used depending on the application.
As the ceramic substrate, an alumina substrate and other so-called LTCC substrates can be used in addition to those sintered at a high temperature.
As the resin substrate, glass, epoxy resin or the like is used.

上記配線パターンを内蔵する基板としては、上記セラミック基板と同時焼成可能な金属粉末を含有する導電性ペーストをセラミックグリーンシートの表面に印刷し、積層した後、焼成して得られるセラミック多層配線基板や、表面に銅プリント配線が形成された樹脂基板を積層する等により得られる多層プリント配線基板等から用途に応じて適宜選択して用いることができる。  As a substrate containing the wiring pattern, a ceramic multilayer wiring substrate obtained by printing a conductive paste containing metal powder that can be fired simultaneously with the ceramic substrate on the surface of the ceramic green sheet, laminating, and firing. In addition, a multilayer printed wiring board obtained by laminating a resin substrate having a copper printed wiring formed on its surface can be appropriately selected and used depending on the application.

上記基板１１上に搭載される部品１３としては、ベアチップその他の半導体素子のほか、コンデンサ、抵抗、コイル等のチップ状電子部品があげられる。  Examples of the component 13 mounted on the substrate 11 include bare chip and other semiconductor elements, and chip-shaped electronic components such as capacitors, resistors, and coils.

上記絶縁層を形成するための絶縁性樹脂としては、エポキシ樹脂その他の熱硬化性樹脂や紫外線硬化性樹脂等が好ましい。前記基板上への絶縁層の形成は、トランスファモールド法やポッティング法或いは真空印刷法等のモールド法を用いることができる。
上記真空印刷法による前記基板上への絶縁層の形成は、真空（減圧）時と真空（減圧）を開放して大気圧に戻したときの差圧を利用して、前記基板と搭載部品との隙間に存在する気体の体積を減少させることで、前記隙間内への前記絶縁性樹脂の充填率を高める。The insulating resin for forming the insulating layer is preferably an epoxy resin or other thermosetting resin or ultraviolet curable resin. The insulating layer can be formed on the substrate by a molding method such as a transfer molding method, a potting method, or a vacuum printing method.
The formation of the insulating layer on the substrate by the vacuum printing method uses the differential pressure between when the vacuum (reduced pressure) is released and when the vacuum (reduced pressure) is released to return to atmospheric pressure, By reducing the volume of the gas existing in the gap, the filling rate of the insulating resin into the gap is increased.

上記シールド層を形成するための導電性樹脂としては、上記エポキシ樹脂その他の熱硬化性樹脂にＡｇ粉やＣｕ粉等の導電性金属粉末を混合したものが好ましい。上記絶縁層を覆うシールド層の形成は、トランスファモールド法やポッティング法或いは真空印刷法等のモールド法を用いることができる。
上記真空印刷法による前記切り溝への導電性樹脂の充填は、真空（減圧）時と真空（減圧）を開放して大気圧に戻したときの差圧を利用して、溝の内部に存在する気体の体積を減少させることで、前記溝内への前記導電性樹脂の充填率を高める。The conductive resin for forming the shield layer is preferably a mixture of the epoxy resin or other thermosetting resin mixed with conductive metal powder such as Ag powder or Cu powder. The shield layer covering the insulating layer can be formed by a molding method such as a transfer molding method, a potting method, or a vacuum printing method.
Filling the cut groove with the conductive resin by the above vacuum printing method exists inside the groove by utilizing the differential pressure when the vacuum (reduced pressure) and the vacuum (reduced pressure) are released and returned to atmospheric pressure. The filling rate of the conductive resin into the groove is increased by reducing the volume of gas to be generated.

次に、本発明の回路モジュールの製造方法の第２の実施形態について、図２を参照して説明する。図２は本実施形態の回路モジュールの製造方法を説明するための図であり、図２（Ａ）〜図２（Ｆ）は、本実施形態の回路モジュールの製造方法の各ステップを示す部分拡大断面図である。  Next, a second embodiment of the circuit module manufacturing method of the present invention will be described with reference to FIG. FIG. 2 is a diagram for explaining a circuit module manufacturing method according to the present embodiment. FIGS. 2A to 2F are partially enlarged views showing respective steps of the circuit module manufacturing method according to the present embodiment. It is sectional drawing.

本実施形態の回路モジュールの製造方法は、基板２１上に複数の部品２３を配置する工程と、前記各部品２３を被覆する絶縁層２５を形成する工程と、該絶縁層２５を被覆する導電性樹脂からなるシールド層２７を形成する工程と、前記シールド層２７が形成された基板を分割する工程と、を有する回路モジュール２８の製造方法であって、
前記絶縁層２５を被覆するシールド層２７を形成する前に予め深さ方向の基端部２６ｂの幅Ｗ１に比べて先端部２６ａの幅Ｗ２が小さい切り溝２６を前記絶縁層２５から前記基板２１に亘って形成し、少なくとも前記切り溝２６内に充填されるように導電性樹脂を塗布してシールド層２７を形成した後、前記切り溝２６の先端部２６ａに沿って前記先端部２６ａの幅Ｗ２より大きく前記基端部２６ｂの幅Ｗ１より小さい幅Ｗ３で切削して前記基板２１を分割するものである。The circuit module manufacturing method according to the present embodiment includes a step of arranging a plurality of components 23 on a substrate 21, a step of forming an insulating layer 25 covering each of the components 23, and a conductive property covering the insulating layer 25. A method of manufacturing a circuit module 28, comprising: a step of forming a shield layer 27 made of a resin; and a step of dividing a substrate on which the shield layer 27 is formed,
Before forming the shield layer 27 that covers the insulating layer 25, a groove 26 having a width W2 of the distal end portion 26a smaller than the width W1 of the proximal end portion 26b in the depth direction is formed from the insulating layer 25 to the substrate 21 in advance. After forming a shield layer 27 by applying a conductive resin so as to fill at least the cut groove 26, the width of the front end portion 26a along the front end portion 26a of the cut groove 26 is formed. The substrate 21 is divided by cutting with a width W3 larger than W2 and smaller than the width W1 of the base end portion 26b.

また、本実施形態においては、前記切り溝２６が前記基端部２６ｂの幅Ｗ１が前記先端部２６ａの幅Ｗ２よりも広くなっている段付溝として形成されている。  In the present embodiment, the kerf 26 is formed as a stepped groove in which the width W1 of the base end portion 26b is wider than the width W2 of the distal end portion 26a.

また、本実施形態においては、前記段付溝の幅Ｗ１の基端部２６ｂと幅Ｗ２の先端部２６ａとが異なる複数の切削手段（具体的には厚みＷ１のダイシングブレードと厚みＷ２のダイシングブレード）で形成されるものである。  In the present embodiment, a plurality of cutting means (specifically, a dicing blade having a thickness W1 and a dicing blade having a thickness W2) are different in the base end portion 26b having a width W1 and the leading end portion 26a having a width W2. ).

本実施形態が先の第１の実施形態と異なる点は、切り溝２６の幅Ｗ１の基端部２６ｂが基板２１に達するまで切り込まれて、前記絶縁層２５の側面が前記シールド層２７の縁部２７ｂによって完全に被覆されシールド性の優れたものとなっている。また、本実施形態では、上述したように前記段付溝が異なる複数の切削手段で形成される点にあり、その他の構成及び作用効果は先の第１の実施形態と同様であるため説明を省略する。
本実施形態においては、上記第１の実施形態と同様にして図２（Ｂ）に示すように、上記基板２１上に搭載された部品２３及び前記接続手段２４を被覆するように絶縁性樹脂の塗料を塗布し、硬化して絶縁層２５を形成する。
次に、図２（Ｃ）に示すように、上記絶縁層２５から前記基板２１に亘って幅Ｗ１の等幅の切り溝２６を形成する。
次に、図２（Ｄ）に示すように、前記幅Ｗ１の切り溝２６を形成したときに用いた切削ブレードよりも肉薄の切削ブレードを用いて上記切り溝２６の深さ方向の先端部にさらに前記基端部２６ｂの幅Ｗ１よりも小さい幅Ｗ２の切り溝２６ａを形成する。
次に、図２（Ｅ）及び図２（Ｆ）に示すように、上記第１の実施形態と同様にして回路モジュール２８を得る。This embodiment is different from the first embodiment in that the base end portion 26b of the width W1 of the kerf 26 is cut until reaching the substrate 21, and the side surface of the insulating layer 25 is the same as that of the shield layer 27. It is completely covered by the edge 27b and has excellent shielding properties. Further, in the present embodiment, as described above, the stepped groove is formed by a plurality of different cutting means, and the other configurations and functions and effects are the same as those in the first embodiment, so the description will be given. Omitted.
In this embodiment, as in the first embodiment, as shown in FIG. 2B, an insulating resin is coated so as to cover the component 23 and the connection means 24 mounted on the substrate 21. A coating material is applied and cured to form the insulating layer 25.
Next, as shown in FIG. 2C, a kerf 26 having an equal width W <b> 1 is formed from the insulating layer 25 to the substrate 21.
Next, as shown in FIG. 2 (D), a cutting blade that is thinner than the cutting blade used when the kerf 26 having the width W1 is formed is used at the distal end of the kerf 26 in the depth direction. Further, a kerf 26a having a width W2 smaller than the width W1 of the base end portion 26b is formed.
Next, as shown in FIGS. 2E and 2F, a circuit module 28 is obtained in the same manner as in the first embodiment.

次に、本発明の回路モジュールの製造方法の第３の実施形態について、図３を参照して説明する。図３は本実施形態の回路モジュールの製造方法を説明するための図であり、図３（Ａ）〜図３（Ｅ）は、本実施形態の回路モジュールの製造方法の各ステップを示す部分拡大断面図である。  Next, a third embodiment of the circuit module manufacturing method of the present invention will be described with reference to FIG. FIG. 3 is a diagram for explaining a circuit module manufacturing method according to the present embodiment. FIGS. 3A to 3E are partially enlarged views showing respective steps of the circuit module manufacturing method according to the present embodiment. It is sectional drawing.

本実施形態の回路モジュールの製造方法は、基板３１上に複数の部品３３を配置する工程と、前記各部品３３を被覆する絶縁層３５を形成する工程と、該絶縁層３５を被覆する導電性樹脂からなるシールド層３７を形成する工程と、前記シールド層３７が形成された基板を分割する工程と、を有する回路モジュール３８の製造方法であって、
前記絶縁層３５を被覆するシールド層３７を形成する前に予め深さ方向の基端部３６ｂの幅Ｗ１に比べて先端部３６ａの幅Ｗ２が小さい切り溝３６を前記絶縁層３５から前記基板３１に亘って形成し、少なくとも前記切り溝３６内に充填されるように導電性樹脂を塗布してシールド層３７を形成した後、前記切り溝３６の先端部３６ａに沿って前記先端部３６ａの幅Ｗ２より大きく前記基端部３６ｂの幅Ｗ１より小さい幅Ｗ３で切削して前記基板３１を分割するものである。The circuit module manufacturing method of the present embodiment includes a step of arranging a plurality of components 33 on a substrate 31, a step of forming an insulating layer 35 that covers the components 33, and a conductive property that covers the insulating layer 35. A method of manufacturing a circuit module 38, comprising: a step of forming a shield layer 37 made of a resin; and a step of dividing a substrate on which the shield layer 37 is formed,
Before forming the shield layer 37 that covers the insulating layer 35, a groove 36 having a width W2 of the distal end portion 36a smaller than the width W1 of the proximal end portion 36b in the depth direction is formed from the insulating layer 35 to the substrate 31 in advance. After forming a shield layer 37 by applying a conductive resin so that at least the groove 36 is filled, the width of the tip 36a is extended along the tip 36a of the groove 36. The substrate 31 is divided by cutting with a width W3 larger than W2 and smaller than the width W1 of the base end portion 36b.

また、本実施形態においては、前記切り溝３６がテーパ付溝であり、前記切り溝３６が前記基端部３６ｂの幅Ｗ１が前記先端部３６ａの幅Ｗ２よりも広い所謂テーパ付の溝として形成されている。  Further, in the present embodiment, the kerf 36 is a tapered groove, and the kerf 36 is formed as a so-called tapered groove in which the width W1 of the base end part 36b is wider than the width W2 of the distal end part 36a. Has been.

本実施形態が先の第１の実施形態と異なる点は、上述したように前記切り溝３６がテーパ付溝である点にあり、その他の構成及び作用効果は先の第１の実施形態と同様であるため説明を省略する。  The difference between the present embodiment and the first embodiment is that the kerf 36 is a tapered groove as described above, and other configurations and functions and effects are the same as those of the first embodiment. Therefore, the description is omitted.

次に、本発明の回路モジュールの製造方法の第４の実施形態について、図４を参照して説明する。図４は本実施形態の回路モジュールの製造方法を説明するための図であり、図４（Ａ）〜図４（Ｅ）は、本実施形態の回路モジュールの製造方法の各ステップを示す部分拡大断面図である。  Next, a fourth embodiment of the circuit module manufacturing method of the present invention will be described with reference to FIG. FIG. 4 is a diagram for explaining a circuit module manufacturing method according to the present embodiment. FIGS. 4A to 4E are partially enlarged views showing respective steps of the circuit module manufacturing method according to the present embodiment. It is sectional drawing.

本実施形態の回路モジュールの製造方法は、基板４１上に複数の部品４３を配置する工程と、前記各部品４３を被覆する絶縁層４５を形成する工程と、該絶縁層４５を被覆する導電性樹脂からなるシールド層４７を形成する工程と、前記シールド層４７が形成された基板を分割する工程と、を有する回路モジュール４８の製造方法であって、
前記絶縁層３５を被覆するシールド層４７を形成する前に予め深さ方向の基端部４６ｂの幅Ｗ１に比べて先端部４６ａの幅Ｗ２が小さい切り溝４６を前記絶縁層４５に形成し、少なくとも前記切り溝４６内に充填されるように導電性樹脂を塗布してシールド層４７を形成した後、前記切り溝４６の先端部４６ａに沿って前記先端部４６ａの幅Ｗ２より大きく前記基端部４６ｂの幅Ｗ１より小さい幅Ｗ３で切削して前記基板４１を分割するものである。The circuit module manufacturing method of the present embodiment includes a step of disposing a plurality of components 43 on a substrate 41, a step of forming an insulating layer 45 covering each of the components 43, and a conductive property covering the insulating layer 45. A method for manufacturing a circuit module 48, comprising: a step of forming a shield layer 47 made of a resin; and a step of dividing a substrate on which the shield layer 47 is formed,
Before forming the shield layer 47 covering the insulating layer 35, a groove 46 having a width W2 of the distal end portion 46a smaller than the width W1 of the proximal end portion 46b in the depth direction is formed in the insulating layer 45 in advance. After forming a shield layer 47 by applying a conductive resin so that at least the groove 46 is filled, the base end is larger than the width W2 of the tip 46a along the tip 46a of the groove 46. The substrate 41 is divided by cutting with a width W3 smaller than the width W1 of the portion 46b.

本実施形態が先の第１の実施形態と異なる点は、上述したように前記切り溝４６が前記絶縁層４５のみに形成されている点にあり、その他の構成及び作用効果は先の第１の実施形態と同様であるため説明を省略する。  The present embodiment is different from the first embodiment in that the kerf 46 is formed only in the insulating layer 45 as described above, and the other configurations and functions and effects are the same as those of the first embodiment. Since it is the same as that of the embodiment, the description is omitted.

本発明の回路モジュールの製造方法によれば、特に機能の限定はしていないが、種々の電子装置に適用可能である。例えば、高周波パワーアンプ、電子ボリューム、ＤＣ／ＤＣコンバータ、ＦＥＴスイッチ、無線モジュール、その他の小型・薄型の回路モジュールの製造に好適である。  The circuit module manufacturing method of the present invention is not particularly limited in function, but can be applied to various electronic devices. For example, it is suitable for manufacturing high-frequency power amplifiers, electronic volumes, DC / DC converters, FET switches, wireless modules, and other small and thin circuit modules.

本発明の回路モジュールの製造方法の第１の実施形態を説明するための要部拡大断面図である。It is a principal part expanded sectional view for demonstrating 1st Embodiment of the manufacturing method of the circuit module of this invention. 本発明の回路モジュールの製造方法の第２の実施形態を説明するための要部拡大断面図である。It is a principal part expanded sectional view for demonstrating 2nd Embodiment of the manufacturing method of the circuit module of this invention. 本発明の回路モジュールの製造方法の第３の実施形態を説明するための要部拡大断面図である。It is a principal part expanded sectional view for demonstrating 3rd Embodiment of the manufacturing method of the circuit module of this invention. 本発明の回路モジュールの製造方法の第４の実施形態を説明するための要部拡大断面図である。It is a principal part expanded sectional view for demonstrating 4th Embodiment of the manufacturing method of the circuit module of this invention. 背景技術の一例を示す断面図である。It is sectional drawing which shows an example of background art.

符号の説明Explanation of symbols

１１：基板
１２：配線パターン
１３：部品
１４：接続手段
１５：絶縁層
１６：切り溝
１６ａ：先端部
１６ｂ：基端部
１７：シールド層
１７ａ：導電性樹脂
１７ｂ：導電性樹脂
１８：回路モジュール
１９：分割溝
２１：基板
２２：配線パターン
２３：部品
２４：接続手段
２５：絶縁層
２６：切り溝
２６ａ：先端部（第２の切り溝）
２６ｂ：基端部（第１の切り溝）
２７：シールド層
２７ａ：導電性樹脂
２７ｂ：導電性樹脂
２８：回路モジュール
２９：分割溝
３１：基板
３２：配線パターン
３３：部品
３４：接続手段
３５：絶縁層
３６：切り溝
３６ａ：先端部
３６ｂ：基端部
３７：シールド層
３７ａ：導電性樹脂
３７ｂ：導電性樹脂
３８：回路モジュール
３９：分割溝
４１：基板
４２：配線パターン
４３：部品
４４：接続手段
４５：絶縁層
４６：切り溝
４６ａ：先端部
４６ｂ：基端部
４７：シールド層
４７ａ：導電性樹脂
４７ｂ：導電性樹脂
４８：回路モジュール
４９：分割溝
Ｗ１：切り溝の基端部の幅
Ｗ２：切り溝の先端部の幅
Ｗ３：分割時の切削溝の幅11: substrate 12: wiring pattern 13: component 14: connection means 15: insulating layer 16: groove 16a: distal end portion 16b: base end portion 17: shield layer 17a: conductive resin 17b: conductive resin 18: circuit module 19 : Dividing groove 21: Substrate 22: Wiring pattern 23: Component 24: Connection means 25: Insulating layer 26: Cut groove 26 a: Tip (second cut groove)
26b: base end (first kerf)
27: Shield layer 27a: Conductive resin 27b: Conductive resin 28: Circuit module 29: Dividing groove 31: Substrate 32: Wiring pattern 33: Component 34: Connection means 35: Insulating layer 36: Cut groove 36a: Tip 36b: Base end portion 37: Shield layer 37a: Conductive resin 37b: Conductive resin 38: Circuit module 39: Dividing groove 41: Substrate 42: Wiring pattern 43: Component 44: Connection means 45: Insulating layer 46: Cut groove 46a: Tip Portion 46b: Base end portion 47: Shield layer 47a: Conductive resin 47b: Conductive resin 48: Circuit module 49: Dividing groove W1: Width of base end portion of kerf W2: Width of tip end portion of kerf W3: Division Cutting groove width

Claims (4)

基板上に複数の部品を配置する工程と、前記各部品を被覆する絶縁層を形成する工程と、前記絶縁層を被覆する導電性樹脂からなるシールド層を形成する工程と、前記シールド層が形成された基板を分割する工程と、を有する回路モジュールの製造方法において、
前記絶縁層を被覆するシールド層を形成する前に予め深さ方向の基端部の幅Ｗ１に比べ
て先端部の幅Ｗ２が小さい切り溝を少なくとも前記絶縁層に形成し、少なくとも前記切り
溝内に充填されるように導電性樹脂を塗布してシールド層を形成した後、前記切り溝の先
端部に沿って前記先端部の幅Ｗ２より大きく前記基端部の幅Ｗ１より小さい幅Ｗ３で切削
して前記基板を分割することを特徴とする回路モジュールの製造方法。 A step of disposing a plurality of components on a substrate; a step of forming an insulating layer covering each of the components; a step of forming a shield layer made of a conductive resin covering the insulating layer; and forming the shield layer A circuit module manufacturing method comprising the steps of:
Before forming the shield layer covering the insulating layer, a kerf having a width W2 at the distal end smaller than the width W1 at the base end in the depth direction is formed in the insulating layer at least in advance. After forming a shield layer by applying a conductive resin so as to be filled in, cut with a width W3 that is larger than the width W2 of the distal end portion and smaller than the width W1 of the proximal end portion along the distal end portion of the kerf. Then, the method of manufacturing a circuit module is characterized in that the substrate is divided. 前記切り溝が段付溝であることを特徴とする請求項１記載の回路モジュールの製造方法。 The method for manufacturing a circuit module according to claim 1, wherein the groove is a stepped groove. 前記段付溝が異なる複数の切削手段で形成されることを特徴とする請求項２に記載の回路モジュールの製造方法。 The method for manufacturing a circuit module according to claim 2, wherein the stepped groove is formed by a plurality of different cutting means. 前記切り溝がテーパ付溝であることを特徴とする請求項１記載の回路モジュールの製造方法。 The circuit module manufacturing method according to claim 1, wherein the kerf is a tapered groove.
JP2006238242A 2006-08-07 2006-08-07 Circuit module manufacturing method and circuit module Active JP5022652B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006238242A JP5022652B2 (en) 2006-08-07 2006-08-07 Circuit module manufacturing method and circuit module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006238242A JP5022652B2 (en) 2006-08-07 2006-08-07 Circuit module manufacturing method and circuit module

Publications (2)

Publication Number Publication Date
JP2008042152A JP2008042152A (en) 2008-02-21
JP5022652B2 true JP5022652B2 (en) 2012-09-12

Family

ID=39176777

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006238242A Active JP5022652B2 (en) 2006-08-07 2006-08-07 Circuit module manufacturing method and circuit module

Country Status (1)

Country Link
JP (1) JP5022652B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108884358A (en) * 2016-03-29 2018-11-23 拓自达电线株式会社 Conductive coating paint and used the conductive coating paint barrier enclosure body manufacturing method
CN109071993A (en) * 2016-03-29 2018-12-21 拓自达电线株式会社 Conductive coating paint and used the conductive coating paint barrier enclosure body manufacturing method
US10756026B2 (en) 2016-06-08 2020-08-25 Mitsubishi Electric Corporation Semiconductor device and method of manufacturing the same

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101960588A (en) * 2008-03-14 2011-01-26 松下电器产业株式会社 Semiconductor device and semiconductor device fabrication method
WO2009119374A1 (en) * 2008-03-24 2009-10-01 株式会社村田製作所 Method for manufacturing electronic component module
JP2010010441A (en) * 2008-06-27 2010-01-14 Murata Mfg Co Ltd Circuit module and method of manufacturing the same
JP5094622B2 (en) * 2008-08-04 2012-12-12 太陽誘電株式会社 Circuit module and method for manufacturing circuit module
WO2010021262A1 (en) 2008-08-19 2010-02-25 株式会社村田製作所 Circuit module and method for manufacturing same
TW201013881A (en) * 2008-09-10 2010-04-01 Renesas Tech Corp Semiconductor device and method for manufacturing same
JP5416458B2 (en) * 2009-04-02 2014-02-12 タツタ電線株式会社 Method of manufacturing high frequency module having shield and heat dissipation
CN103053021A (en) * 2010-08-18 2013-04-17 株式会社村田制作所 Electronic part and method of manufacturing same
WO2015023312A2 (en) 2013-05-16 2015-02-19 National Institute Of Aerospace Associates Radiation hardened microelectronic chip packaging technology
EP2997595B1 (en) * 2013-05-16 2020-11-18 National Institute Of Aerospace Associates Method of forming a radiation hardened microelectronic chip package
JP5985785B1 (en) 2014-09-30 2016-09-06 タツタ電線株式会社 Conductive paint for shielding electronic component package and method of manufacturing shield package using the same
US9761538B1 (en) * 2016-03-14 2017-09-12 Stmicroelectronics, Inc. Method for making a shielded integrated circuit (IC) package with an electrically conductive polymer layer
TWI770013B (en) * 2016-03-29 2022-07-11 日商拓自達電線股份有限公司 Conductive paint and manufacturing method of shielding package using the same
JP2018009112A (en) 2016-07-14 2018-01-18 タツタ電線株式会社 Conductive coating material and method for producing shield package using the same
EP3650499B1 (en) * 2017-07-07 2023-11-08 Tatsuta Electric Wire & Cable Co., Ltd. Electroconductive resin composition and method for manufacturing shielded package using same
US11912897B2 (en) 2018-04-10 2024-02-27 Tatsuta Electric Wire & Cable Co., Ltd. Electroconductive coating material and method for producing shielded package using said electroconductive coating material
CN111063661A (en) * 2019-12-16 2020-04-24 东莞记忆存储科技有限公司 Flip chip packaging method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4662324B2 (en) * 2002-11-18 2011-03-30 太陽誘電株式会社 Circuit module
WO2006046713A1 (en) * 2004-10-28 2006-05-04 Kyocera Corporation Electronic component module and wireless communication equipment

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108884358A (en) * 2016-03-29 2018-11-23 拓自达电线株式会社 Conductive coating paint and used the conductive coating paint barrier enclosure body manufacturing method
CN109071993A (en) * 2016-03-29 2018-12-21 拓自达电线株式会社 Conductive coating paint and used the conductive coating paint barrier enclosure body manufacturing method
CN109071993B (en) * 2016-03-29 2021-03-30 拓自达电线株式会社 Conductive coating material and method for manufacturing shield package using same
CN108884358B (en) * 2016-03-29 2021-03-30 拓自达电线株式会社 Conductive coating material and method for manufacturing shield package using same
US10756026B2 (en) 2016-06-08 2020-08-25 Mitsubishi Electric Corporation Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
JP2008042152A (en) 2008-02-21

Similar Documents

Publication Publication Date Title
JP5022652B2 (en) Circuit module manufacturing method and circuit module
JP5195903B2 (en) Electronic component module and method for manufacturing the electronic component module
EP1708258B1 (en) Composite ceramic substrate
US9781828B2 (en) Module substrate and method for manufacturing module substrate
EP2320718A1 (en) Circuit module and method for manufacturing same
CN102548253A (en) Manufacturing method of multilayer circuit board
KR20010109149A (en) A surface mount type electronic circuit unit
JP2008288610A (en) Manufacturing method of circuit module
WO2011052480A1 (en) Electronic component device and package substrate
JP4752612B2 (en) Manufacturing method of circuit board with protruding electrode
JP2008177461A (en) Electronic apparatus and manufacturing method thereof
JP2011100649A (en) Substrate with built-in electronic component and electronic module
KR20070111911A (en) Method of manufacturing the ceramics board for electronic element package
JP4388410B2 (en) Multiple wiring board
JP2004288660A (en) Wiring board
JP5447180B2 (en) Ceramic multilayer substrate and electronic module
JP2008187198A (en) Multi-piece wiring substrate and wiring substrate, and manufacturing method therefor
JP2006173287A (en) Electronic part housing ceramic package and its manufacturing method
JP2011176020A (en) Multi-piece wiring board and method of manufacturing the same
US10872853B2 (en) Module
JP7122939B2 (en) Wiring board and manufacturing method thereof
CN109950017B (en) Electronic component and method for manufacturing electronic component
CN110832773B (en) Package for housing electronic component, electronic device, and electronic module
KR100565501B1 (en) Circuit Board Filled With Passive Element and A Manufacturing Method
JP2005150652A (en) Substrate

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090807

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100301

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120201

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120222

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120524

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120618

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 5022652

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150622

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250