JP5019436B2 - 半導体集積回路 - Google Patents
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- 239000000758 substrate Substances 0.000 abstract description 58
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 40
- 229910052710 silicon Inorganic materials 0.000 abstract description 40
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- 239000000126 substance Substances 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
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- Condensed Matter Physics & Semiconductors (AREA)
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- Semiconductor Memories (AREA)
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Description
先ず、本願において開示される発明の代表的な実施の形態について概要を説明する。代表的な実施の形態についての概要説明で括弧を付して参照する図面の参照符号はそれが付された構成要素の概念に含まれるものを例示するに過ぎない。
次に、実施の形態について更に詳述する。
図1には、本発明の実施形態1に係る半導体集積回路の断面構造が例示される。半導体集積回路1は、SOI構造を採用しており、P型のシリコン基板(p−sub)2を下層とし、例えば30nm以下の薄い絶縁膜である埋め込み酸化膜(Buried Oxide、BOX)層(以下、UTBという)3上に形成されたn型MOSトランジスタ(以下、nMOSという)及びp型MOSトランジスタ(以下、pMOSという)等を有している。半導体集積回路1には、シリコン基板2に、メモリ(Memory)4と論理回路(LOGIC)5が混載されている。メモリ4は、複数のメモリセルを有している。1個のメモリセルは、1個の部分空乏(partially-depleted、PD)型のnMOS6で形成されている。ここでは一例として、メモリセルをnMOSで形成するようにしたが、pMOSで形成してもよい。論理回路5は、完全空乏(fully-depleted、FD)型のnMOS7とpMOS8とを有している。部分空乏型のnMOS6は、完全空乏型のnMOS7とpMOS8に比べて、図示のようにUTB3上のシリコン層の厚さが厚く形成されている。また、これらのnMOS6,7とpMOS8は、溝堀型絶縁領域としてのSTI(Shallow Trench Isolation)層9により電気的に分離されている。
図10には、本発明の実施形態2に係る半導体集積回路の断面構造が例示される。以下の各実施形態では、上記半導体集積回路1と同一機能等を有する箇所については同一符号を付し、説明を適宜省略する。半導体集積回路1Aには、シリコン基板2上に、SOI構造を有する部分空乏型(PD)のnMOS6からなるメモリ4と、SOI構造を有する完全空乏型(FD)のnMOS7とpMOS8からなる論理回路5と、バルク構造を有するnMOS51とpMOS52からなる入力保護素子50と、が混載されている。メモリ4と論理回路5については、上記した半導体集積回路1のものと同一構造を有するので、説明を省略する。また、バルク構造とは、ここでは、それぞれのMOSが個別に電気的に分離されていない構造、例えば同一導電型の複数のMOSトランジスタをウエル領域のような共通の半導体領域に形成した構造をいう。バルク構造を有するnMOS51とpMOS52は、SOI構造を有する完全空乏型のnMOS7とpMOS8と比べると、UTB3が配置されていない点が異なり、互いに電気的に分離されていない。このため、バルク構造を有するnMOS51とpMOS52は、CMOSと同じ構造とされ、例えばI/O回路での入力保護素子50を形成できる。また、バルク構造を有するnMOS51とpMOS52は、例えばチャネル形成領域と連続したバックゲート領域14B,22Bを有している。バックゲート領域14Bとシリコン基板2の間には、上記dn領域16,16Aと同一機能を有するdn領域16Bが配置されている。また、dn領域16BとSTI層9の間には、上記n領域18,18Aと同一機能を有するn領域18Bが配置されている。図11には、バルク構造を有するnMOSとpMOSからなる入力保護素子を含む回路構成が例示されている。ここでは、入力保護素子50は、外部入力端子53と、保護対象とされる適宜の保護対象回路54との間に配置されている。入力保護素子50は、ゲートが接地端子VSSに接続されたnMOS51と、ゲートが電源端子VDDに接続されたpMOS52とを有する。pMOS52のバックゲート領域22Bは、電源端子VDDに接続されている。nMOS51のバックゲート領域14Bは、接地端子VSSに接続されている。
図13には、本発明の実施形態3に係る半導体集積回路の断面構造が例示される。半導体集積回路1Bは、図1に例示した上記半導体集積回路1と比べると、UTB3とシリコン基板2の間の構造が異なっている。即ち、半導体集積回路1Bでは、シリコン基板2上には、シリコン基板2よりも機械的又は化学的処理に対して耐性が高い埋め込み酸化膜(以下、TBという)60が積層されている。さらに、このTB60上には、部分空乏型のnMOS6のバックゲート領域61と、完全空乏型のnMOS7のバックゲート領域62と、完全空乏型のpMOS8のバックゲート領域63がそれぞれ積層されている。TB60は、これらのバックゲート領域61,62,63とシリコン基板2とを電気的に分離している。このため、半導体集積回路1Bでは、リーク電流の発生を防止するための図1に例示したnMOS6,7におけるdn領域16等を配置する必要がなく、積層構造を簡素化できる。さらに、半導体集積回路1Bでは、上記dn領域16等を配置しないことで、nMOS6,7とpMOS8をより接近させて配置できるから、サイズを小さくすることもできる。
2 シリコン基板
3 埋め込み酸化膜
4 メモリ
5 論理回路
6 部分空乏型のnMOS
7 完全空乏型のnMOS
8 完全空乏型のpMOS
12 チャネル形成領域
14 バックゲート領域
51 バルク構造を有するnMOS
52 バルク構造を有するpMOS
WL ワード線
BL ビット線
SL ソース線
BG バックゲート端子
Claims (4)
- 第1半導体集積回路と、第2半導体集積回路とを有し、前記第1半導体集積回路と前記第2半導体集積回路が積層された半導体集積回路であって、
前記第1半導体集積回路及び前記第2半導体集積回路の夫々は、
各々が電気的に分離されて第1絶縁膜上に形成されたSOI構造を有する部分空乏型の第1MOSトランジスタと完全空乏型の第2MOSトランジスタとを含み、
前記第1MOSトランジスタの前記第1絶縁膜の下に、前記第1MOSトランジスタのゲート端子とは独立に電圧が印加可能にされた第1半導体領域を有し、
前記第2MOSトランジスタの前記第1絶縁膜の下に、前記第2MOSトランジスタのゲート端子とは独立に電圧が印加可能にされた第2半導体領域を有し、
前記第1半導体領域及び前記第2半導体領域の下に配置された第2絶縁膜を有し、
前記第1MOSトランジスタは、チャネル形成用の第3半導体領域に過剰のキャリアを蓄積した第1の状態と、前記過剰のキャリアが前記第3半導体領域から減少された第2の状態とによって情報を保持する記憶素子を形成し、
前記第2MOSトランジスタは、論理回路を形成する半導体集積回路。 - 前記第1半導体集積回路上の配線を用いた第1巻き線と、前記第2半導体集積回路上の配線を用いた第2巻き線とを有し、
前記第1半導体集積回路と前記第2半導体集積回路は、前記第1巻き線と前記第2巻き線により電磁的に結合される請求項1記載の半導体集積回路。 - 前記第1半導体集積回路上に設けられた第1電極と、前記第2半導体集積回路上に前記第1電極に対向して設けられた第2電極とを有し、
前記第1半導体集積回路と前記第2半導体集積回路は、前記第1電極と前記第2電極により容量結合される請求項1記載の半導体集積回路。 - 前記第1半導体集積回路上に設けられた発光素子と、前記第2半導体集積回路上に設けられた受光素子とを有し、
前記第1半導体集積回路と前記第2半導体集積回路は、前記発光素子と前記受光素子を用いて光通信を行う請求項1記載の半導体集積回路。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2007041554A JP5019436B2 (ja) | 2007-02-22 | 2007-02-22 | 半導体集積回路 |
US11/960,680 US20080203403A1 (en) | 2007-02-22 | 2007-12-19 | Semiconductor integrated circuit |
US13/086,377 US20110188329A1 (en) | 2007-02-22 | 2011-04-13 | Semiconductor integrated circuit |
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JP2007041554A JP5019436B2 (ja) | 2007-02-22 | 2007-02-22 | 半導体集積回路 |
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JP2008205322A JP2008205322A (ja) | 2008-09-04 |
JP5019436B2 true JP5019436B2 (ja) | 2012-09-05 |
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CN101680018B (zh) * | 2007-01-10 | 2017-03-15 | 海莫希尔有限责任公司 | 体外血液动力学的内皮/平滑肌细胞共培养模型在鉴定血管疾病的新型治疗靶标中的应用 |
US8278167B2 (en) * | 2008-12-18 | 2012-10-02 | Micron Technology, Inc. | Method and structure for integrating capacitor-less memory cell with logic |
FR2944641B1 (fr) * | 2009-04-15 | 2011-04-29 | Centre Nat Rech Scient | Point memoire ram a un transistor. |
EP2320454A1 (en) * | 2009-11-05 | 2011-05-11 | S.O.I.Tec Silicon on Insulator Technologies | Substrate holder and clipping device |
JP2011108773A (ja) * | 2009-11-16 | 2011-06-02 | Seiko Epson Corp | 半導体装置 |
FR2953641B1 (fr) * | 2009-12-08 | 2012-02-10 | S O I Tec Silicon On Insulator Tech | Circuit de transistors homogenes sur seoi avec grille de controle arriere enterree sous la couche isolante |
FR2953636B1 (fr) * | 2009-12-08 | 2012-02-10 | Soitec Silicon On Insulator | Procede de commande d'une cellule memoire dram sur seoi disposant d'une seconde grille de controle enterree sous la couche isolante |
FR2957193B1 (fr) | 2010-03-03 | 2012-04-20 | Soitec Silicon On Insulator | Cellule a chemin de donnees sur substrat seoi avec grille de controle arriere enterree sous la couche isolante |
FR2953643B1 (fr) * | 2009-12-08 | 2012-07-27 | Soitec Silicon On Insulator | Cellule memoire flash sur seoi disposant d'une seconde grille de controle enterree sous la couche isolante |
US8508289B2 (en) * | 2009-12-08 | 2013-08-13 | Soitec | Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer |
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FR2955204B1 (fr) * | 2010-01-14 | 2012-07-20 | Soitec Silicon On Insulator | Cellule memoire dram disposant d'un injecteur bipolaire vertical |
FR2955195B1 (fr) * | 2010-01-14 | 2012-03-09 | Soitec Silicon On Insulator | Dispositif de comparaison de donnees dans une memoire adressable par contenu sur seoi |
FR2955203B1 (fr) | 2010-01-14 | 2012-03-23 | Soitec Silicon On Insulator | Cellule memoire dont le canal traverse une couche dielectrique enterree |
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FR2957186B1 (fr) * | 2010-03-08 | 2012-09-28 | Soitec Silicon On Insulator | Cellule memoire de type sram |
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JPH04246863A (ja) * | 1991-02-01 | 1992-09-02 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JPH08195443A (ja) * | 1995-01-18 | 1996-07-30 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US6090636A (en) * | 1998-02-26 | 2000-07-18 | Micron Technology, Inc. | Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same |
JP3456913B2 (ja) * | 1998-12-25 | 2003-10-14 | 株式会社東芝 | 半導体装置 |
US6621725B2 (en) * | 2000-08-17 | 2003-09-16 | Kabushiki Kaisha Toshiba | Semiconductor memory device with floating storage bulk region and method of manufacturing the same |
US6414355B1 (en) * | 2001-01-26 | 2002-07-02 | Advanced Micro Devices, Inc. | Silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness |
JP2003031693A (ja) * | 2001-07-19 | 2003-01-31 | Toshiba Corp | 半導体メモリ装置 |
JP2003124345A (ja) * | 2001-10-11 | 2003-04-25 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
EP1357603A3 (en) * | 2002-04-18 | 2004-01-14 | Innovative Silicon SA | Semiconductor device |
US7304827B2 (en) * | 2003-05-02 | 2007-12-04 | Zi-Ping Chen | ESD protection circuits for mixed-voltage buffers |
JP4046337B2 (ja) * | 2003-08-18 | 2008-02-13 | 株式会社東芝 | 半導体装置の製造方法 |
JP4664631B2 (ja) * | 2004-08-05 | 2011-04-06 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP4274113B2 (ja) * | 2004-12-07 | 2009-06-03 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP4800700B2 (ja) * | 2005-08-01 | 2011-10-26 | ルネサスエレクトロニクス株式会社 | 半導体装置およびそれを用いた半導体集積回路 |
JP2006080549A (ja) * | 2005-10-18 | 2006-03-23 | Toshiba Corp | 半導体記憶装置及び半導体集積回路 |
US7820519B2 (en) * | 2006-11-03 | 2010-10-26 | Freescale Semiconductor, Inc. | Process of forming an electronic device including a conductive structure extending through a buried insulating layer |
-
2007
- 2007-02-22 JP JP2007041554A patent/JP5019436B2/ja not_active Expired - Fee Related
- 2007-12-19 US US11/960,680 patent/US20080203403A1/en not_active Abandoned
-
2011
- 2011-04-13 US US13/086,377 patent/US20110188329A1/en not_active Abandoned
Also Published As
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JP2008205322A (ja) | 2008-09-04 |
US20110188329A1 (en) | 2011-08-04 |
US20080203403A1 (en) | 2008-08-28 |
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