JP5014380B2 - 多層基板および半導体装置 - Google Patents
多層基板および半導体装置 Download PDFInfo
- Publication number
- JP5014380B2 JP5014380B2 JP2009127293A JP2009127293A JP5014380B2 JP 5014380 B2 JP5014380 B2 JP 5014380B2 JP 2009127293 A JP2009127293 A JP 2009127293A JP 2009127293 A JP2009127293 A JP 2009127293A JP 5014380 B2 JP5014380 B2 JP 5014380B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- conductor layer
- ground
- conductors
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
2a〜2j・・・絶縁層
3・・・半導体素子
7・・・電源導体層
7a・・・電源導体層非形成部
8・・・接地導体層
9・・・信号導体層
10・・・電源貫通導体
11・・・接地貫通導体
12・・・信号貫通導体
Claims (4)
- 複数の絶縁層および該絶縁層間に形成された電源導体層ならびに該電源導体層が形成された前記絶縁層間と異なる前記絶縁層間に形成された接地導体層を有するとともに、下面の外周部に複数の信号端子ならびに中央部に複数の電源端子および複数の接地端子を有する半導体素子を搭載する搭載部を上面に有する基体と、該基体の前記搭載部の中央部から前記基体の下面側に向かって形成された、前記電源導体層に電気的に接続された複数の電源貫通導体および前記接地導体層に電気的に接続された複数の接地貫通導体と、前記基体の前記搭載部の外周部から前記基体の下面側に向かって形成された複数の信号貫通導体とを備えており、複数の前記電源貫通導体および複数の前記接地貫通導体は、平面視で前記搭載部の中心から外周側に向かって交互に環状に配列されており、前記電源導体層は、平面視で環状に配列された複数の前記接地貫通導体が貫通する部位を含む環状の電源導体層非形成部を有しており、前記接地導体層は、平面視で環状に配列された複数の前記電源貫通導体が貫通する部位を含む環状の接地導体層非形成部を有していることを特徴とする多層基板。
- 複数の前記電源貫通導体は、複数種の電源電位ごとの群を成しており、該群ごとにその群間に複数の前記接地貫通導体を挟んで、平面視で前記搭載部の中心から外周側に向かって環状に配列されていることを特徴とする請求項1記載の多層基板。
- 平面視で前記搭載部の中央部の最外周に複数の前記接地貫通導体が環状に配列されていることを特徴とする請求項1または請求項2に記載の多層基板。
- 請求項1乃至請求項3のいずれかに記載の多層基板と、該多層基板の前記搭載部に搭載された半導体素子とを備えていることを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009127293A JP5014380B2 (ja) | 2009-05-27 | 2009-05-27 | 多層基板および半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009127293A JP5014380B2 (ja) | 2009-05-27 | 2009-05-27 | 多層基板および半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010278101A JP2010278101A (ja) | 2010-12-09 |
JP5014380B2 true JP5014380B2 (ja) | 2012-08-29 |
Family
ID=43424822
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009127293A Expired - Fee Related JP5014380B2 (ja) | 2009-05-27 | 2009-05-27 | 多層基板および半導体装置 |
Country Status (1)
Country | Link |
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JP (1) | JP5014380B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106054093A (zh) * | 2016-05-25 | 2016-10-26 | 国网辽宁省电力有限公司电力科学研究院 | 一种接地装置测试仪抗工频干扰能力评估装置 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5732357B2 (ja) * | 2011-09-09 | 2015-06-10 | 新光電気工業株式会社 | 配線基板、及び半導体パッケージ |
WO2016103359A1 (ja) * | 2014-12-24 | 2016-06-30 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0637461A (ja) * | 1992-07-13 | 1994-02-10 | Ibiden Co Ltd | 多層プリント配線板 |
JP3441199B2 (ja) * | 1994-11-22 | 2003-08-25 | 京セラ株式会社 | 半導体素子収納用パッケージ |
JP4041253B2 (ja) * | 1999-11-19 | 2008-01-30 | 京セラ株式会社 | 集積回路素子搭載用基板および集積回路装置 |
JP2001203470A (ja) * | 2000-01-21 | 2001-07-27 | Toshiba Corp | 配線基板、半導体パッケージ、および半導体装置 |
JP3796104B2 (ja) * | 2000-08-01 | 2006-07-12 | 京セラ株式会社 | 多層配線基板 |
JP2003188305A (ja) * | 2001-12-14 | 2003-07-04 | Ngk Spark Plug Co Ltd | 配線基板 |
-
2009
- 2009-05-27 JP JP2009127293A patent/JP5014380B2/ja not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106054093A (zh) * | 2016-05-25 | 2016-10-26 | 国网辽宁省电力有限公司电力科学研究院 | 一种接地装置测试仪抗工频干扰能力评估装置 |
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Publication number | Publication date |
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JP2010278101A (ja) | 2010-12-09 |
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