JP5011562B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP5011562B2 JP5011562B2 JP2007215673A JP2007215673A JP5011562B2 JP 5011562 B2 JP5011562 B2 JP 5011562B2 JP 2007215673 A JP2007215673 A JP 2007215673A JP 2007215673 A JP2007215673 A JP 2007215673A JP 5011562 B2 JP5011562 B2 JP 5011562B2
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- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
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- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
- H01L2224/84815—Reflow soldering
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- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
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Description
図1は、本発明の実施の形態1における半導体装置の構成を概略的に示す概略断面図である。図1に示すように、本実施の形態の半導体装置100aは、半導体素子110と、電極端子120と、電極端子130と、絶縁基板140と、はんだ151〜156と、ヒートシンク160と、封止部材170と、ケース180とを主に備えている。
図13は、本発明の実施の形態2の半導体装置において電極端子と半導体素子とが接合されている領域近傍の構成を概略的に示す拡大断面図である。図14は、本発明の実施の形態2における半導体装置の電極端子の構成を概略的に示す斜視図である。図13および図14を参照して、本実施の形態における半導体装置100dは、基本的には実施の形態1の半導体装置100aと同様の構成を備えているが、電極端子120が対向する側面123、124のうちの一方の側面123に形成された凹部122と先端面121との距離L123と、他方の側面124に形成された凹部122と先端面121との距離L124とが同等である点においてのみ異なる。
図33は、本発明の実施の形態3の半導体装置において電極端子と半導体素子とが接合されている領域近傍の構成を概略的に示す断面図である。図34は、本発明の実施の形態3における半導体装置の電極端子の構成を概略的に示す斜視図である。図33および図34に示すように、本実施の形態における100nは、基本的には実施の形態1の半導体装置100aと同様の構成を備えているが、延伸部分120aは、延伸部分120aを貫通する貫通孔127を有し、貫通孔127に反対側に向いた面127aが形成されている点においてのみ異なる。
図35は、本発明の実施の形態4の半導体装置において電極端子と半導体装置とが接合されている領域近傍の構成を概略的に示す斜視図である。図36は、本発明の実施の形態4における電極端子の構成を概略的に示し、(A)は正面図であり、(B)は(A)において矢印Bから見たときの側面図であり、(C)は斜視図である。図35および図36(A)〜(C)に示すように、本実施の形態における半導体装置100oは、基本的には実施の形態1の半導体装置100aと同様の構成を備えているが、延伸方向に沿って伸びる面としての側面123が波打つように湾曲している点においてのみ異なる。
Claims (8)
- 半導体素子と、
延伸方向に沿って伸びる延伸部分を有し、かつ前記延伸部分の前記延伸方向の先端面を前記半導体素子の表面に対して突き合わせた状態で前記半導体素子と接合される電極端子と、
前記半導体素子と前記電極端子とを接合するはんだとを備え、
前記電極端子は、前記電極端子の前記はんだで接合される領域に、前記延伸方向に交差する面であって、前記先端面と反対側に向いた面を有する、半導体装置。 - 前記電極端子の前記先端面における幅は、前記延伸部分の前記先端面以外の他の部分の最大の幅以下である、請求項1に記載の半導体装置。
- 前記延伸部分の側面に凹部が形成され、
前記凹部に前記反対側に向いた面が形成されている、請求項1または2に記載の半導体装置。 - 前記延伸部分は、互いに対向する2つの側面を有し、
前記2つの側面の各々に凹部が形成され、
前記凹部に前記反対側に向いた面が形成されている、請求項1または2に記載の半導体装置。 - 前記2つの側面のうちの一方の側面に形成された凹部と前記先端面との距離は、前記2つの側面のうちの他方の側面に形成された凹部と前記先端面との距離と異なっている、請求項4に記載の半導体装置。
- 前記凹部は、矩形状および半円状のいずれか一方の形状を有している、請求項3〜5のいずれかに記載の半導体装置。
- 前記延伸部分は、前記延伸部分を貫通する貫通孔を有し、
前記貫通孔に前記反対側に向いた面が形成されている、請求項1または2に記載の半導体装置。 - 半導体素子を準備する工程と、
延伸方向に沿って伸びる延伸部分と、前記延伸部分の前記延伸方向の先端面と、前記延伸方向に交差する面であって前記先端面と反対側に向いた面とを有する電極端子を準備する工程と、
前記半導体素子の表面と前記電極端子の前記先端面とを突き合わすように配置した状態で前記半導体素子と前記電極端子とをはんだを用いて接合する工程とを備え、
前記接合する工程では、前記反対側に向いた面に前記はんだが付着するように接合する、半導体装置の製造方法。
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JP2007215673A JP5011562B2 (ja) | 2007-08-22 | 2007-08-22 | 半導体装置およびその製造方法 |
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JP2007215673A JP5011562B2 (ja) | 2007-08-22 | 2007-08-22 | 半導体装置およびその製造方法 |
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JP2009049272A JP2009049272A (ja) | 2009-03-05 |
JP5011562B2 true JP5011562B2 (ja) | 2012-08-29 |
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JP2007215673A Expired - Fee Related JP5011562B2 (ja) | 2007-08-22 | 2007-08-22 | 半導体装置およびその製造方法 |
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Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5589409B2 (ja) * | 2010-01-29 | 2014-09-17 | オムロン株式会社 | 実装部品、電子機器および実装方法 |
JP2014123638A (ja) * | 2012-12-21 | 2014-07-03 | Murata Mfg Co Ltd | 部品モジュール |
JP6239840B2 (ja) * | 2013-03-27 | 2017-11-29 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
JP6659289B2 (ja) * | 2015-09-28 | 2020-03-04 | 京セラ株式会社 | ヒータ |
JP6643093B2 (ja) * | 2016-01-15 | 2020-02-12 | 京セラ株式会社 | ヒータ |
JP6256639B2 (ja) * | 2017-01-31 | 2018-01-10 | 株式会社村田製作所 | 部品モジュール |
WO2019082344A1 (ja) * | 2017-10-26 | 2019-05-02 | 新電元工業株式会社 | 半導体装置の製造方法 |
JP6808849B2 (ja) * | 2017-10-26 | 2021-01-06 | 新電元工業株式会社 | 半導体装置 |
WO2019082343A1 (ja) * | 2017-10-26 | 2019-05-02 | 新電元工業株式会社 | 半導体装置 |
EP4002447A1 (en) * | 2020-11-18 | 2022-05-25 | Infineon Technologies Austria AG | Contact clip for semiconductor device package |
Family Cites Families (7)
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JPS5877060U (ja) * | 1981-11-18 | 1983-05-24 | 日本電気株式会社 | 電子部品 |
JPS61125058A (ja) * | 1984-11-22 | 1986-06-12 | Hitachi Ltd | 半導体装置 |
JP2560869B2 (ja) * | 1989-04-27 | 1996-12-04 | 富士電機株式会社 | 二端子面実装形半導体装置 |
JPH05315517A (ja) * | 1992-05-12 | 1993-11-26 | Nec Corp | 半導体装置 |
JPH07130937A (ja) * | 1993-11-05 | 1995-05-19 | Hitachi Ltd | 表面実装型半導体装置およびその製造に用いるリードフレーム |
JP2002334964A (ja) * | 2001-05-08 | 2002-11-22 | Hitachi Ltd | 半導体装置 |
JP2006066716A (ja) * | 2004-08-27 | 2006-03-09 | Fuji Electric Holdings Co Ltd | 半導体装置 |
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