JP4993248B2 - リセスチャネル及び非対称接合構造を有する半導体素子の製造方法 - Google Patents
リセスチャネル及び非対称接合構造を有する半導体素子の製造方法 Download PDFInfo
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- JP4993248B2 JP4993248B2 JP2005194721A JP2005194721A JP4993248B2 JP 4993248 B2 JP4993248 B2 JP 4993248B2 JP 2005194721 A JP2005194721 A JP 2005194721A JP 2005194721 A JP2005194721 A JP 2005194721A JP 4993248 B2 JP4993248 B2 JP 4993248B2
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- 239000004065 semiconductor Substances 0.000 title claims description 74
- 238000004519 manufacturing process Methods 0.000 title claims description 31
- 239000012535 impurity Substances 0.000 claims description 63
- 239000000758 substrate Substances 0.000 claims description 39
- 238000000034 method Methods 0.000 claims description 31
- 150000002500 ions Chemical class 0.000 claims description 30
- 238000005468 ion implantation Methods 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 8
- 238000002955 isolation Methods 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 229910021332 silicide Inorganic materials 0.000 description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 7
- 238000003860 storage Methods 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- -1 B ions Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
Claims (9)
- ソース領域が形成される第1領域、ドレイン領域が形成される第2領域およびそれらの間のチャネル領域が形成される第3領域を有する半導体基板の前記第2領域と、前記第3領域の前記第2領域に隣接する一部領域と、にしきい電圧調節のためのイオン注入を行って不純物領域を形成する段階と;
前記不純物領域が形成された前記半導体基板の前記第3領域をエッチングしてリセスチャネル用トレンチおよび前記チャネル領域を形成する段階と;
前記リセスチャネル用トレンチが形成された半導体基板にゲートスタックを形成する段階と;
前記ゲートスタックが形成された半導体基板にイオン注入工程を行って前記ソース領域及び前記ドレイン領域を形成する段階と;
を含み、前記リセスチャネル用トレンチを形成する段階は、前記リセスチャネル用トレンチの深さを前記不純物領域よりも深くすることを特徴とするリセスチャネル及び非対称接合構造を有する半導体素子の製造方法。 - 前記不純物領域は、前記半導体基板の表面から50〜2500Åの深さを有して形成されることを特徴とする請求項1記載のリセスチャネル及び非対称接合構造を有する半導体素子の製造方法。
- 前記リセスチャネル用トレンチは、前記半導体基板の表面から50〜2500Åの深さを有して形成されることを特徴とする請求項1記載のリセスチャネル及び非対称接合構造を有する半導体素子の製造方法。
- 前記不純物領域を形成する段階は、p型不純物イオンを注入して行うことを特徴とする請求項1記載のリセスチャネル及び非対称接合構造を有する半導体素子の製造方法。
- 前記p型不純物イオンは、Bイオン、BF2イオンまたはIイオンを含むことを特徴とする請求項4記載のリセスチャネル及び非対称接合構造を有する半導体素子の製造方法。
- 前記不純物領域を形成するためのマスク膜パターンの幅は、フィーチャーサイズの1〜3倍の範囲になることを特徴とする請求項1記載のリセスチャネル及び非対称接合構造を有する半導体素子の製造方法。
- 前記不純物領域を形成するためのマスク膜パターンの幅は、ゲート形成のためのゲートマスク膜パターンの幅の1〜3倍の範囲になることを特徴とする請求項1記載のリセスチャネル及び非対称接合構造を有する半導体素子の製造方法。
- 前記不純物領域を形成した後、n型不純物イオンを前記不純物領域の表面に配置されるように注入する段階をさらに含むことを特徴とする請求項1記載のリセスチャネル及び非対称接合構造を有する半導体素子の製造方法。
- 前記n型不純物イオンは、PイオンまたはAsイオンを含むことを特徴とする請求項8記載のリセスチャネル及び非対称接合構造を有する半導体素子の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050020926A KR100712989B1 (ko) | 2005-03-14 | 2005-03-14 | 리세스 채널 및 비대칭접합 구조를 갖는 반도체 소자의제조방법 |
KR10-2005-0020926 | 2005-03-14 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006261627A JP2006261627A (ja) | 2006-09-28 |
JP4993248B2 true JP4993248B2 (ja) | 2012-08-08 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2005194721A Expired - Fee Related JP4993248B2 (ja) | 2005-03-14 | 2005-07-04 | リセスチャネル及び非対称接合構造を有する半導体素子の製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7381612B2 (ja) |
JP (1) | JP4993248B2 (ja) |
KR (1) | KR100712989B1 (ja) |
CN (1) | CN100463146C (ja) |
TW (1) | TWI279845B (ja) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100675889B1 (ko) * | 2005-04-26 | 2007-02-02 | 주식회사 하이닉스반도체 | 리세스 채널을 가지는 반도체 소자 및 그 제조방법 |
JP4773169B2 (ja) * | 2005-09-14 | 2011-09-14 | エルピーダメモリ株式会社 | 半導体装置の製造方法 |
KR100843712B1 (ko) * | 2007-02-26 | 2008-07-04 | 삼성전자주식회사 | 활성 영역 내 채널 불순물 확산 영역과 자기 정렬하는데적합한 게이트 패턴을 가지는 트랜지스터들 및 그의형성방법들 |
JP5608313B2 (ja) * | 2007-03-16 | 2014-10-15 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置の製造方法 |
TWI349340B (en) * | 2007-09-03 | 2011-09-21 | Nanya Technology Corp | Method for manufacturing non-volatile memory |
KR100920045B1 (ko) * | 2007-12-20 | 2009-10-07 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 제조방법 |
JP2010141107A (ja) * | 2008-12-11 | 2010-06-24 | Elpida Memory Inc | 半導体装置及びその製造方法 |
CN101924075B (zh) * | 2009-06-09 | 2012-06-27 | 中芯国际集成电路制造(上海)有限公司 | 快闪存储器制造方法 |
KR101096226B1 (ko) * | 2010-10-28 | 2011-12-22 | 주식회사 하이닉스반도체 | 매립게이트를 구비한 반도체장치 제조 방법 |
JP2012204689A (ja) * | 2011-03-25 | 2012-10-22 | Toshiba Corp | 半導体装置及びその製造方法 |
CN104637822B (zh) * | 2015-01-23 | 2018-05-11 | 无锡同方微电子有限公司 | 一种双沟槽场效应管及其制备方法 |
CN110246841B (zh) | 2018-03-08 | 2021-03-23 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
CN108735608B (zh) * | 2018-05-30 | 2023-10-24 | 长鑫存储技术有限公司 | 半导体器件及其制作方法 |
CN118119126A (zh) * | 2022-07-26 | 2024-05-31 | Oppo广东移动通信有限公司 | 基板、壳体组件和电子设备 |
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-
2005
- 2005-03-14 KR KR1020050020926A patent/KR100712989B1/ko not_active IP Right Cessation
- 2005-05-09 TW TW094114906A patent/TWI279845B/zh not_active IP Right Cessation
- 2005-06-20 CN CNB2005100783816A patent/CN100463146C/zh not_active Expired - Fee Related
- 2005-06-24 US US11/166,482 patent/US7381612B2/en not_active Expired - Fee Related
- 2005-07-04 JP JP2005194721A patent/JP4993248B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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TW200633005A (en) | 2006-09-16 |
US20060205162A1 (en) | 2006-09-14 |
CN100463146C (zh) | 2009-02-18 |
CN1835209A (zh) | 2006-09-20 |
TWI279845B (en) | 2007-04-21 |
US7381612B2 (en) | 2008-06-03 |
KR20060099605A (ko) | 2006-09-20 |
JP2006261627A (ja) | 2006-09-28 |
KR100712989B1 (ko) | 2007-05-02 |
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