JP4968726B2 - インターフレームのための高速モード決定符号化 - Google Patents
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Description
本出願は、2003年6月25日付で出願され、「インターフレームのための高速モード決定のための方法および装置(METHOD AND APPARATUS FOR FAST MODE DECISION FOR INTERFRAMES)」と題された米国仮特許出願第60/482,331号(事件整理番号PU030164)の利益を主張するものであり、その開示内容全体を本明細書中に盛り込むものとする。
従来技術のこれらのおよび他の欠点、不都合は、インターフレーム高速モード決定符号化のための装置および方法により解決される。
(等式2)
QPおよびλMODEが与えられ、MODEは可変である。SSDは、当初の信号および再構築された信号との間の自乗差の和(Sum of Square Differences)である。R(s,c,MODE)は、マクロブロック・ヘッダ、動き係数、および全てのDCT係数を含むMODEの選択に関連するビットの数である。MODEは、使用する可能性のあるマクロブロック・モードのセット(集合)の中のモードを示す。
INTRA4×4は次のモードを含んでいる。
INTRA16×16は次のモードを含んでいる。
Claims (4)
- H.264/MPEG AVCビデオ符号化においてインター符号化されたフレームの現在のマクロブロック・モードを選択する方法であって、前記マクロブロック・モードは、
であり、前記INTRA4×4モードは、
であり、前記INTRA16×16は、
のモードを含んでおり、
前記方法は、
所与の量子化パラメーターQPで、SKIP及び16×16モードについて、前記SKIPモードの値Jが前記16×16モードのJよりも小さく、かつ、前記16×16モードに残差が無いかどうかをチェックするステップであって、Jは、当初の信号と再構築された信号との間の自乗差の和と、ラグランジュ乗数λMODEとマクロブロック・ヘッダ、動き係数及び全てのDCT係数のビットを含む現在のモードに関連して要求されるビットの数Rとの積と、の和値である、当該ステップと、
前記チェックの結果が偽である場合は、8×8モードのチェックを続けるステップと、
前記チェックの結果が真である場合は、前記SKIPモードが前記16×16モードと同じ動き情報を有するかどうかをチェックするステップであって、
当該チェックの結果が偽である場合は、8×8モードの前記チェックを続け、
当該チェックの結果が真である場合は、イントラ・モードのチェックを続ける、当該ステップと、
前記8×8モードをチェックし、かつ、前記8×8モードが前記16×16モードと同じ動き情報を有するかどうかを判定するステップと、
当該判定の結果が真である場合は4×4モードのチェックを続け、当該判定の結果が偽である場合は16×8モード及び8×16モードをチェックし、これらのモードが前記16×16モードと同じ動き情報を有する場合は4×4モードのチェックを続けるステップと、
前記4×4モードをチェックし、かつ、前記4×4モードが前記8×8モードと同じ動き情報を有するかどうかを判定するステップと、
当該判定の結果が真である場合はイントラ・モードのチェックを続け、当該判定の結果が偽である場合は8×4モード及び4×8モードをチェックし、これらのモードが前記8×8モードと同じ動き情報を有する場合はイントラ・モードのチェックを続けるステップと、を有し、
各マクロブロック・モードに符号化コストの閾値が存在しており、現在のマクロブロックについて現在チェックされているモードの符号化コストに関して対応する閾値が満たされている場合には、現在のマクロブロックについて現在チェックされている当該モードが選択され、残りのチェックされていないモードのチェックが中止される、前記方法。 - 前記符号化コストの閾値T(mode)が、下記のように計算され、
T(mode) = α(mode)*Tn + β(mode)
Tn = MAX(COSTlowbound, MIN(COSThighbound, COST1, COST2, ..., COSTn)),
上記式において、α(mode)およびβ(mode)は1つのモードのためのスカラーであり、COSTiはi番目の隣接ブロックの符号化コストを示す、請求項1に記載の方法。 - 空間的または/および時間的に隣接しているマクロブロック及びブロック・パーティション情報は、チェックが必要なモードを決定することに使用される、請求項1に記載の方法。
- 特定のモードを調べた後、空間的または/および時間的に隣接しているマクロブロックが現在のマクロブロックの動き情報と特定の関係を有する場合にモード選択処理が終了する、請求項1に記載の方法。
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US48233103P | 2003-06-25 | 2003-06-25 | |
US60/482,331 | 2003-06-25 | ||
PCT/US2004/019527 WO2005004491A1 (en) | 2003-06-25 | 2004-06-17 | Fast mode-decision encoding for interframes |
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JP2007524279A JP2007524279A (ja) | 2007-08-23 |
JP4968726B2 true JP4968726B2 (ja) | 2012-07-04 |
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US (1) | US9210441B2 (ja) |
EP (1) | EP1639827B1 (ja) |
JP (1) | JP4968726B2 (ja) |
CN (1) | CN100594730C (ja) |
BR (1) | BRPI0411765A (ja) |
DE (1) | DE602004026580D1 (ja) |
ES (1) | ES2343410T3 (ja) |
MX (1) | MXPA05014211A (ja) |
MY (1) | MY143420A (ja) |
WO (1) | WO2005004491A1 (ja) |
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US20060193385A1 (en) | 2006-08-31 |
CN100594730C (zh) | 2010-03-17 |
JP2007524279A (ja) | 2007-08-23 |
WO2005004491A1 (en) | 2005-01-13 |
ES2343410T3 (es) | 2010-07-30 |
DE602004026580D1 (de) | 2010-05-27 |
KR20060027813A (ko) | 2006-03-28 |
BRPI0411765A (pt) | 2006-08-08 |
EP1639827B1 (en) | 2010-04-14 |
CN1810037A (zh) | 2006-07-26 |
MY143420A (en) | 2011-05-31 |
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