JP4953091B2 - Capacitor chip and manufacturing method thereof - Google Patents
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この出願は、米国法典第３５巻第１１１条（ｂ）項の規定に従い、２００５年１２月２１日に提出した米国仮出願第６０／７５２，０４５の出願日の利益を同第１１９条（ｅ）項（１）により主張する同第１１１条（ａ）項の規定に基づく出願である。 This application is subject to the benefit of the filing date of US Provisional Application No. 60 / 752,045 filed on December 21, 2005, pursuant to the provisions of 35 USC 35, 111 (b). ) Is an application based on the provisions of Article 111 (a) claimed in paragraph (1).
本発明はコンデンサチップ及びその製造方法、特に積層型固体電解コンデンサ及びその製造方法に関する。 The present invention relates to a capacitor chip and a manufacturing method thereof, and more particularly to a multilayer solid electrolytic capacitor and a manufacturing method thereof.
近年、電気機器のデジタル化、パーソナルコンピュータ等の電子機器の小型化・高速化に伴い、小型で大容量のコンデンサ、高周波領域において低インピーダンスのコンデンサが要求されている。最近では、電子伝導性を有する導電性重合体を固体電解質として用いた固体電解コンデンサが提案されている。特に、より大きな容量を有する製品が求められており、複数のコンデンサ素子を積層し、封止することからなる積層型固体電解コンデンサとして製造されている。 In recent years, with the digitization of electrical equipment and the downsizing and speeding up of electronic equipment such as personal computers, small and large-capacitance capacitors and low-impedance capacitors are required in the high-frequency region. Recently, a solid electrolytic capacitor using a conductive polymer having electronic conductivity as a solid electrolyte has been proposed. In particular, a product having a larger capacity is demanded, and is manufactured as a multilayer solid electrolytic capacitor including a plurality of capacitor elements stacked and sealed.
例えば、特開2002-319522号公報（特許文献１）（EP 1160809明細書）には、陽極体の電気的一体化に要する空間を小さくすることで小型大容量化を図り、なおかつ、特に陽極体同士の電気的接続に関して、低抵抗で信頼性の高い接続状態を得ることが可能な固体電解コンデンサについて記載されている。 For example, Japanese Patent Application Laid-Open No. 2002-319522 (Patent Document 1) (EP 1160809 Specification) discloses a reduction in the space required for electrical integration of the anode body to reduce the size and capacity, and in particular, the anode body. It describes a solid electrolytic capacitor that can obtain a reliable connection state with low resistance with respect to electrical connection between them.
図１は従来の積層型固体電解コンデンサの構造を表す断面図である。
一般に、エッチング処理された比表面積の大きな金属箔や薄板からなる陽極基体（１）表面に誘電体の酸化皮膜層（２）を形成し、通常はさらにマスキング層（５）を設けた後、前記酸化皮膜層（２）の外側に陰極部として機能する固体の半導体層（以下、固体電解質という。）や導電ペーストなどの導電体層（３）を順次形成してコンデンサ素子（６）を作製する。こうして形成した複数個のコンデンサ素子（６）を方向を揃えて積層し、適宜、導体層（４）を設け、さらに電極リード部（７，８）を付加し、全体を樹脂（９）で封止して積層型固体電解コンデンサとする。FIG. 1 is a sectional view showing the structure of a conventional multilayer solid electrolytic capacitor.
Generally, after forming an oxide film layer (2) of a dielectric on the surface of an anode substrate (1) made of a metal foil or thin plate having a large specific surface area that has been etched, usually after further providing a masking layer (5), A solid semiconductor layer (hereinafter referred to as a solid electrolyte) functioning as a cathode portion and a conductive layer (3) such as a conductive paste are sequentially formed outside the oxide film layer (2) to produce a capacitor element (6). . A plurality of capacitor elements (6) formed in this manner are laminated in the same direction, and a conductor layer (4) is provided as appropriate, electrode lead portions (7, 8) are added, and the whole is sealed with resin (9). The multilayer solid electrolytic capacitor is stopped.
積層型固体電解コンデンサにおいては、積層するコンデンサ素子（６）の厚さや数を増やすことによりコンデンサの静電容量を高くすることができる。しかし、積層したコンデンサ素子の厚みの合計が大きくなると、コンデンサ素子の封止樹脂からの露出やコンデンサチップを包む封止樹脂にピンホールやウェルドライン等の外観不良が生じやすくなるため、積層したコンデンサ素子の厚さの合計が制限されることが問題であった。 In a multilayer solid electrolytic capacitor, the capacitance of the capacitor can be increased by increasing the thickness and number of capacitor elements (6) to be stacked. However, if the total thickness of the laminated capacitor elements increases, the capacitor elements are likely to be exposed from the sealing resin and the appearance of defects such as pinholes and weld lines in the sealing resin that encloses the capacitor chip. The problem is that the total thickness of the elements is limited.
本発明の目的は、積層型固体電解コンデンサの外観不良を生じさせることなく、積層したコンデンサ素子の厚さの合計の許容範囲を広げ、静電容量を高くする技術を提供することにある。 An object of the present invention is to provide a technique for widening the allowable range of the total thickness of the laminated capacitor elements and increasing the capacitance without causing an appearance defect of the laminated solid electrolytic capacitor.
本発明者は、上記課題について鋭意検討した結果、電気をコンデンサチップの外に取り出すための金属製リードフレームにコンデンサ素子を１つ以上積層し、樹脂で封止したコンデンサチップ内において、積層体の配置を一定範囲内の配置とすることによって積層体の厚さが厚くなっても外観不良ができにくいことを見出し、本発明を完成した。 As a result of earnestly examining the above problems, the present inventor has laminated one or more capacitor elements on a metal lead frame for taking electricity out of the capacitor chip, and in the capacitor chip sealed with resin, The inventors have found that by arranging the arrangement within a certain range, it is difficult to cause an appearance defect even when the thickness of the laminate is increased, and the present invention has been completed.
すなわち、本発明は以下に示すコンデンサチップ及びその製造方法、特に積層型固体電解コンデンサ及びその製造方法に関する。
［１］リードフレームの一方または両面にコンデンサ素子を積層し、得られた積層体を樹脂封止してなるコンデンサチップにおいて、チップ内における前記積層体の厚さをＨｓ、コンデンサチップの厚さをＨｃとし、積層体上部から封止樹脂上面までの距離の最小距離をＤｔとし、積層体下部から封止樹脂下面までの距離の最小距離をＤｂとした場合に、Ｈｃ−Ｈｓが０．１ｍｍ以上であり、かつＤｔ及びＤｂの比Ｄｔ／Ｄｂが０．１から９であり、かつＤｔ及びＤｂのいずれも０．０２ｍｍ以上であるコンデンサチップ。
［２］Ｈｃ−Ｈｓが０．３ｍｍ以上である前記１に記載のコンデンサチップ。
［３］Ｈｃ−Ｈｓが０．６ｍｍ以上である前記２に記載のコンデンサチップ。
［４］Ｄｔ／Ｄｂが０．２〜６である前記１〜３のいずれかに記載のコンデンサチップ。
［５］Ｄｔ／Ｄｂが０．２〜０．７または１．５〜５である前記１〜３のいずれかに記載のコンデンサチップ。
［６］少なくともリードフレームの一方の面に２以上のコンデンサ素子が積層された前記１〜５のいずれかに記載の積層型コンデンサチップ。
［７］コンデンサ素子が弁作用金属からなる陽極基体を含み、前記弁作用金属表面の一部に誘電体層である酸化皮膜層と陰極層である固体電解質層を形成してなる固体電解コンデンサ素子である前記１〜６のいずれかに記載の固体電解コンデンサ。
［８］弁作用金属がマグネシウム、シリコン、アルミニウム、ジルコニウム、チタン、タンタル、ニオブ、ハフニウムのいずれかを主成分とする金属及びそれらの合金から選択される前記７に記載の固体電解コンデンサ。
［９］リードフレームの一方または両面にコンデンサ素子を積層し、得られた積層体を樹脂封止する工程を含むコンデンサチップの製造方法において、チップ内における前記積層体の厚さをＨｓ、コンデンサチップの厚さをＨｃとし、積層体上部から封止樹脂上面までの距離の最小距離をＤｔとし、積層体下部から封止樹脂下面までの距離の最小距離をＤｂとした場合に、Ｈｃ−Ｈｓが０．１ｍｍ以上であり、かつＤｔ及びＤｂの比Ｄｔ／Ｄｂが０．１から９であり、かつＤｔ及びＤｂのいずれも０．０２ｍｍ以上とするコンデンサチップの製造方法。That is, the present invention relates to a capacitor chip and a manufacturing method thereof, and more particularly to a multilayer solid electrolytic capacitor and a manufacturing method thereof.
[1] In a capacitor chip in which capacitor elements are stacked on one or both surfaces of a lead frame and the obtained stacked body is resin-sealed, the thickness of the stacked body in the chip is Hs, and the thickness of the capacitor chip is Hc−Hs is 0.1 mm or more, where Hc is the minimum distance from the top of the laminate to the top surface of the sealing resin is Dt, and the minimum distance from the bottom of the stack to the bottom surface of the sealing resin is Db. A capacitor chip in which the ratio Dt / Db of Dt and Db is 0.1 to 9, and both Dt and Db are 0.02 mm or more.
[2] The capacitor chip as described in 1 above, wherein Hc—Hs is 0.3 mm or more.
[3] The capacitor chip as described in 2 above, wherein Hc-Hs is 0.6 mm or more.
[4] The capacitor chip according to any one of 1 to 3, wherein Dt / Db is 0.2 to 6.
[5] The capacitor chip according to any one of 1 to 3, wherein Dt / Db is 0.2 to 0.7 or 1.5 to 5.
[6] The multilayer capacitor chip as described in any one of [1] to [5], wherein two or more capacitor elements are stacked on at least one surface of the lead frame.
[7] A solid electrolytic capacitor element in which the capacitor element includes an anode base made of a valve metal, and an oxide film layer as a dielectric layer and a solid electrolyte layer as a cathode layer are formed on a part of the surface of the valve metal. The solid electrolytic capacitor as described in any one of 1 to 6 above.
[8] The solid electrolytic capacitor as described in 7 above, wherein the valve-acting metal is selected from metals containing magnesium, silicon, aluminum, zirconium, titanium, tantalum, niobium, and hafnium as a main component and alloys thereof.
[9] In a method of manufacturing a capacitor chip including a step of laminating capacitor elements on one or both sides of a lead frame and resin-sealing the obtained laminate, the thickness of the laminate in the chip is Hs, Where Hc is Hc, the minimum distance from the top of the laminate to the top surface of the sealing resin is Dt, and the minimum distance from the bottom of the stack to the bottom surface of the sealing resin is Db. A method for manufacturing a capacitor chip, which is 0.1 mm or more, the ratio Dt / Db of Dt and Db is 0.1 to 9, and both Dt and Db are 0.02 mm or more.
本発明によれば、外観不良がなく、静電容量の高い積層型固体電解コンデンサを製造することができる。なお、本発明はコンデンサチップ一般に適用可能である。 According to the present invention, it is possible to manufacture a multilayer solid electrolytic capacitor having no appearance defect and high capacitance. The present invention is applicable to general capacitor chips.
以下、図面を参照して本発明のコンデンサチップ、特にその好適態様である積層型固体電解コンデンサを例としてより具体的に説明する。 Hereinafter, a capacitor chip of the present invention, particularly a multilayer solid electrolytic capacitor which is a preferred embodiment thereof will be described more specifically with reference to the drawings.
図２は本発明の好ましい実施態様におけるコンデンサチップ（積層型固体電解コンデンサ）の断面図である。
本発明のコンデンサチップは、電圧をコンデンサチップに印可するための金属製リードフレーム（１１）にコンデンサ素子（６）を１つ以上積層し、封止樹脂（９）で封止したコンデンサチップにおいて、積層後のコンデンサ素子（６）とリードフレーム（１１）の合計厚さをＨｓとし、グルーパッド（１０）等の突起部を含まない封止後のコンデンサチップの厚さをＨｃとし、積層上部から封止樹脂上面までの距離の最小距離をＤｔとし、積層下部からグルーパッドなどの突起部を含まない封止樹脂下面までの距離の最小距離をＤｂとした場合に、Ｈｃ−Ｈｓが０．１ｍｍ以上であり、かつＤｔ及びＤｂの比Ｄｔ／Ｄｂが０．１から９であり、かつＤｔ及びＤｂのいずれも０．０２ｍｍ以上とすることを特徴とする。FIG. 2 is a cross-sectional view of a capacitor chip (multilayer solid electrolytic capacitor) according to a preferred embodiment of the present invention.
The capacitor chip of the present invention is a capacitor chip in which one or more capacitor elements (6) are stacked on a metal lead frame (11) for applying a voltage to the capacitor chip and sealed with a sealing resin (9). The total thickness of the capacitor element (6) and the lead frame (11) after stacking is Hs, and the thickness of the capacitor chip after sealing that does not include protrusions such as the glue pads (10) is Hc. Hc-Hs is 0.1 mm, where Dt is the minimum distance to the top surface of the sealing resin and Db is the minimum distance from the bottom of the stack to the bottom surface of the sealing resin that does not include protrusions such as glue pads. The ratio Dt / Db between Dt and Db is 0.1 to 9, and both Dt and Db are 0.02 mm or more.
すなわち、本発明は、封止体内においてコンデンサ素子とリードフレームを含む積層体の位置を特定の範囲に位置づけることにより外観不良を解消したものである。
Ｈｃ−Ｈｓ（＝Ｄｔ＋Ｄｂ）は上記のように０．１ｍｍ以上とする。０．１ｍｍ未満では外観不良を生じる。目的や用途にもよるが、ある程度、厚みが許容される場合には、好ましくは０．３ｍｍ以上、より好ましくは０．６ｍｍ以上とする。Ｈｃ−Ｈｓの上限は限定されないが、Ｈｃ−Ｈｓはコンデンサ容量には寄与しない厚みであり、単位体積当たりより大きな容量を確保する必要から、通常、５ｍｍ以下、好ましくは２ｍｍ以下、より好ましくは１ｍｍ以下である。That is, according to the present invention, the appearance defect is eliminated by positioning the position of the laminated body including the capacitor element and the lead frame in a specific range in the sealed body.
Hc−Hs (= Dt + Db) is 0.1 mm or more as described above. If it is less than 0.1 mm, an appearance defect is caused. Although depending on the purpose and application, when the thickness is allowed to some extent, it is preferably 0.3 mm or more, more preferably 0.6 mm or more. The upper limit of Hc-Hs is not limited, but Hc-Hs is a thickness that does not contribute to the capacitor capacity, and since it is necessary to secure a larger capacity per unit volume, it is usually 5 mm or less, preferably 2 mm or less, more preferably 1 mm. It is as follows.
Ｄｔ／Ｄｂは上記のように０．１〜９の範囲内とする。Ｄｔ／ＤｂはＨｃ−Ｈｓが比較的大きい場合（例えば、０．６ｍｍ以上の場合）は上記範囲内であればよいが、Ｈｃ−Ｈｓが比較的小さい場合（例えば、０．６ｍｍ未満の場合）は、より１に近い値が好ましく、例えば、０．２〜６、より好ましくは０．３〜３である。 Dt / Db is within the range of 0.1 to 9 as described above. Dt / Db may be within the above range when Hc-Hs is relatively large (for example, 0.6 mm or more), but Hc-Hs is relatively small (for example, less than 0.6 mm). Is preferably a value closer to 1, for example, 0.2 to 6, more preferably 0.3 to 3.
なお、Ｄｔ／Ｄｂ比がある範囲を超えると、樹脂封止時に積層体上面と積層体下面における樹脂の流入速度のバランスが崩れると考えられる。例えばＤｔ＞Ｄｂの場合、積層体下面と封止金型の距離が狭く、封止時の樹脂の流入速度が積層体上面より速くなり、その流入速度に起因する応力が素子に加わると考えられる。このときＤｔ／Ｄｂ比が小さいうちは漏れ電流に影響を与えないが、ある値を超えると、その応力により漏れ電流に影響を与えると考えられる。Ｄｔ＜Ｄｂの場合も同様である。なお、上記の機構は本発明の結果を基に考察したものであり、本発明以前に予想されたものではない。また、本発明は上記機構を介するか否かによって限定されるものではない。 In addition, when Dt / Db ratio exceeds a certain range, it is thought that the balance of the inflow rate of the resin in the upper surface of the laminate and the lower surface of the laminate is lost during resin sealing. For example, in the case of Dt> Db, the distance between the lower surface of the laminate and the sealing mold is narrow, the inflow speed of the resin at the time of sealing is faster than the upper surface of the stack, and the stress due to the inflow speed is considered to be applied to the element. . At this time, while the Dt / Db ratio is small, the leakage current is not affected. However, if the value exceeds a certain value, it is considered that the leakage current is affected by the stress. The same applies when Dt <Db. In addition, said mechanism is considered based on the result of this invention, and is not anticipated before this invention. Moreover, this invention is not limited by whether the said mechanism is interposed.
また、Ｄｔ、Ｄｂはいずれも０．０２ｍｍ以上とすることが耐湿性の観点から好ましく、単位体積当たりの容量を確保するという観点からは５ｍｍ以下、好ましくは２ｍｍ以下、より好ましくは１ｍｍ以下である。
なお、Ｄｔ、Ｄｂはいずれも樹脂層の厚さであり、コンデンサチップの厚みのうち、上記のグルーパッドその他の実装補助部材（図２中１０）や実装用電極（同図中の陽極リード部７、陰極リード部８）は含まない。In addition, Dt and Db are each preferably 0.02 mm or more from the viewpoint of moisture resistance, and from the viewpoint of ensuring capacity per unit volume, 5 mm or less, preferably 2 mm or less, more preferably 1 mm or less. .
Note that Dt and Db are the thickness of the resin layer. Of the thickness of the capacitor chip, the above-mentioned glue pad and other mounting auxiliary members (10 in FIG. 2) and mounting electrodes (the anode lead portion in the same figure) 7 and cathode lead portion 8) are not included.
（固体電解コンデンサ素子）
コンデンサ素子（６）は、積層可能であれば特に限定されず、板状、棒状、線状、好ましくは概ね平板状の素子、例えば、箔ないし薄板等の素子である。典型的には、図１及び２に示すように、陽極基体（１）上に酸化皮膜層（２）を有し、さらにその上に固体電解質層（３）を有するコンデンサ素子である。(Solid electrolytic capacitor element)
The capacitor element (6) is not particularly limited as long as it can be laminated. The capacitor element (6) is a plate-like, rod-like, or linear, preferably substantially flat-like element, for example, an element such as a foil or a thin plate. Typically, as shown in FIGS. 1 and 2, a capacitor element having an oxide film layer (2) on an anode substrate (1) and further having a solid electrolyte layer (3) thereon.
（弁作用金属）
本発明において、固体電解コンデンサの陽極基体として用いられる弁作用金属としては、マグネシウム、シリコン、アルミニウム、ジルコニウム、チタン、タンタル、ニオブ、ハフニウムのいずれかを主成分とする金属及びそれらの合金が挙げられる。これらは各金属の多孔体でもよい。多孔質の形態については、圧延箔のエッチング物、微粉焼結体など、多孔質成形体のいずれの形態でもよい。(Valve action metal)
In the present invention, examples of the valve action metal used as the anode substrate of the solid electrolytic capacitor include metals mainly containing any of magnesium, silicon, aluminum, zirconium, titanium, tantalum, niobium, and hafnium, and alloys thereof. . These may be porous bodies of each metal. About a porous form, any form of porous molded objects, such as an etching thing of a rolled foil, a fine powder sintered compact, may be sufficient.
陽極基体（１）の形状としては、平板状の箔や板や棒状等が挙げられる。
厚さは使用目的によって異なるが、例えば、約４０〜３００μｍの範囲が使用される。薄型の固体電解コンデンサとするためには、金属（例えば、アルミニウム）箔では８０〜２５０μｍのものを使用することが好ましい。
金属箔の大きさ及び形状も用途により異なるが、平板状素子単位として幅約１〜５０ｍｍ、長さ約１〜５０ｍｍの矩形のものが好ましく、より好ましくは幅約２〜１５ｍｍ、長さ約２〜２５ｍｍである。Examples of the shape of the anode substrate (1) include flat foils, plates and rods.
Although the thickness varies depending on the purpose of use, for example, a range of about 40 to 300 μm is used. In order to obtain a thin solid electrolytic capacitor, it is preferable to use a metal (for example, aluminum) foil having a thickness of 80 to 250 μm.
Although the size and shape of the metal foil vary depending on the application, a rectangular element having a width of about 1 to 50 mm and a length of about 1 to 50 mm is preferable as a flat element unit, more preferably about 2 to 15 mm in width and about 2 in length. ~ 25 mm.
（酸化被膜層）
酸化皮膜層（２）は、上記陽極基体（１）を化成処理して得ることができる。
陽極基体の表面に設ける誘電体皮膜層は、弁作用金属の表面部分に設けられた弁作用金属自体の酸化物層であってもよく、あるいは、弁作用金属箔の表面上に設けられた他の誘電体層であってもよいが、特に弁作用金属自体の酸化物からなる層であることが望ましい。(Oxide coating layer)
The oxide film layer (2) can be obtained by chemical conversion of the anode substrate (1).
The dielectric coating layer provided on the surface of the anode substrate may be an oxide layer of the valve action metal itself provided on the surface portion of the valve action metal, or may be provided on the surface of the valve action metal foil. However, a layer made of an oxide of the valve metal itself is desirable.
（固体電解質）
次に、陰極部の誘電体皮膜層上に固体電解質層（３）を形成させる。固体電解質層の種類には特に制限は無く、従来公知の固体電解質が使用できるが、とりわけ高導電率の導電性高分子を固体電解質として作製する固体電解コンデンサは、従来の電解液を用いた湿式電解コンデンサや二酸化マンガンを用いた固体電解コンデンサに比べて、等価直列抵抗成分が低く、大容量でかつ小形となり、高周波性能が良好なために好ましい。(Solid electrolyte)
Next, a solid electrolyte layer (3) is formed on the dielectric coating layer of the cathode part. The type of the solid electrolyte layer is not particularly limited, and a conventionally known solid electrolyte can be used. In particular, a solid electrolytic capacitor for producing a high conductivity conductive polymer as a solid electrolyte is a wet type using a conventional electrolytic solution. Compared to electrolytic capacitors and solid electrolytic capacitors using manganese dioxide, this is preferable because it has a low equivalent series resistance component, a large capacity and a small size, and good high-frequency performance.
また、必要に応じて固体電解質（３）上に導電体層（図示していない。）を設けてもよい。導電体層は、例えば、導電ペースト、メッキや蒸着、導電樹脂フィルムの貼付等により形成される。陰極部分である固体電解質（３）と陽極部分である金属基体（１）との絶縁をより確実にするためにマスキング（５）を設けてもよい。 Moreover, you may provide a conductor layer (not shown) on a solid electrolyte (3) as needed. The conductor layer is formed by, for example, a conductive paste, plating, vapor deposition, or a conductive resin film. Masking (5) may be provided in order to ensure insulation between the solid electrolyte (3) as the cathode portion and the metal substrate (1) as the anode portion.
（積層型固体電解コンデンサの製造方法）
本発明の好ましい実施態様における積層型固体電解コンデンサは、リードフレーム（１１）（陰極部及び陽極部下面に段差を設けてもよい）上に固体電解コンデンサ素子（６）を積層するか、固体電解コンデンサ素子（６）の積層体をリードフレーム（１１）上に固定した後、前記リードフレーム（１１）の陰極リード部（８）及び陽極リード部（７）のそれぞれ少なくとも一部を露出させて樹脂封止する工程を含む方法によって製造できる。(Manufacturing method of multilayer solid electrolytic capacitor)
In a preferred embodiment of the present invention, the multilayer solid electrolytic capacitor comprises a solid electrolytic capacitor element (6) laminated on a lead frame (11) (a step may be provided on the lower surface of the cathode and anode), or solid electrolytic After the capacitor element (6) laminate is fixed on the lead frame (11), at least a part of each of the cathode lead portion (8) and the anode lead portion (7) of the lead frame (11) is exposed to form a resin. It can be manufactured by a method including a sealing step.
通常は、複数の陰極リード部（８）と複数の陽極リード部（７）が空隙を隔てて対向して設けられたリードフレーム（１１）上に、それぞれ陰極リード部（８）と陽極リード部（７）が位置するように固体電解コンデンサ素子（６）を積層するか、予め形成した固体電解コンデンサ素子の積層体を固定する。
この場合、陽極積層部は陽極リード部（７）と電気的に接続され、陰極積層部は陰極リード部（８）と電気的に接続される。図２に示すように、陽極端面に導体層／部材（４）を設けてもよい。Usually, a cathode lead portion (8) and an anode lead portion are respectively provided on a lead frame (11) provided with a plurality of cathode lead portions (8) and a plurality of anode lead portions (7) facing each other with a gap therebetween. The solid electrolytic capacitor element (6) is laminated so that (7) is located, or a previously formed laminated body of solid electrolytic capacitor elements is fixed.
In this case, the anode laminate portion is electrically connected to the anode lead portion (7), and the cathode laminate portion is electrically connected to the cathode lead portion (8). As shown in FIG. 2, a conductor layer / member (4) may be provided on the anode end face.
コンデンサ素子（６）は、通常は陰極部分が他のコンデンサ素子の陰極部分上に位置するように積層され、陽極部分が他のコンデンサ素子の陽極部分上に位置するように積層される。
陰極部分を他のコンデンサ素子の陰極部分に積層するにはそれぞれを電気的に接続する任意の方法が用いられるが、例えば、導電性ペーストを用いた積層法、ハンダ付け、溶接等が挙げられる。また、固体電解コンデンサ素子積層体のリードフレーム（１１）への固定もこれに準じて行うことができる。The capacitor element (6) is usually laminated so that the cathode portion is located on the cathode portion of the other capacitor element, and is laminated so that the anode portion is located on the anode portion of the other capacitor element.
Arbitrary methods for electrically connecting each of the cathode portions to the cathode portions of other capacitor elements are used, and examples thereof include a lamination method using a conductive paste, soldering, and welding. Further, the solid electrolytic capacitor element laminate can be fixed to the lead frame (11) in accordance with this.
なお、図２ではリード部をリードフレーム（１１）を用いて形成し、この上にコンデンサ素子（６）の積層体を設けているが、図１のように陽極リード部をコンデンサの側面から引き出してもよい。
さらに、図２では積層体の間に陰極リード部を設けているが、陰極、陽極のいずれもリード部分を積層体の上もしくは下に設ける（すなわち、リード部分の片側にそれぞれ１または複数の固体電解コンデンサ素子（６）を設ける）ことも可能である。In FIG. 2, the lead portion is formed by using the lead frame (11), and the laminated body of the capacitor element (6) is provided thereon. However, the anode lead portion is pulled out from the side surface of the capacitor as shown in FIG. May be.
Further, in FIG. 2, the cathode lead portion is provided between the laminates, but both the cathode and the anode are provided with lead portions above or below the laminate (that is, one or more solids on one side of the lead portion, respectively). It is also possible to provide an electrolytic capacitor element (6).
次いで、コンデンサ素子積層構造体（コンデンサ素子積層体を有するリードフレーム）を、露出させるべき陰極リード部及び陽極リード部を残して樹脂封止し、樹脂の硬化後、形成されたコンデンサをその側端部でリードフレームの外枠部分（図示していない）から切り離す。 Next, the capacitor element laminate structure (lead frame having the capacitor element laminate) is resin-sealed leaving the cathode lead portion and the anode lead portion to be exposed, and after the resin is cured, the formed capacitor is connected to its side end. And cut off from the outer frame portion (not shown) of the lead frame.
（封止樹脂）
樹脂封止は、コンデンサ素子を使用環境から保護する目的で当分野で慣用されている任意の方法で行われる。例えば、注型成形、圧縮成形、射出成形などでよいが、注型成形の中でも複数のポットを用いるマルチプランジャーを有したトランスファー成形が好ましい。(Sealing resin)
Resin sealing is performed by any method commonly used in the art for the purpose of protecting the capacitor element from the use environment. For example, cast molding, compression molding, injection molding, and the like may be used, but transfer molding having a multi-plunger using a plurality of pots is preferable among cast molding.
使用される樹脂は、基板実装時のハンダ熱に耐えられる耐熱性を有し、適宜な加熱状態或いは常温において液体状態を得ることができる樹脂であれば好適に使用することができるが、耐湿性、絶縁性等の観点から多用されているエポキシ系樹脂が好ましく使用される。 The resin used can be suitably used as long as it has heat resistance that can withstand soldering heat when mounted on the substrate and can obtain a liquid state at an appropriate heating state or room temperature. Epoxy resins that are frequently used from the viewpoint of insulation and the like are preferably used.
エポキシ樹脂は、液状であり、かつ封止用途に使用されるものであれば制限されることなく用いることができるが、例えば、液状のｏ−クレゾールノボラック型エポキシ樹脂、ビフェニル型エポキシ樹脂、ジシクロペンタジエン型エポキシ樹脂、ビスフェノール型エポキシ樹脂、ブロム含有エポキシ樹脂、ナフタレン骨格を有するエポキシ樹脂等を挙げることができる。 The epoxy resin is liquid and can be used without limitation as long as it is used for sealing purposes. For example, liquid o-cresol novolac epoxy resin, biphenyl epoxy resin, dicyclo Examples thereof include a pentadiene type epoxy resin, a bisphenol type epoxy resin, a bromine-containing epoxy resin, and an epoxy resin having a naphthalene skeleton.
以下に本発明の実施例を示すが、これらは説明のための単なる例示であって、本発明はこれらに何等制限されるものでない。 Examples of the present invention are shown below, but these are merely illustrative examples, and the present invention is not limited thereto.
実施例１
アルミニウム化成箔（厚み１００μｍ）を短軸方向３ｍｍ×長軸方向１０ｍｍに切り出し、長軸方向を４ｍｍと５ｍｍの部分に区切るように、両面に幅１ｍｍのポリイミド溶液を周状に塗布、乾燥させマスキングを作成した。この化成箔の３ｍｍ×４ｍｍの部分を、１０質量％のアジピン酸アンモニウム水溶液で４Ｖの電圧を印加して切り口部分に化成し、誘電体酸化皮膜を形成した。次に、このアルミニウム箔の３ｍｍ×４ｍｍの部分を、３，４−エチレンジオキシチオフェンを２５質量％含むイソプロピルアルコール（ＩＰＡ）溶液に１０秒間含浸し、これを室温で１０分間乾燥し、２−アントラキノンスルホン酸ナトリウムが０．０５質量％となるように調整した１ｍｏｌ／Ｌの過硫酸アンモニウム水溶液に１０秒間浸漬した。続いてこのアルミニウム箔を温度４０℃で３０分間放置して酸化重合を行った。さらにこの浸漬工程および重合工程を１２回繰り返し導電性重合体の固体電解質層をアルミニウム箔の外表面に形成した。
最終的に生成したポリ（３，４−エチレンジオキシチオフェン）を純水で洗浄し、その後１００℃で３０分間乾燥を行い、固体電解質層を形成した。
次に、固体電解質層を形成した３ｍｍ×４ｍｍの部分を、１５質量％アジピン酸アンモニウム溶液中に浸漬し、固体電解質層を形成していない部分の弁作用金属箔に陽極の接点を設けて３．８Ｖの電圧を印加し、再化成を行った。
次に、カ−ボンペーストと銀ペーストを被覆し、膜厚計（Peacock社製：デジタルダイヤルゲージＤＧ−２０５，精度３μｍ）を用いて、素子を膜厚計の測定部にゆっくりと挟んで厚みを測定した。平均膜厚は０．２５ｍｍであった。
作製したコンデンサ素子を厚さ０．１ｍｍの金属製リードフレームの上面に２枚、下面に１枚積層し、リードフレームを含む厚さが０．８５ｍｍとなる積層コンデンサ素子を作製した。
積層上面から封止樹脂の上面までの距離が０．３５ｍｍ、積層下面からグルーパッドを除く封止樹脂の下面までの距離が０．５ｍｍとなるようにエポキシ樹脂で封止を行い、グルーパッドを除く高さが１．７ｍｍであるコンデンサチップを１００個作製した。さらに、１０５℃で定格電圧（２Ｖ）を印加して２時間エージングを行い、合計１００個のコンデンサを作製した。
封止後に外観検査を行い、０．０５ｍｍ以上の穴、積層素子の露出、あるいは封止樹脂に０．０５ｍｍ以上のひび割れが生じたものは外観不良とした。結果を表１に示す。またこれら１００個のコンデンサについて、初期特性として１２０Ｈｚにおける容量と損失係数（ｔａｎδ×１００（％））、等価直列抵抗（ＥＳＲ）、それに漏れ電流を測定した。なお、漏れ電流は定格電圧を印加して１分後に測定した。表２にこれらの測定値の平均値と、０．００２ＣＶ以上の漏れ電流を不良品としたときの不良率を示した。ここで、漏れ電流の平均値は不良品を除いて計算した値である。Example 1
Cut aluminum alloy foil (thickness: 100μm) into 3mm minor axis direction x 10mm major axis direction, and apply a polyimide solution with a width of 1mm on both sides and dry to mask the major axis direction into 4mm and 5mm parts. It was created. A 3 mm × 4 mm portion of this chemical conversion foil was formed into a cut portion by applying a voltage of 4 V with a 10 mass% ammonium adipate aqueous solution to form a dielectric oxide film. Next, a 3 mm × 4 mm portion of the aluminum foil was impregnated with an isopropyl alcohol (IPA) solution containing 25% by mass of 3,4-ethylenedioxythiophene for 10 seconds, and this was dried at room temperature for 10 minutes. It was immersed for 10 seconds in a 1 mol / L ammonium persulfate aqueous solution adjusted to 0.05 mass% sodium anthraquinonesulfonate. Subsequently, this aluminum foil was left to stand at a temperature of 40 ° C. for 30 minutes for oxidative polymerization. Furthermore, this immersion process and polymerization process were repeated 12 times to form a solid electrolyte layer of a conductive polymer on the outer surface of the aluminum foil.
The finally produced poly (3,4-ethylenedioxythiophene) was washed with pure water and then dried at 100 ° C. for 30 minutes to form a solid electrolyte layer.
Next, a 3 mm × 4 mm portion where the solid electrolyte layer was formed was immersed in a 15% by mass ammonium adipate solution, and an anode contact was provided on the portion of the valve action metal foil where the solid electrolyte layer was not formed. Reforming was performed by applying a voltage of .8V.
Next, a carbon paste and a silver paste are coated, and the thickness is measured by slowly sandwiching the element between the thickness gauge measurement parts using a film thickness meter (Peacock, Digital Dial Gauge DG-205,
Two of the produced capacitor elements were laminated on the upper surface of a metal lead frame having a thickness of 0.1 mm and one on the lower surface to produce a multilayer capacitor element having a thickness including the lead frame of 0.85 mm.
The glue pad is sealed with epoxy resin so that the distance from the top surface of the laminate to the top surface of the sealing resin is 0.35 mm, and the distance from the bottom surface of the laminate to the bottom surface of the sealing resin excluding the glue pad is 0.5 mm. 100 capacitor chips with a height of 1.7 mm were prepared. Furthermore, a rated voltage (2 V) was applied at 105 ° C. and aging was performed for 2 hours, and a total of 100 capacitors were produced.
After sealing, an appearance inspection was performed, and a hole having a thickness of 0.05 mm or more, exposure of the laminated element, or cracking of 0.05 mm or more in the sealing resin was regarded as a defective appearance. The results are shown in Table 1. Further, with respect to these 100 capacitors, the capacity and loss coefficient at 120 Hz (tan δ × 100 (%)), equivalent series resistance (ESR), and leakage current were measured as initial characteristics. The leakage current was measured 1 minute after applying the rated voltage. Table 2 shows the average value of these measured values and the defective rate when a leakage current of 0.002 CV or more is regarded as a defective product. Here, the average value of the leakage current is a value calculated excluding defective products.
実施例２
実施例１で作製した厚さ０．２５ｍｍのコンデンサ素子を、厚さ０．１ｍｍの金属製リードフレームの上面に３枚、下面に２枚積層し、リードフレームを含む厚さが１．３５ｍｍとなる積層コンデンサ素子を作製した。
積層上面から封止樹脂の上面までの距離が０．１５ｍｍ、積層下面からグルーパッドを除く封止樹脂の下面までの距離が０．２ｍｍとなるようにした点を除いて実施例１と同様の方法で、グルーパットを除く高さが１．７ｍｍであるコンデンサチップを１００個作製した。また、実施例１と同じ方法で外観検査及びコンデンサ特性の測定を実施した。結果を表１、２に示す。Example 2
Three capacitor elements having a thickness of 0.25 mm manufactured in Example 1 were laminated on the top surface of a metal lead frame having a thickness of 0.1 mm and two on the bottom surface, and the thickness including the lead frame was 1.35 mm. A multilayer capacitor element was produced.
The same as in Example 1 except that the distance from the top surface of the laminate to the top surface of the sealing resin is 0.15 mm, and the distance from the bottom surface of the laminate to the bottom surface of the sealing resin excluding the glue pad is 0.2 mm. By the method, 100 capacitor chips having a height of 1.7 mm excluding the glue pads were produced. Further, the appearance inspection and the measurement of the capacitor characteristics were performed in the same manner as in Example 1. The results are shown in Tables 1 and 2.
実施例３
実施例１で作製した厚さ０．２５ｍｍのコンデンサ素子を、厚さ０．１ｍｍの金属製リードフレームの上面に２枚、下面に２枚積層し、リードフレームを含む厚さが１．１ｍｍとなる積層コンデンサ素子を作製した。
積層上面から封止樹脂の上面までの距離が０．３ｍｍ、積層下面からグルーパッドを除く封止樹脂の下面までの距離が０．３ｍｍとなるようにした点を除いて実施例１と同様の方法で、グルーパットを除く高さが１．７ｍｍであるコンデンサチップを１００個作製した。また、実施例１と同じ方法で外観検査及びコンデンサ特性の測定を実施した。結果を表１、２に示す。Example 3
Two capacitor elements having a thickness of 0.25 mm produced in Example 1 were laminated on the upper surface and two on the lower surface of a metal lead frame having a thickness of 0.1 mm, and the thickness including the lead frame was 1.1 mm. A multilayer capacitor element was produced.
The same as in Example 1 except that the distance from the upper surface of the laminate to the upper surface of the sealing resin is 0.3 mm, and the distance from the lower surface of the laminate to the lower surface of the sealing resin excluding the glue pad is 0.3 mm. By the method, 100 capacitor chips having a height of 1.7 mm excluding the glue pads were produced. Further, the appearance inspection and the measurement of the capacitor characteristics were performed in the same manner as in Example 1. The results are shown in Tables 1 and 2.
実施例４
実施例１で作製した厚さ０．２５ｍｍのコンデンサ素子を、厚さ０．１ｍｍの金属製リードフレームの上面に３枚、下面に１枚積層し、リードフレームを含む厚さが１．１ｍｍとなる積層コンデンサ素子を作製した。
積層上面から封止樹脂の上面までの距離が０．１ｍｍ、積層下面からグルーパッドを除く封止樹脂の下面までの距離が０．５ｍｍとなるようにした点を除いて実施例１と同様の方法で、グルーパットを除く高さが１．７ｍｍであるコンデンサチップを１００個作製した。また、実施例１と同じ方法で外観検査及びコンデンサ特性の測定を実施した。結果を表１、２に示す。Example 4
Three capacitor elements with a thickness of 0.25 mm produced in Example 1 were laminated on the top surface of a metal lead frame with a thickness of 0.1 mm and one on the bottom surface, and the thickness including the lead frame was 1.1 mm. A multilayer capacitor element was produced.
The same as in Example 1 except that the distance from the upper surface of the laminate to the upper surface of the sealing resin is 0.1 mm, and the distance from the lower surface of the laminate to the lower surface of the sealing resin excluding the glue pad is 0.5 mm. By the method, 100 capacitor chips having a height of 1.7 mm excluding the glue pads were produced. Further, the appearance inspection and the measurement of the capacitor characteristics were performed in the same manner as in Example 1. The results are shown in Tables 1 and 2.
実施例５
実施例１で作製した厚さ０．２５ｍｍのコンデンサ素子を、厚さ０．１ｍｍの金属製リードフレームの上面に３枚、下面に２枚積層し、リードフレームを含む厚さが１．３５ｍｍとなる積層コンデンサ素子を作製した。
積層上面から封止樹脂の上面までの距離が０．１ｍｍ、積層下面からグルーパッドを除く封止樹脂の下面までの距離が０．２５ｍｍとなるようにした点を除いて実施例１と同様の方法で、グルーパットを除く高さが１．７ｍｍであるコンデンサチップを１００個作製した。また、実施例１と同じ方法で外観検査及びコンデンサ特性の測定を実施した。結果を表１、２に示す。Example 5
Three capacitor elements having a thickness of 0.25 mm manufactured in Example 1 were laminated on the top surface of a metal lead frame having a thickness of 0.1 mm and two on the bottom surface, and the thickness including the lead frame was 1.35 mm. A multilayer capacitor element was produced.
The same as in Example 1 except that the distance from the upper surface of the laminated resin to the upper surface of the sealing resin is 0.1 mm, and the distance from the lower surface of the laminated resin to the lower surface of the sealing resin excluding the glue pad is 0.25 mm. By the method, 100 capacitor chips having a height of 1.7 mm excluding the glue pads were produced. Further, the appearance inspection and the measurement of the capacitor characteristics were performed in the same manner as in Example 1. The results are shown in Tables 1 and 2.
実施例６
実施例１で作製した厚さ０．２５ｍｍのコンデンサ素子を、厚さ０．１ｍｍの金属製リードフレームの上面に３枚、下面に１枚積層し、リードフレームを含む厚さが１．１ｍｍとなる積層コンデンサ素子を作製した。
積層上面から封止樹脂の上面までの距離が０．１２ｍｍ、積層下面からグルーパッドを除く封止樹脂の下面までの距離が０．４８ｍｍとなるようにした点を除いて実施例１と同様の方法で、グルーパットを除く高さが１．７ｍｍであるコンデンサチップを１００個作製した。また、実施例１と同じ方法で外観検査及びコンデンサ特性の測定を実施した。結果を表１、２に示す。Example 6
Three capacitor elements with a thickness of 0.25 mm produced in Example 1 were laminated on the top surface of a metal lead frame with a thickness of 0.1 mm and one on the bottom surface, and the thickness including the lead frame was 1.1 mm. A multilayer capacitor element was produced.
The same as in Example 1 except that the distance from the top surface of the laminate to the top surface of the sealing resin is 0.12 mm, and the distance from the bottom surface of the laminate to the bottom surface of the sealing resin excluding the glue pad is 0.48 mm. By the method, 100 capacitor chips having a height of 1.7 mm excluding the glue pads were produced. Further, the appearance inspection and the measurement of the capacitor characteristics were performed in the same manner as in Example 1. The results are shown in Tables 1 and 2.
実施例７
実施例１で作製した厚さ０．２５ｍｍのコンデンサ素子を、厚さ０．１ｍｍの金属製リードフレームの上面に１枚、下面に３枚積層し、リードフレームを含む厚さが１．１ｍｍとなる積層コンデンサ素子を作製した。
積層上面から封止樹脂の上面までの距離が０．５２ｍｍ、積層下面からグルーパッドを除く封止樹脂の下面までの距離が０．０８ｍｍとなるようにした点を除いて実施例１と同様の方法で、グルーパットを除く高さが１．７ｍｍであるコンデンサチップを１００個作製した。また、実施例１と同じ方法で外観検査及びコンデンサ特性の測定を実施した。結果を表１、２に示す。Example 7
The capacitor element having a thickness of 0.25 mm produced in Example 1 was laminated on the upper surface of the 0.1 mm-thick metal lead frame and three on the lower surface, and the thickness including the lead frame was 1.1 mm. A multilayer capacitor element was produced.
The same as in Example 1 except that the distance from the upper surface of the laminated resin to the upper surface of the sealing resin is 0.52 mm, and the distance from the lower surface of the laminated resin to the lower surface of the sealing resin excluding the glue pad is 0.08 mm. By the method, 100 capacitor chips having a height of 1.7 mm excluding the glue pads were produced. Further, the appearance inspection and the measurement of the capacitor characteristics were performed in the same manner as in Example 1. The results are shown in Tables 1 and 2.
実施例８
厚さ０．２９ｍｍのコンデンサ素子を、厚さ０．１ｍｍの金属製リードフレームの上面に３枚、下面に２枚積層し、リードフレームを含む厚さが１．５５ｍｍとなる積層コンデンサ素子を作製した。
積層上面から封止樹脂の上面までの距離が０．１０ｍｍ、積層下面からグルーパッドを除く封止樹脂の下面までの距離が０．０５ｍｍとなるようにした点を除いて実施例１と同様の方法で、グルーパットを除く高さが１．７ｍｍであるコンデンサチップを１００個作製した。また、実施例１と同じ方法で外観検査及びコンデンサ特性の測定を実施した。結果を表１、２に示す。Example 8
Three capacitor elements having a thickness of 0.29 mm are laminated on the upper surface and two on the lower surface of a 0.1 mm thick metal lead frame to produce a multilayer capacitor element having a thickness including the lead frame of 1.55 mm. did.
The same as in Example 1 except that the distance from the top surface of the laminate to the top surface of the sealing resin is 0.10 mm, and the distance from the bottom surface of the laminate to the bottom surface of the sealing resin excluding the glue pad is 0.05 mm. By the method, 100 capacitor chips having a height of 1.7 mm excluding the glue pads were produced. Further, the appearance inspection and the measurement of the capacitor characteristics were performed in the same manner as in Example 1. The results are shown in Tables 1 and 2.
比較例１
実施例１で作製した厚さ０．２５ｍｍのコンデンサ素子を、厚さ０．１ｍｍの金属製リードフレームの上面に３枚、下面に２枚積層し、リードフレームを含む厚さが１．３５ｍｍとなる積層コンデンサ素子を作製した。
積層上面から封止樹脂の上面までの距離が０．３２ｍｍ、積層下面からグルーパッドを除く封止樹脂の下面までの距離が０．０３ｍｍとなるようにエポキシ樹脂で封止を行い、グルーパッドを除く高さが１．７ｍｍであるコンデンサチップを１００個作製した。また、実施例１と同じ方法で外観検査及びコンデンサ特性の測定を実施した。結果を表１、２に示す。Comparative Example 1
Three capacitor elements having a thickness of 0.25 mm manufactured in Example 1 were laminated on the top surface of a metal lead frame having a thickness of 0.1 mm and two on the bottom surface, and the thickness including the lead frame was 1.35 mm. A multilayer capacitor element was produced.
The glue pad is sealed with epoxy resin so that the distance from the top surface of the laminate to the top surface of the sealing resin is 0.32 mm, and the distance from the bottom surface of the laminate to the bottom surface of the sealing resin excluding the glue pad is 0.03 mm. 100 capacitor chips with a height of 1.7 mm were prepared. Further, the appearance inspection and the measurement of the capacitor characteristics were performed in the same manner as in Example 1. The results are shown in Tables 1 and 2.
比較例２
厚さ０．３０ｍｍのコンデンサ素子を、厚さ０．１ｍｍの金属製リードフレームの上面に３枚、下面に２枚積層し、リードフレームを含む厚さが１．６０ｍｍとなる積層コンデンサ素子を作製した。
積層上面から封止樹脂の上面までの距離が０．０９ｍｍ、積層下面からグルーパッドを除く封止樹脂の下面までの距離が０．０１ｍｍとなるようにエポキシ樹脂で封止を行い、グルーパッドを除く高さが１．７ｍｍであるコンデンサチップを１００個作製した。また、実施例１と同じ方法で外観検査及びコンデンサ特性の測定を実施した。結果を表１、２に示す。Comparative Example 2
Three capacitor elements with a thickness of 0.30 mm are laminated on the top surface and two on the bottom surface of a metal lead frame with a thickness of 0.1 mm to produce a multilayer capacitor element having a thickness including the lead frame of 1.60 mm. did.
The glue pad is sealed with epoxy resin so that the distance from the top surface of the laminate to the top surface of the sealing resin is 0.09 mm and the distance from the bottom surface of the laminate to the bottom surface of the sealing resin excluding the glue pad is 0.01 mm. 100 capacitor chips with a height of 1.7 mm were prepared. Further, the appearance inspection and the measurement of the capacitor characteristics were performed in the same manner as in Example 1. The results are shown in Tables 1 and 2.
比較例３
厚さ０．２６ｍｍのコンデンサ素子を、厚さ０．１ｍｍの金属製リードフレームの上面に３枚、下面に３枚積層し、リードフレームを含む厚さが１．６６ｍｍとなる積層コンデンサ素子を作製した。
積層上面から封止樹脂の上面までの距離が０．０２ｍｍ、積層下面からグルーパッドを除く封止樹脂の下面までの距離が０．０２ｍｍとなるようにエポキシ樹脂で封止を行い、グルーパッドを除く高さが１．７ｍｍであるコンデンサチップを１００個作製た。また、実施例１と同じ方法で外観検査及びコンデンサ特性の測定を実施した。結果を表１、２に示す。Comparative Example 3
Three capacitor elements having a thickness of 0.26 mm are laminated on the top surface and three on the bottom surface of a metal lead frame having a thickness of 0.1 mm to produce a multilayer capacitor element having a thickness including the lead frame of 1.66 mm. did.
The glue pad is sealed with epoxy resin so that the distance from the top surface of the laminate to the top surface of the sealing resin is 0.02 mm, and the distance from the bottom surface of the laminate to the bottom surface of the sealing resin excluding the glue pad is 0.02 mm. 100 capacitor chips having a height of 1.7 mm were removed. Further, the appearance inspection and the measurement of the capacitor characteristics were performed in the same manner as in Example 1. The results are shown in Tables 1 and 2.
本発明によれば、外観不良が少なく、静電容量の高い積層型固体電解コンデンサを製造することができる。このため、本発明のコンデンサ及びその製造方法は、広い分野の積層コンデンサの製造において有用である。 According to the present invention, it is possible to manufacture a multilayer solid electrolytic capacitor with few appearance defects and high capacitance. For this reason, the capacitor and the manufacturing method thereof of the present invention are useful in the manufacture of multilayer capacitors in a wide field.
１ 陽極基体
２ 酸化被膜層
３ 固体電解質層
４ 導電層
５ マスキング
６ コンデンサ素子
７ 陽極リード部
８ 陰極リード部
９ 封止樹脂
１０ グルーパッド
１１ 金属リードフレームDESCRIPTION OF SYMBOLS 1
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| CN102117704B (en) * | 2010-01-06 | 2014-04-23 | 钰邦电子（无锡）有限公司 | Stack type solid electrolytic capacitor and manufacturing method thereof |
| CN102142324A (en) * | 2010-02-03 | 2011-08-03 | 钰邦电子（无锡）有限公司 | Sheet stack type solid electrolytic capacitor |
| CN102142321B (en) * | 2010-02-03 | 2014-08-13 | 钰邦电子（无锡）有限公司 | Stack-type solid electrolytic capacitor |
| CN101980345A (en) * | 2010-10-25 | 2011-02-23 | 福建国光电子科技股份有限公司 | Packaging process of solid electrolytic capacitor |
| CN101996773A (en) * | 2010-11-09 | 2011-03-30 | 钰邦电子（无锡）有限公司 | Stack type solid electrolytic capacitor |
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| JPH0697009A (en) * | 1992-09-09 | 1994-04-08 | Showa Denko Kk | Solid electrolytic capacitor |
| JPH08236399A (en) * | 1995-02-22 | 1996-09-13 | Rohm Co Ltd | Solid electrolytic capacitor |
| JP2002319522A (en) * | 2000-05-26 | 2002-10-31 | Matsushita Electric Ind Co Ltd | Solid electrolytic capacitor |
| JP2004055699A (en) * | 2002-07-18 | 2004-02-19 | Nec Tokin Corp | Solid electrolytic capacitor and its manufacturing method |
| JP2004087713A (en) * | 2002-08-26 | 2004-03-18 | Japan Carlit Co Ltd:The | Aluminum solid electrolytic capacitor |
| JP2005101562A (en) * | 2003-08-20 | 2005-04-14 | Showa Denko Kk | Chip solid electrolytic capacitor and its manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH0697009A (en) * | 1992-09-09 | 1994-04-08 | Showa Denko Kk | Solid electrolytic capacitor |
| JPH08236399A (en) * | 1995-02-22 | 1996-09-13 | Rohm Co Ltd | Solid electrolytic capacitor |
| JP2002319522A (en) * | 2000-05-26 | 2002-10-31 | Matsushita Electric Ind Co Ltd | Solid electrolytic capacitor |
| JP2004055699A (en) * | 2002-07-18 | 2004-02-19 | Nec Tokin Corp | Solid electrolytic capacitor and its manufacturing method |
| JP2004087713A (en) * | 2002-08-26 | 2004-03-18 | Japan Carlit Co Ltd:The | Aluminum solid electrolytic capacitor |
| JP2005101562A (en) * | 2003-08-20 | 2005-04-14 | Showa Denko Kk | Chip solid electrolytic capacitor and its manufacturing method |
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| CN101317241B (en) | 2012-12-05 |
| JPWO2007069670A1 (en) | 2009-05-21 |
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| CN101317241A (en) | 2008-12-03 |
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