JP4945592B2 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
- Publication number
- JP4945592B2 JP4945592B2 JP2009060928A JP2009060928A JP4945592B2 JP 4945592 B2 JP4945592 B2 JP 4945592B2 JP 2009060928 A JP2009060928 A JP 2009060928A JP 2009060928 A JP2009060928 A JP 2009060928A JP 4945592 B2 JP4945592 B2 JP 4945592B2
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- JP
- Japan
- Prior art keywords
- dummy
- mtj
- layer
- mram
- elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1659—Cell access
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/14—Dummy cell management; Sense reference voltage generators
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Hall/Mr Elements (AREA)
- Semiconductor Memories (AREA)
Description
抵抗変化型メモリとしては、磁気ランダムアクセスメモリ(MRAM:magnetic random access memory)、抵抗ランダムアクセスメモリ(ReRAM:resistive random access memory)、相変化ランダムアクセスメモリ(PCRAM:phase-change random access memory)など様々な種類のメモリを使用することが可能である。本実施形態では、抵抗変化型メモリとしてMRAMを一例に挙げて説明する。MRAMは、トンネル磁気抵抗(TMR)効果を利用するMTJ素子を記憶素子(可変抵抗素子)として備え、このMTJ素子の磁化状態により情報を記憶する。
次に、第1の実施形態に係るMRAMの製造方法について図面を参照しつつ説明する。
第2の実施形態は、第1の実施形態の他の構成例であり、活性領域AAをT字形に形成することによって、活性領域AAとソース線SLとを1個のコンタクトプラグで電気的に接続するようにしている。MTJ素子23及びダミー素子28の配列及び構成は、第1の実施形態と同じである。
第3の実施形態は、第1の実施形態と異なるMTJ素子パターンを採用した例である。図22に理想的なMTJ素子パターンのレイアウトを示す。図22のレイアウトは、菱形の密集パターンであり、具体的には、近接する4個のMTJ素子が菱形を形成しており、隣り合う2個の菱形が1つの辺を共有するようにして複数の菱形が密集している。
前述したように、本発明の抵抗変化型メモリとしては、MRAM以外の様々なメモリ、具体的には、ReRAM及びPRAMを用いることが可能である。
Claims (5)
- メモリ領域に配置され、かつ抵抗値の変化に応じてデータを記憶し、かつ第1の配線に一端が電気的に接続され、第2の配線に他端が電気的に接続された複数の磁気抵抗素子と、
前記メモリ領域に配置され、かつ前記磁気抵抗素子と同じ材料からなり、かつ電気的に絶縁された複数のダミー素子と、
を具備し、
前記磁気抵抗素子及び前記ダミー素子からなるアレイは、交差する第1及び第2の方向に格子状に配列され、
前記アレイは、前記第1の方向及び第2の方向のそれぞれにおいて、隣接する素子の間隔が同じになるように配列され、
前記ダミー素子のサイズは、前記磁気抵抗素子のサイズより小さいことを特徴とする半導体記憶装置。 - 前記磁気抵抗素子及び前記ダミー素子は、前記第1の方向に交互に配置されることを特徴とする請求項1に記載の半導体記憶装置。
- 前記ダミー素子は、前記磁気抵抗素子と同じ平面形状を有することを特徴とする請求項1又は2に記載の半導体記憶装置。
- 前記ダミー素子は、前記磁気抵抗素子と同じ高さに配置されることを特徴とする請求項1乃至3のいずれかに記載の半導体記憶装置。
- 前記磁気抵抗素子は、磁化方向が固定された固定層と、磁化方向が変化可能な記録層と、前記固定層及び前記記録層に挟まれた非磁性層とを含み、
前記ダミー素子は、前記磁気抵抗素子と同じ積層構造を有することを特徴とする請求項1乃至4のいずれかに記載の半導体記憶装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009060928A JP4945592B2 (ja) | 2009-03-13 | 2009-03-13 | 半導体記憶装置 |
US12/723,349 US20100232210A1 (en) | 2009-03-13 | 2010-03-12 | Semiconductor memory device and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009060928A JP4945592B2 (ja) | 2009-03-13 | 2009-03-13 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010219098A JP2010219098A (ja) | 2010-09-30 |
JP4945592B2 true JP4945592B2 (ja) | 2012-06-06 |
Family
ID=42730585
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009060928A Expired - Fee Related JP4945592B2 (ja) | 2009-03-13 | 2009-03-13 | 半導体記憶装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US20100232210A1 (ja) |
JP (1) | JP4945592B2 (ja) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7919826B2 (en) * | 2007-04-24 | 2011-04-05 | Kabushiki Kaisha Toshiba | Magnetoresistive element and manufacturing method thereof |
US8681536B2 (en) * | 2010-01-15 | 2014-03-25 | Qualcomm Incorporated | Magnetic tunnel junction (MTJ) on planarized electrode |
JP2011238679A (ja) * | 2010-05-07 | 2011-11-24 | Fujitsu Semiconductor Ltd | 磁気記憶装置の製造方法及び磁気記憶装置 |
JP5702177B2 (ja) | 2011-02-04 | 2015-04-15 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8587982B2 (en) * | 2011-02-25 | 2013-11-19 | Qualcomm Incorporated | Non-volatile memory array configurable for high performance and high density |
JP5554736B2 (ja) | 2011-03-09 | 2014-07-23 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP5518777B2 (ja) | 2011-03-25 | 2014-06-11 | 株式会社東芝 | 半導体記憶装置 |
JP5658704B2 (ja) * | 2012-03-13 | 2015-01-28 | 株式会社東芝 | シフトレジスタ型メモリおよびその駆動方法 |
KR102101407B1 (ko) * | 2013-03-14 | 2020-04-16 | 삼성전자주식회사 | 자기 저항 메모리 장치 및 그 제조 방법 |
US9299410B2 (en) | 2013-09-04 | 2016-03-29 | Shintaro SAKAI | Reading magnetic memory based on regions within a cell array |
KR102102783B1 (ko) * | 2014-01-06 | 2020-04-22 | 삼성전자주식회사 | 반도체 소자, 자기 기억 소자 및 이들의 제조 방법 |
US9269889B2 (en) * | 2014-03-12 | 2016-02-23 | Keiji Hosotani | Semiconductor memory device and manufacturing method thereof |
US9425085B2 (en) | 2014-05-05 | 2016-08-23 | Taiwan Semiconductor Manufacturing Company Limited | Structures, devices and methods for memory devices |
KR102212556B1 (ko) * | 2014-10-08 | 2021-02-08 | 삼성전자주식회사 | 반도체 장치 |
JP2017040628A (ja) * | 2015-08-21 | 2017-02-23 | 株式会社デンソー | 磁気センサ |
JP2018160628A (ja) * | 2017-03-23 | 2018-10-11 | 東芝メモリ株式会社 | 記憶装置 |
TWI811517B (zh) | 2020-01-16 | 2023-08-11 | 聯華電子股份有限公司 | 磁阻式隨機存取記憶體之佈局圖案 |
CN114974339A (zh) * | 2021-02-22 | 2022-08-30 | 联华电子股份有限公司 | 存储器阵列 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55117269A (en) * | 1979-03-02 | 1980-09-09 | Fujitsu Ltd | Semiconductor integrated circuit device |
JP4570313B2 (ja) * | 2001-10-25 | 2010-10-27 | ルネサスエレクトロニクス株式会社 | 薄膜磁性体記憶装置 |
US6466475B1 (en) * | 2001-10-31 | 2002-10-15 | Hewlett-Packard Company | Uniform magnetic environment for cells in an MRAM array |
JP3923914B2 (ja) * | 2002-04-05 | 2007-06-06 | 株式会社東芝 | 磁気記憶装置及びその製造方法 |
JP2004119478A (ja) * | 2002-09-24 | 2004-04-15 | Renesas Technology Corp | 半導体記憶装置、不揮発性記憶装置および磁気記憶装置 |
DE60335904D1 (de) * | 2002-11-28 | 2011-03-10 | Nxp Bv | Verfahren und vorrichtung zum erkennen des beginns einer thermischen relaxation in magnetischen datenspeichern |
US7402851B2 (en) * | 2003-02-24 | 2008-07-22 | Samsung Electronics Co., Ltd. | Phase changeable memory devices including nitrogen and/or silicon and methods for fabricating the same |
JP4247085B2 (ja) * | 2003-09-29 | 2009-04-02 | 株式会社東芝 | 磁気記憶装置およびその製造方法 |
JP4415745B2 (ja) * | 2004-04-22 | 2010-02-17 | ソニー株式会社 | 固体メモリ装置 |
JP2008227009A (ja) * | 2007-03-09 | 2008-09-25 | Toshiba Corp | 磁気ランダムアクセスメモリ、その書き込み方法及びその製造方法 |
-
2009
- 2009-03-13 JP JP2009060928A patent/JP4945592B2/ja not_active Expired - Fee Related
-
2010
- 2010-03-12 US US12/723,349 patent/US20100232210A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20100232210A1 (en) | 2010-09-16 |
JP2010219098A (ja) | 2010-09-30 |
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