JP4940950B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4940950B2 JP4940950B2 JP2006531772A JP2006531772A JP4940950B2 JP 4940950 B2 JP4940950 B2 JP 4940950B2 JP 2006531772 A JP2006531772 A JP 2006531772A JP 2006531772 A JP2006531772 A JP 2006531772A JP 4940950 B2 JP4940950 B2 JP 4940950B2
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- wiring
- film
- copper
- copper alloy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53233—Copper alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Description
(a)半導体基板上方に形成された絶縁膜中の所定の領域に、配線を形成するための溝及びビアを形成する工程と、
(b)前記溝及びビアの表面に拡散防止層を形成する工程と、
(c)前記拡散防止膜上に下層銅又は銅合金膜を、ビア径の5倍以上の幅を持つ配線に接続するビアを形成する溝及びビアに対しては、これらが完全に埋設される厚さ未満となり、かつビア径の5倍未満の幅を持つ配線に接続するビアを形成する溝及びビアに対しては、これらが完全に埋設される厚さ以上となる膜厚に形成する工程と、
(d)この銅又は銅合金膜上に前記銅又は銅合金膜中よりも高い濃度の添加金属元素を含む銅合金からなる他の銅合金膜を、全ての溝及びビアが完全に埋設されるのに十分な厚さに形成する工程と、
(e)前記(d)工程で形成された前記他の銅合金膜中の添加金属元素を前記(c)工程で形成された銅又は銅合金膜中へ拡散させる加熱工程と、
を有することを特徴とする。
2 層間絶縁膜、
3a、3b エッチストップ膜、
4a、4b 層間絶縁膜、
5a、5b バリアメタル膜、
6 配線、
7a、7b 配線保護膜、
8 ビア層間絶縁膜、
9a、9b、9c デュアルダマシン配線、
9a1、9b1、9c 配線部、
9a2、9b2、9c2 ビア部、
10 銅膜、
11 銅合金膜、
12 銅合金シード膜。
次に、本発明の第1形態に係る半導体装置における配線構造につき、図1に示す一実施形態に基づき詳細に説明する。
次に、本発明の第2の実施形態に係る半導体装置における配線構造につき、図1に示す第1実施形態の構造を参照して詳細に説明する。
Claims (1)
- (a)半導体基板上方に形成された絶縁膜中の所定の領域に、配線を形成するための溝及びビアを形成する工程と、
(b)前記溝及びビアの表面に拡散防止層を形成する工程と、
(c)前記拡散防止膜上に下層銅又は銅合金膜を、ビア径の5倍以上の幅を持つ配線に接続するビアを形成する溝及びビアに対しては、これらが完全に埋設される厚さ未満となり、かつビア径の5倍未満の幅を持つ配線に接続するビアを形成する溝及びビアに対しては、これらが完全に埋設される厚さ以上となる膜厚に形成する工程と、
(d)この銅又は銅合金膜上に前記銅又は銅合金膜中よりも高い濃度の添加金属元素を含む銅合金からなる他の銅合金膜を、全ての溝及びビアが完全に埋設されるのに十分な厚さに形成する工程と、
(e)前記(d)工程で形成された前記他の銅合金膜中の添加金属元素を前記(c)工程で形成された銅又は銅合金膜中へ拡散させる加熱工程と、
を有することを特徴とする半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006531772A JP4940950B2 (ja) | 2004-08-12 | 2005-08-12 | 半導体装置の製造方法 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004235133 | 2004-08-12 | ||
JP2004235133 | 2004-08-12 | ||
PCT/JP2005/014855 WO2006016678A1 (ja) | 2004-08-12 | 2005-08-12 | 半導体装置及びその製造方法 |
JP2006531772A JP4940950B2 (ja) | 2004-08-12 | 2005-08-12 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2006016678A1 JPWO2006016678A1 (ja) | 2008-05-01 |
JP4940950B2 true JP4940950B2 (ja) | 2012-05-30 |
Family
ID=35839435
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006531772A Expired - Fee Related JP4940950B2 (ja) | 2004-08-12 | 2005-08-12 | 半導体装置の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (3) | US8004087B2 (ja) |
JP (1) | JP4940950B2 (ja) |
WO (1) | WO2006016678A1 (ja) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7795152B2 (en) * | 2006-05-10 | 2010-09-14 | Micron Technology, Inc. | Methods of making self-aligned nano-structures |
CN102067293B (zh) * | 2008-06-18 | 2013-07-03 | 富士通株式会社 | 半导体器件及其制造方法 |
JP5353109B2 (ja) * | 2008-08-15 | 2013-11-27 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
JP5251639B2 (ja) * | 2009-03-16 | 2013-07-31 | 富士通セミコンダクター株式会社 | 半導体装置の設計検証装置 |
JP2010245235A (ja) * | 2009-04-03 | 2010-10-28 | Panasonic Corp | 半導体装置及びその製造方法 |
JP2011238828A (ja) * | 2010-05-12 | 2011-11-24 | Nec Corp | 半導体装置及びその製造方法 |
WO2012133400A1 (ja) * | 2011-03-30 | 2012-10-04 | 東京エレクトロン株式会社 | Cu配線の形成方法 |
US9679863B2 (en) * | 2011-09-23 | 2017-06-13 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming interconnect substrate for FO-WLCSP |
KR101992352B1 (ko) * | 2012-09-25 | 2019-06-24 | 삼성전자주식회사 | 반도체 장치 |
JP6282474B2 (ja) | 2014-01-31 | 2018-02-21 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
WO2018063208A1 (en) * | 2016-09-29 | 2018-04-05 | Intel Corporation | Metal aluminum gallium indium carbide thin films as liners and barriers for interconnects |
JP6472551B2 (ja) * | 2018-01-24 | 2019-02-20 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6640391B2 (ja) * | 2019-01-22 | 2020-02-05 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2020065069A (ja) * | 2019-12-25 | 2020-04-23 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09289214A (ja) | 1996-04-24 | 1997-11-04 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置およびその製造方法 |
JP3540699B2 (ja) * | 1998-01-12 | 2004-07-07 | 松下電器産業株式会社 | 半導体装置の製造方法 |
JP2001217242A (ja) * | 2000-02-03 | 2001-08-10 | Seiko Epson Corp | 半導体装置およびその製造方法 |
JP2002033384A (ja) | 2000-07-13 | 2002-01-31 | Hitachi Ltd | 配線構造およびそれを有する半導体装置 |
JP2002075995A (ja) * | 2000-08-24 | 2002-03-15 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US6630741B1 (en) * | 2001-12-07 | 2003-10-07 | Advanced Micro Devices, Inc. | Method of reducing electromigration by ordering zinc-doping in an electroplated copper-zinc interconnect and a semiconductor device thereby formed |
JP2003257970A (ja) | 2002-02-27 | 2003-09-12 | Nec Electronics Corp | 半導体装置及びその配線構造 |
JP3973467B2 (ja) | 2002-03-20 | 2007-09-12 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP3623491B2 (ja) * | 2002-06-28 | 2005-02-23 | Necエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US7074709B2 (en) | 2002-06-28 | 2006-07-11 | Texas Instruments Incorporated | Localized doping and/or alloying of metallization for increased interconnect performance |
JP4555540B2 (ja) | 2002-07-08 | 2010-10-06 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
WO2004053971A1 (ja) * | 2002-12-09 | 2004-06-24 | Nec Corporation | 配線用銅合金、半導体装置、配線の形成方法及び半導体装置の製造方法 |
JP3959389B2 (ja) | 2003-01-07 | 2007-08-15 | 株式会社東芝 | 半導体装置 |
JP2004273523A (ja) * | 2003-03-05 | 2004-09-30 | Renesas Technology Corp | 配線接続構造 |
JP2004289008A (ja) | 2003-03-24 | 2004-10-14 | Renesas Technology Corp | 半導体集積回路装置およびその製造方法 |
WO2004088745A1 (ja) * | 2003-03-28 | 2004-10-14 | Fujitsu Limited | 半導体装置 |
US7101790B2 (en) * | 2003-03-28 | 2006-09-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming a robust copper interconnect by dilute metal doping |
JP2005038999A (ja) * | 2003-07-18 | 2005-02-10 | Sony Corp | 半導体装置の製造方法 |
US6979625B1 (en) * | 2003-11-12 | 2005-12-27 | Advanced Micro Devices, Inc. | Copper interconnects with metal capping layer and selective copper alloys |
JP2005197606A (ja) * | 2004-01-09 | 2005-07-21 | Toshiba Corp | 半導体装置およびその製造方法 |
US20050236181A1 (en) * | 2004-04-24 | 2005-10-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Novel ECP method for preventing the formation of voids and contamination in vias |
JP2006019708A (ja) * | 2004-06-04 | 2006-01-19 | Toshiba Corp | 半導体装置の製造方法及び半導体装置 |
US7223691B2 (en) * | 2004-10-14 | 2007-05-29 | International Business Machines Corporation | Method of forming low resistance and reliable via in inter-level dielectric interconnect |
US20060091551A1 (en) * | 2004-10-29 | 2006-05-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Differentially metal doped copper damascenes |
-
2005
- 2005-08-12 US US11/659,800 patent/US8004087B2/en not_active Expired - Fee Related
- 2005-08-12 JP JP2006531772A patent/JP4940950B2/ja not_active Expired - Fee Related
- 2005-08-12 WO PCT/JP2005/014855 patent/WO2006016678A1/ja active Application Filing
-
2011
- 2011-07-11 US US13/067,960 patent/US8916466B2/en active Active
-
2014
- 2014-11-24 US US14/551,505 patent/US9257390B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20110266678A1 (en) | 2011-11-03 |
US20150102492A1 (en) | 2015-04-16 |
US8004087B2 (en) | 2011-08-23 |
US8916466B2 (en) | 2014-12-23 |
US9257390B2 (en) | 2016-02-09 |
JPWO2006016678A1 (ja) | 2008-05-01 |
WO2006016678A1 (ja) | 2006-02-16 |
US20090026622A1 (en) | 2009-01-29 |
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