JP4852276B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4852276B2 JP4852276B2 JP2005232040A JP2005232040A JP4852276B2 JP 4852276 B2 JP4852276 B2 JP 4852276B2 JP 2005232040 A JP2005232040 A JP 2005232040A JP 2005232040 A JP2005232040 A JP 2005232040A JP 4852276 B2 JP4852276 B2 JP 4852276B2
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- die pad
- passive component
- insulating adhesive
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- semiconductor device
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/48195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Description
その後、封止樹脂30から図示しない突出したリードフレーム20のアウターリード部23の切断および曲げ金型等により成型加工して外部接続端子を形成する。
半導体チップ11は、複数の電極パッド12を有しており、受動部品15は対抗する端部に一対の電極端子16を有する。半導体チップ11の電極パッド12と、受動部品15の電極端子16とは、ボンディングワイヤ18により電気的に接続されている。
11:半導体チップ
12:電極パッド
15:受動部品
16:電極端子
18:ボンディングワイヤ
20:リードフレーム
21:ダイパッド
22:インナーリード
23:アウターリード
24:支持部
25:周辺フレーム部分
30:封止樹脂
32:接着剤
33:第1の絶縁性接着剤
34:第2の絶縁性接着剤
200:ノズル
Claims (4)
- 導体からなるダイパッドに半導体素子と受動部品とを搭載し、ボンディングワイヤにて前記受動部品と前記半導体素子とを接続してなる半導体装置の製造方法において、
前記ダイパッド上に接着剤を介して前記半導体素子を搭載する工程と、
前記ダイパッド上に第1のペースト状絶縁性接着剤を供給する工程と、
前記第1のペースト状絶縁性接着剤を前記ダイパッド上において略均一の厚さとする工程と、
前記第1のペースト状絶縁性接着剤を硬化する工程と、
前記第1のペースト状絶縁性接着剤上に第2のペースト状絶縁性接着剤を供給する工程と、
前記第2のペースト状絶縁性接着剤および前記第1のペースト状絶縁性接着剤を介して前記受動部品を加圧しながら前記ダイパッドに搭載する工程と、
前記第2のペースト状絶縁性接着剤を硬化させる工程と、
前記半導体素子と前記受動部品をボンディングワイヤにより接続する工程と、
前記半導体素子と前記受動部品と前記ボンディングワイヤを樹脂により一体的に封止する工程と
を含むことを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記接着剤が導電性接着剤であり、
前記ダイパッド上に第1のペースト状絶縁性接着剤を供給する工程が、該導電性接着剤を介して前記半導体素子を前記ダイパッドに接続搭載した後に行われることを特徴とする半導体装置の製造方法。 - 請求項1乃至2いずれかに記載の半導体装置の製造方法において、
前記第1のペースト状絶縁性接着剤と前記第2のペースト状絶縁性接着剤とが同一の材料からなることを特徴とする半導体装置の製造方法。 - 請求項1乃至3いずれかに記載の半導体装置の製造方法において、
前記接着剤が導電性接着剤であって、
前記第2のペースト状絶縁性接着剤を前記接着剤を被覆するように供給し、前記第2のペースト状絶縁性接着剤によって、前記半導体素子の外周部を前記ダイパッドに固着させる工程を含むことを特徴とする半導体装置の製造方法。
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JP2005232040A JP4852276B2 (ja) | 2005-08-10 | 2005-08-10 | 半導体装置の製造方法 |
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JP2005232040A JP4852276B2 (ja) | 2005-08-10 | 2005-08-10 | 半導体装置の製造方法 |
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JP2007048962A JP2007048962A (ja) | 2007-02-22 |
JP4852276B2 true JP4852276B2 (ja) | 2012-01-11 |
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Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
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KR101469975B1 (ko) * | 2008-01-22 | 2014-12-11 | 엘지이노텍 주식회사 | 멀티 칩 모듈 및 그 제조방법 |
JP6414602B2 (ja) * | 2014-11-12 | 2018-10-31 | 株式会社村田製作所 | 複合電子部品およびdcdcコンバータモジュール |
EP4021153A4 (en) * | 2019-08-23 | 2022-09-07 | Fuji Corporation | ELECTRONIC SWITCHING DEVICE AND ITS MANUFACTURING PROCESS |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2636776A1 (fr) * | 1988-09-16 | 1990-03-23 | Trt Telecom Radio Electr | Dispositif comportant un circuit electronique monte sur un support souple, protege contre les decharges d'electricite statique, et carte souple le comprenant |
JPH02111060A (ja) * | 1988-10-20 | 1990-04-24 | Toshiba Corp | 樹脂封止型半導体装置 |
JPH02158147A (ja) * | 1988-12-09 | 1990-06-18 | Fujitsu Ltd | 半導体装置 |
JP2004047811A (ja) * | 2002-07-12 | 2004-02-12 | Fujitsu Ltd | 受動素子内蔵半導体装置 |
JP4135101B2 (ja) * | 2004-06-18 | 2008-08-20 | サンケン電気株式会社 | 半導体装置 |
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