JP4850576B2 - 回路モジュールの製造方法、及びそれに使用される回路モジュール用の集合基板 - Google Patents
回路モジュールの製造方法、及びそれに使用される回路モジュール用の集合基板 Download PDFInfo
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- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/05573—Single external layer
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- H—ELECTRICITY
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
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- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
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- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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- Testing Of Individual Semiconductor Devices (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
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Description
また、このように構成した本発明は、バーンインテストを行うための引出パターンが回路基板間を繋ぐ連結部に形成できて、集合基板の小型化が図れ、安価なものが得られる。
また、このように構成した本発明は、第1,第2の繋ぎ部の存在によって、引出パターンの形成面積が大きくなって、多くの引出パターンの形成が容易にできる。
また、このように構成した本発明は、バーンインテスト用電極が第2の繋ぎ部に集中することによって、通電の容易なものが得られる。
1a 切断誘発部
2 回路基板
3 連結部
3a 第1の繋ぎ部
3b 第2の繋ぎ部
3c 凸部
4 回路パターン
4a 第1のランド部
4b 第2のランド部
4c パターン
5 延長パターン
6 引出パターン
6a 第1のパターン部
6b 第2のパターン部
7 バーンインテスト用電極
8 ベアチップ
8a 本体部
8b 電極
9 接続体
10 電子部品
K 境界位置
Claims (5)
- 複数の回路モジュールを形成するための回路パターンを有する複数の回路基板と、この複数の回路基板間を繋ぐ連結部を備えた集合基板を有すると共に、前記回路基板には、前記回路パターンに接続され、ベアチップを接続するための複数の第1のランド部、及び前記ベアチップ以外の電子部品を接続するための複数の第2のランド部を含み、前記第1のランド部に接続された状態で、前記回路基板と前記連結部の境界位置まで延びる複数の延長パターンとが設けられ、前記連結部には、前記延長パターンに接続された複数の引出パターンが設けられて構成された前記集合基板を備え、
前記連結部は、互いに隣り合う前記回路基板間に位置する第1の繋ぎ部と、外周部に位置する第2の繋ぎ部を有し、前記引出パターンが前記第1,第2の繋ぎ部に設けられ、
前記引出パターンの端部には、複数のバーンインテスト用電極が設けられ、複数の前記バーンインテスト用電極が前記外周部の一辺に位置する前記第2の繋ぎ部に集中して配置され、
前記引出パターンには、電源線、接地線、信号入力線や信号出力線があり、前記信号出力線は、前記個々のベアチップから引き出し、その他の電源線、接地線、信号入力線は、それぞれの前記ベアチップに対して共通化されており、
前記第1のランド部に前記ベアチップを接続する第1の接続工程と、高温状態で前記延長パターンと前記引出パターンを使用して前記ベアチップを通電動作させ、前記回路基板毎に接続された前記個々のベアチップ毎に良否を判別するバーンインテスト工程と、このバーンインテスト工程の後、良品の前記ベアチップを有した前記回路基板の前記第2のランド部に前記電子部品を接続する第2の接続工程とを有することを特徴とする回路モジュールの製造方法。 - 前記第2の接続工程が前記集合基板の状態で行われた後、前記境界位置で前記集合基板を切断する切断工程を行って、個々の前記回路基板を得るようにしたことを特徴とする請求項1記載の回路モジュールの製造方法。
- 前記バーンインテスト工程の後、前記境界位置で前記集合基板を切断して、個々の前記回路基板を得る切断工程を行い、しかる後、前記第2の接続工程を行うようにしたことを特徴とする請求項1記載の回路モジュールの製造方法。
- 回路モジュールを形成するための回路パターンを有する複数の回路基板と、この回路基板間を繋ぐ連結部を有すると共に、前記回路基板には、前記回路パターンに接続され、ベアチップを接続するための複数の第1のランド部、及び前記ベアチップ以外の電子部品を接続するための複数の第2のランド部を含み、前記第1のランド部に接続された状態で、前記回路基板と前記連結部の境界位置まで延びる複数の延長パターンとが設けられ、前記連結部には、前記延長パターンに接続された複数の引出パターンが設けられ、
前記連結部は、互いに隣り合う前記回路基板間に位置する第1の繋ぎ部と、外周部に位置する第2の繋ぎ部を有し、前記引出パターンが前記第1,第2の繋ぎ部に設けられ、
前記引出パターンの端部には、複数のバーンインテスト用電極が設けられ、複数の前記バーンインテスト用電極が前記外周部の一辺に位置する前記第2の繋ぎ部に集中して配置され、
前記引出パターンには、電源線、接地線、信号入力線や信号出力線があり、前記信号出力線は、前記個々のベアチップから引き出し、その他の電源線、接地線、信号入力線は、それぞれの前記ベアチップに対して共通化されていることを特徴とする回路モジュール用の集合基板。 - 前記引出パターンの端部には、複数のバーンインテスト用電極が設けられると共に、前記外周部の一辺に位置する前記第2の繋ぎ部には、外方に突出する凸部が設けられ、複数の前記バーンインテスト用電極が前記凸部に集中して配置されたことを特徴とする請求項4記載の回路モジュール用の集合基板。
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JP2006127778A JP4850576B2 (ja) | 2006-05-01 | 2006-05-01 | 回路モジュールの製造方法、及びそれに使用される回路モジュール用の集合基板 |
US11/789,162 US20070252607A1 (en) | 2006-05-01 | 2007-04-23 | Method of manufacturing circuit module, collective board for circuit module, and circuit module manufactured by the method |
KR1020070041818A KR100812307B1 (ko) | 2006-05-01 | 2007-04-30 | 회로모듈의 제조방법 및 그것에 사용되는 회로모듈용집합기판, 및 그 제조방법에 의하여 제조된 회로모듈 |
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JP2006127778A JP4850576B2 (ja) | 2006-05-01 | 2006-05-01 | 回路モジュールの製造方法、及びそれに使用される回路モジュール用の集合基板 |
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JP2007299995A JP2007299995A (ja) | 2007-11-15 |
JP4850576B2 true JP4850576B2 (ja) | 2012-01-11 |
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JP (1) | JP4850576B2 (ja) |
KR (1) | KR100812307B1 (ja) |
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JP5626567B2 (ja) * | 2010-08-06 | 2014-11-19 | 株式会社ジェイテクト | 素子実装基板の組み立て方法 |
KR102041501B1 (ko) * | 2013-09-13 | 2019-11-06 | 삼성전자 주식회사 | 연배열 인쇄회로기판, 그의 불량 단품 인쇄회로기판의 교체 방법 및 이를 이용한 전자 장치의 제조 방법 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5947793A (ja) * | 1982-09-10 | 1984-03-17 | 富士通株式会社 | 混成集積回路の製造方法 |
US4632485A (en) * | 1985-06-06 | 1986-12-30 | Brown Kenneth C | Electrical circuit testing apparatus |
JPS6442142A (en) * | 1987-08-10 | 1989-02-14 | Nec Corp | Burn-in test method for hybrid integrated circuit |
KR930010076B1 (ko) * | 1989-01-14 | 1993-10-14 | 티디케이 가부시키가이샤 | 다층혼성집적회로 |
JP3194483B2 (ja) * | 1991-11-08 | 2001-07-30 | 富士通株式会社 | バーンイン試験方法及びバーンイン試験装置 |
JPH05259589A (ja) * | 1992-03-16 | 1993-10-08 | Fuji Electric Co Ltd | 多面取りプリント基板 |
JPH06174786A (ja) * | 1992-12-09 | 1994-06-24 | Mitsubishi Electric Corp | バーンインボード |
JPH1022596A (ja) * | 1996-07-01 | 1998-01-23 | Hitachi Ltd | 回路基板 |
KR100244181B1 (ko) * | 1996-07-11 | 2000-02-01 | 구본준 | 액정표시장치의리페어구조및그를이용한리페어방법 |
JPH1065301A (ja) * | 1996-08-23 | 1998-03-06 | Yokogawa Electric Corp | チェック用配線パターン付きプリント基板 |
JPH10233561A (ja) * | 1997-02-19 | 1998-09-02 | Alps Electric Co Ltd | 分割基板及びその分割基板を用いた電子機器の製造方法 |
US6038133A (en) * | 1997-11-25 | 2000-03-14 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module and method for producing the same |
US6329832B1 (en) * | 1998-10-05 | 2001-12-11 | Micron Technology, Inc. | Method for in-line testing of flip-chip semiconductor assemblies |
KR100797422B1 (ko) * | 2000-09-25 | 2008-01-23 | 이비덴 가부시키가이샤 | 반도체소자, 반도체소자의 제조방법, 다층프린트배선판 및다층프린트배선판의 제조방법 |
EP1293789A1 (de) * | 2001-09-12 | 2003-03-19 | Alcatel | Verfahren zum Testen und Inbetriebnehmen einer elektrischen Schaltungseinheit sowie solche Schaltunseinheiten |
JP4398626B2 (ja) * | 2002-03-26 | 2010-01-13 | パナソニック株式会社 | 積層回路 |
JP2004022977A (ja) * | 2002-06-19 | 2004-01-22 | Murata Mfg Co Ltd | 集合基板および電子部品の製造方法 |
CN2594855Y (zh) * | 2002-09-27 | 2003-12-24 | 威达电股份有限公司 | 具有绘图加速端口的计算机底板 |
JP2005072361A (ja) * | 2003-08-26 | 2005-03-17 | Hitachi Kokusai Electric Inc | 面付け基板の分割方法 |
JP2005317861A (ja) * | 2004-04-30 | 2005-11-10 | Toshiba Corp | 半導体装置およびその製造方法 |
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2006
- 2006-05-01 JP JP2006127778A patent/JP4850576B2/ja not_active Expired - Fee Related
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2007
- 2007-04-23 US US11/789,162 patent/US20070252607A1/en not_active Abandoned
- 2007-04-30 KR KR1020070041818A patent/KR100812307B1/ko not_active IP Right Cessation
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KR100812307B1 (ko) | 2008-03-10 |
US20070252607A1 (en) | 2007-11-01 |
JP2007299995A (ja) | 2007-11-15 |
KR20070106927A (ko) | 2007-11-06 |
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