JP4825832B2 - 印刷回路基板の製造方法 - Google Patents
印刷回路基板の製造方法 Download PDFInfo
- Publication number
- JP4825832B2 JP4825832B2 JP2008067433A JP2008067433A JP4825832B2 JP 4825832 B2 JP4825832 B2 JP 4825832B2 JP 2008067433 A JP2008067433 A JP 2008067433A JP 2008067433 A JP2008067433 A JP 2008067433A JP 4825832 B2 JP4825832 B2 JP 4825832B2
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- Prior art keywords
- circuit pattern
- metal layer
- forming
- insulating layer
- conductive
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0147—Carriers and holders
- H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0376—Etching temporary metallic carrier substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0384—Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49121—Beam lead frame or beam lead device
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
302 金属層
304 感光材
306 第1回路パターン
308 ペーストバンプ
310 第1絶縁層
312 ビア
314 第2絶縁層
316 導電層
600 離型材
Claims (6)
- 一面に金属層が積層され、前記金属層と異なるエッチング液に反応し、接着剤が塗布された離型材の両面に各々接着される一対の導電性キャリアの前記金属層に第1回路パターンを形成するステップと、
前記一対の導電性キャリアを分離するステップと、
前記第1回路パターンの所定の位置にペーストバンプを形成するステップと、
前記第1回路パターンが第1絶縁層に向かい、前記ペーストバンプが突出するように一対の前記導電性キャリアの間に前記第1絶縁層を介在して圧着するステップと、
前記導電性キャリアを選択的に除去してビアを形成するステップと、
前記金属層に対応するエッチング液を塗布して前記金属層を除去するステップと、を含み、
前記ビアを形成するステップが
前記ビアの位置に対応するエッチングレジストを形成するステップと、
前記導電性キャリアに対応するエッチング液を塗布するステップと、を含み、
前記第1回路パターンを形成するステップは、
前記一対の導電性キャリアの前記金属層に前記第1回路パターンに対応するメッキレジ
ストを形成するステップと、
前記金属層を電極にして電解メッキするステップと、
を含むことを特徴とする印刷回路基板の製造方法。 - 前記第1回路パターンを形成するステップは、
前記金属層に前記第1回路パターンに対応するメッキレジストを形成するステップと、
前記金属層を電極にして電解メッキするステップと、
を含むことを特徴とする請求項1に記載の印刷回路基板の製造方法。 - 前記金属層は、ニッケル(Ni)を含むことを特徴とする請求項1または請求項2に記載の印刷回路基板の製造方法。
- 前記金属層を除去するステップ以後に、
前記ビアが貫通するように第2絶縁層を圧着するステップと、
前記第2絶縁層上に第2回路パターンを形成するステップと、
をさらに含むことを特徴とする請求項1から請求項3までの何れか1項に記載の印刷回路基板の製造方法。 - 前記第2絶縁層は外面に導電層をさらに含み、
前記圧着するステップは、
前記ビアが前記第2絶縁層を貫通して前記導電層と電気的に接続するように圧着するステップと、を含み、
前記第2回路パターンを形成するステップ以後に、
前記第2回路パターンを加圧して前記第2絶縁層に圧入するステップをさらに含むことを特徴とする請求項4に記載の印刷回路基板の製造方法。 - 前記第2回路パターンを形成するステップは、
前記第2絶縁層上に前記第2回路パターンに対応するメッキレジストを形成するステップと、
前記第2絶縁層をメッキするステップと、
を含むことを特徴とする請求項4に記載の印刷回路基板の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070069280A KR100872131B1 (ko) | 2007-07-10 | 2007-07-10 | 인쇄회로기판 제조방법 |
KR10-2007-0069280 | 2007-07-10 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009021545A JP2009021545A (ja) | 2009-01-29 |
JP4825832B2 true JP4825832B2 (ja) | 2011-11-30 |
Family
ID=40251923
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008067433A Expired - Fee Related JP4825832B2 (ja) | 2007-07-10 | 2008-03-17 | 印刷回路基板の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7836590B2 (ja) |
JP (1) | JP4825832B2 (ja) |
KR (1) | KR100872131B1 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100841987B1 (ko) * | 2007-07-10 | 2008-06-27 | 삼성전기주식회사 | 다층 인쇄회로기판 제조방법 |
TWI347807B (en) * | 2008-05-13 | 2011-08-21 | Unimicron Technology Corp | Electrically interconnect structure and process thereof and circuit board structure |
KR100990576B1 (ko) * | 2008-05-26 | 2010-10-29 | 삼성전기주식회사 | 미세 최외층 회로패턴을 갖는 인쇄회로기판 및 그 제조방법 |
KR101021344B1 (ko) | 2009-10-19 | 2011-03-14 | (주)인터플렉스 | 연성인쇄회로기판의 제조방법 |
KR101047139B1 (ko) * | 2009-11-11 | 2011-07-07 | 삼성전기주식회사 | 단층 보드온칩 패키지 기판 및 그 제조방법 |
KR101088062B1 (ko) * | 2009-12-23 | 2011-11-30 | 엘지이노텍 주식회사 | 범프를 구비한 스택형 인쇄회로기판 및 제조방법 |
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ATE86797T1 (de) * | 1988-12-16 | 1993-03-15 | Siemens Ag | Verfahren zur selbstjustierten herstellung von kontakten zwischen in uebereinander angeordneten verdrahtungsebenen einer integrierten schaltung enthaltenen leiterbahnen. |
US5121299A (en) * | 1989-12-29 | 1992-06-09 | International Business Machines Corporation | Multi-level circuit structure utilizing conductive cores having conductive protrusions and cavities therein |
US5209817A (en) * | 1991-08-22 | 1993-05-11 | International Business Machines Corporation | Selective plating method for forming integral via and wiring layers |
JP2658661B2 (ja) * | 1991-09-18 | 1997-09-30 | 日本電気株式会社 | 多層印刷配線板の製造方法 |
US5480048A (en) * | 1992-09-04 | 1996-01-02 | Hitachi, Ltd. | Multilayer wiring board fabricating method |
JPH08139450A (ja) * | 1994-11-07 | 1996-05-31 | Toshiba Corp | 印刷配線板の製造方法 |
JPH08264939A (ja) * | 1995-03-28 | 1996-10-11 | Toshiba Corp | 印刷配線板の製造方法 |
US6168725B1 (en) * | 1997-12-22 | 2001-01-02 | Visteon Global Technologies, Inc. | Etching of Al-Cu layers to form electronic circuits using base solutions including nitrites, borates or bromates |
JP3554171B2 (ja) * | 1998-01-23 | 2004-08-18 | 京セラ株式会社 | 回路基板の製造方法 |
US6815709B2 (en) * | 2001-05-23 | 2004-11-09 | International Business Machines Corporation | Structure having flush circuitry features and method of making |
KR20030071391A (ko) | 2002-02-28 | 2003-09-03 | 삼성전기주식회사 | 범프의 형성방법 및 이로부터 형성된 범프를 이용한인쇄회로기판의 제조방법 |
JP2004140085A (ja) | 2002-10-16 | 2004-05-13 | Shinko Electric Ind Co Ltd | 回路基板及びその製造方法 |
JP4283609B2 (ja) | 2003-07-15 | 2009-06-24 | テセラ・インターコネクト・マテリアルズ,インコーポレイテッド | 配線回路基板の製造方法、配線回路基板および多層配線基板の製造方法 |
JP4398683B2 (ja) * | 2003-08-11 | 2010-01-13 | テセラ・インターコネクト・マテリアルズ,インコーポレイテッド | 多層配線基板の製造方法 |
DE102004005300A1 (de) | 2004-01-29 | 2005-09-08 | Atotech Deutschland Gmbh | Verfahren zum Behandeln von Trägermaterial zur Herstellung von Schltungsträgern und Anwendung des Verfahrens |
KR100688823B1 (ko) | 2004-07-21 | 2007-03-02 | 삼성전기주식회사 | 고밀도 기판의 제조방법 |
JP4597631B2 (ja) * | 2004-10-13 | 2010-12-15 | 大日本印刷株式会社 | 部品内蔵配線板、部品内蔵配線板の製造方法 |
JP2007150171A (ja) * | 2005-11-30 | 2007-06-14 | Kyocer Slc Technologies Corp | 配線基板の製造方法 |
-
2007
- 2007-07-10 KR KR1020070069280A patent/KR100872131B1/ko active IP Right Grant
-
2008
- 2008-02-01 US US12/068,124 patent/US7836590B2/en not_active Expired - Fee Related
- 2008-03-17 JP JP2008067433A patent/JP4825832B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2009021545A (ja) | 2009-01-29 |
US7836590B2 (en) | 2010-11-23 |
KR100872131B1 (ko) | 2008-12-08 |
US20090013525A1 (en) | 2009-01-15 |
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