JP4750865B2 - デ―タ・プロセッサにおいて後続の命令処理に影響を及ぼす方法および装置 - Google Patents
デ―タ・プロセッサにおいて後続の命令処理に影響を及ぼす方法および装置 Download PDFInfo
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- JP4750865B2 JP4750865B2 JP2009035190A JP2009035190A JP4750865B2 JP 4750865 B2 JP4750865 B2 JP 4750865B2 JP 2009035190 A JP2009035190 A JP 2009035190A JP 2009035190 A JP2009035190 A JP 2009035190A JP 4750865 B2 JP4750865 B2 JP 4750865B2
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- interrupt
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- data processor
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- 238000012545 processing Methods 0.000 title claims description 16
- 238000000034 method Methods 0.000 title claims description 15
- 230000006870 function Effects 0.000 description 20
- 239000004020 conductor Substances 0.000 description 9
- 230000001934 delay Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 5
- 238000007689 inspection Methods 0.000 description 5
- 230000003111 delayed effect Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30094—Condition code generation, e.g. Carry, Zero flag
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30079—Pipeline control instructions, e.g. multicycle NOP
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30087—Synchronisation or serialisation instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
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- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
- Debugging And Monitoring (AREA)
Description
図4は、図3の割り込み認識遅延命令を用いて検査およびセット機能を実行する際に使用可能な一連の命令の一実施例を示す。
図6は、図3の割り込み認識遅延命令を用いてメモリ型カウンタ増分機能(memory−based counter function)を実行する際に使用可能な一連の命令の一実施例を示す。
12 中央演算装置(CPU)
14 メモリ
16 バス・インターフェース・モジュール
18 その他のモジュール
20 バス
22,24,28 集積回路端子
26 外部バス
30 命令パイプ回路
32 命令デコード回路
34,36 レジスタ
38 条件ビット
40 算術演算論理ユニット(ALU)
42 CPU制御回路
44 例外制御回路
46 割り込み制御回路
47 オーバーライド回路
48 カウンタ/タイマ回路
50 割り込み信号
52 例外信号
54,56,60,62,64 導体
58 制御/ステータス信号
70 指定フィールド
R1,R3 レジスタ
Claims (3)
- データ・プロセッサにおいて後続の命令処理に影響を及ぼす方法であって、
第1の命令を提供すること、
第2の命令を提供することであって、前記第1の命令の実行の完了後に前記第2の命令が実行される場合、前記第2の命令は第1の動作を行い、前記第2の命令の実行が始まる前に前記第1の命令の実行が完了していない場合、前記第2の命令は前記第1の動作とは異なる第2の動作を行なう、第2の命令を提供すること、
を備え、前記第1の命令と第2の命令とは同一の命令であり、前記第1の動作は、割り込み認識を、制御期間中に選択的に遅延させることを含み、前記第2の動作は、無動作命令の実行に対応するものである、方法。 - 前記第2の命令の前記第1の動作は、前記データ・プロセッサによる例外の遅延処理を含む、請求項1に記載の方法。
- データ・プロセッサであって、
第1の命令及び第2の命令を実行する命令実行回路であって、前記第1の命令の実行の完了後に第2の命令が実行される場合、前記第2の命令は第1の動作を行い、前記第2の命令の実行開始前に前記第1の命令の実行が完了していない場合、前記第2の命令は、前記第1の動作とは異なる第2の動作を行なう、前記命令実行回路と、
前記データ・プロセッサ内の所定の状態を示すフラグと
を備え、前記第1の命令と第2の命令とは同一の命令であり、前記第1の動作はフラグを所定の第1の状態にすること含み、前記第2の動作は、前記フラグの状態に影響を及ぼさない無動作命令の実行に対応するものである、データ・プロセッサ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/963,321 US6000029A (en) | 1997-11-03 | 1997-11-03 | Method and apparatus for affecting subsequent instruction processing in a data processor |
US963321 | 1997-11-03 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP31026898A Division JP4883824B2 (ja) | 1997-11-03 | 1998-10-30 | デ―タ・プロセッサにおいて後続の命令処理に影響を及ぼす方法および装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009104675A JP2009104675A (ja) | 2009-05-14 |
JP4750865B2 true JP4750865B2 (ja) | 2011-08-17 |
Family
ID=25507071
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP31026898A Expired - Fee Related JP4883824B2 (ja) | 1997-11-03 | 1998-10-30 | デ―タ・プロセッサにおいて後続の命令処理に影響を及ぼす方法および装置 |
JP2009035190A Expired - Fee Related JP4750865B2 (ja) | 1997-11-03 | 2009-02-18 | デ―タ・プロセッサにおいて後続の命令処理に影響を及ぼす方法および装置 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP31026898A Expired - Fee Related JP4883824B2 (ja) | 1997-11-03 | 1998-10-30 | デ―タ・プロセッサにおいて後続の命令処理に影響を及ぼす方法および装置 |
Country Status (9)
Country | Link |
---|---|
US (2) | US6000029A (ja) |
EP (1) | EP0913767B1 (ja) |
JP (2) | JP4883824B2 (ja) |
KR (1) | KR100588790B1 (ja) |
CN (1) | CN1098487C (ja) |
DE (1) | DE69810064T2 (ja) |
HK (1) | HK1020218A1 (ja) |
SG (2) | SG71861A1 (ja) |
TW (1) | TW494363B (ja) |
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US6857036B2 (en) * | 2001-07-17 | 2005-02-15 | Hewlett Packard Development Company, L.P. | Hardware method for implementing atomic semaphore operations using code macros |
US20030154347A1 (en) * | 2002-02-12 | 2003-08-14 | Wei Ma | Methods and apparatus for reducing processor power consumption |
US7529367B2 (en) | 2003-04-18 | 2009-05-05 | Via Technologies, Inc. | Apparatus and method for performing transparent cipher feedback mode cryptographic functions |
US7542566B2 (en) | 2003-04-18 | 2009-06-02 | Ip-First, Llc | Apparatus and method for performing transparent cipher block chaining mode cryptographic functions |
US7539876B2 (en) | 2003-04-18 | 2009-05-26 | Via Technologies, Inc. | Apparatus and method for generating a cryptographic key schedule in a microprocessor |
US7925891B2 (en) | 2003-04-18 | 2011-04-12 | Via Technologies, Inc. | Apparatus and method for employing cryptographic functions to generate a message digest |
US7529368B2 (en) | 2003-04-18 | 2009-05-05 | Via Technologies, Inc. | Apparatus and method for performing transparent output feedback mode cryptographic functions |
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US7900055B2 (en) | 2003-04-18 | 2011-03-01 | Via Technologies, Inc. | Microprocessor apparatus and method for employing configurable block cipher cryptographic algorithms |
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US9740549B2 (en) | 2012-06-15 | 2017-08-22 | International Business Machines Corporation | Facilitating transaction completion subsequent to repeated aborts of the transaction |
US8966324B2 (en) | 2012-06-15 | 2015-02-24 | International Business Machines Corporation | Transactional execution branch indications |
US9384004B2 (en) | 2012-06-15 | 2016-07-05 | International Business Machines Corporation | Randomized testing within transactional execution |
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-
1997
- 1997-11-03 US US08/963,321 patent/US6000029A/en not_active Expired - Lifetime
-
1998
- 1998-10-14 TW TW087117065A patent/TW494363B/zh not_active IP Right Cessation
- 1998-10-26 DE DE69810064T patent/DE69810064T2/de not_active Expired - Fee Related
- 1998-10-26 EP EP98120220A patent/EP0913767B1/en not_active Expired - Lifetime
- 1998-10-30 JP JP31026898A patent/JP4883824B2/ja not_active Expired - Fee Related
- 1998-10-30 SG SG1998004357A patent/SG71861A1/en unknown
- 1998-10-30 SG SG200106112A patent/SG101487A1/en unknown
- 1998-11-02 CN CN98121455A patent/CN1098487C/zh not_active Expired - Lifetime
- 1998-11-03 KR KR1019980046900A patent/KR100588790B1/ko not_active IP Right Cessation
-
1999
- 1999-10-22 US US09/425,469 patent/US6237089B1/en not_active Expired - Lifetime
- 1999-11-12 HK HK99105223A patent/HK1020218A1/xx not_active IP Right Cessation
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2009
- 2009-02-18 JP JP2009035190A patent/JP4750865B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0913767A3 (en) | 2000-01-26 |
US6237089B1 (en) | 2001-05-22 |
JP2009104675A (ja) | 2009-05-14 |
HK1020218A1 (en) | 2000-03-31 |
KR100588790B1 (ko) | 2006-10-04 |
SG101487A1 (en) | 2004-01-30 |
DE69810064T2 (de) | 2003-04-17 |
JPH11219302A (ja) | 1999-08-10 |
CN1098487C (zh) | 2003-01-08 |
EP0913767A2 (en) | 1999-05-06 |
EP0913767B1 (en) | 2002-12-11 |
TW494363B (en) | 2002-07-11 |
US6000029A (en) | 1999-12-07 |
SG71861A1 (en) | 2000-04-18 |
DE69810064D1 (de) | 2003-01-23 |
KR19990044957A (ko) | 1999-06-25 |
CN1216375A (zh) | 1999-05-12 |
JP4883824B2 (ja) | 2012-02-22 |
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