JP4742731B2 - 積層型半導体装置の製造方法 - Google Patents
積層型半導体装置の製造方法 Download PDFInfo
- Publication number
- JP4742731B2 JP4742731B2 JP2005226179A JP2005226179A JP4742731B2 JP 4742731 B2 JP4742731 B2 JP 4742731B2 JP 2005226179 A JP2005226179 A JP 2005226179A JP 2005226179 A JP2005226179 A JP 2005226179A JP 4742731 B2 JP4742731 B2 JP 4742731B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- circuit board
- semiconductor
- liquid resin
- semiconductor chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
Claims (2)
- バンプが一主面側に設けられている複数の半導体チップを、フリップチップ接続によって回路基板上に積層して搭載する搭載工程と、
前記搭載工程で前記回路基板上に搭載された前記複数の半導体チップの間の間隙、および、前記複数の半導体チップのうち前記回路基板の直上に設けられた最下部の半導体チップと前記回路基板の間の間隙に、液状樹脂を注入して充填する液状樹脂充填工程と
を有し、
前記搭載工程の実施前に、
前記複数の半導体チップのそれぞれに貫通孔を形成する貫通孔形成工程と、
前記複数の半導体チップの一主面の周縁部に封止材を形成する封止材形成工程と
を実施し、
前記搭載工程では、前記複数の半導体チップの間の間隙、および、前記最下部の半導体チップと前記回路基板との間の間隙が、前記複数の半導体チップのそれぞれに設けられた前記貫通孔で連通された状態になるように、前記複数の半導体チップのそれぞれを、前記回路基板上に順次搭載し、前記封止材で互いを接合し、
前記液状樹脂充填工程では、前記搭載工程で前記回路基板上に搭載された前記複数の半導体チップのうち前記回路基板から最も離れた最上層の半導体チップに設けられた貫通孔から、前記液状樹脂を注入する、
積層型半導体装置の製造方法。 - 前記貫通孔形成工程では、前記複数の半導体チップの一主面の周縁部において前記バンプが設けられる部分よりも外側の部分に、前記貫通孔を形成し、
前記封止材形成工程では、前記複数の半導体チップの一主面の周縁部において、前記貫通孔が形成される部分よりも外側の部分に、前記封止材を形成する、
請求項1に記載の積層型半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005226179A JP4742731B2 (ja) | 2005-08-04 | 2005-08-04 | 積層型半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005226179A JP4742731B2 (ja) | 2005-08-04 | 2005-08-04 | 積層型半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007042904A JP2007042904A (ja) | 2007-02-15 |
JP4742731B2 true JP4742731B2 (ja) | 2011-08-10 |
Family
ID=37800601
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005226179A Expired - Fee Related JP4742731B2 (ja) | 2005-08-04 | 2005-08-04 | 積層型半導体装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4742731B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI492339B (zh) | 2009-06-01 | 2015-07-11 | Shinetsu Chemical Co | A dam material composition for a bottom layer filler material for a multilayer semiconductor device, and a manufacturing method of a multilayer semiconductor device using the dam material composition |
JP2013182973A (ja) * | 2012-03-01 | 2013-09-12 | Tokyo Electron Ltd | 基板の接合方法及び半導体装置 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3475575B2 (ja) * | 1995-06-08 | 2003-12-08 | 富士通テン株式会社 | 半導体チップの封止方法及び封止構造 |
JPH10270477A (ja) * | 1997-03-27 | 1998-10-09 | Hitachi Ltd | 半導体パッケージ製造方法 |
JP2000260912A (ja) * | 1999-03-05 | 2000-09-22 | Fujitsu Ltd | 半導体装置の実装構造及び半導体装置の実装方法 |
JP4019985B2 (ja) * | 2003-03-19 | 2007-12-12 | セイコーエプソン株式会社 | 半導体装置の製造方法、回路基板、及び電子機器 |
-
2005
- 2005-08-04 JP JP2005226179A patent/JP4742731B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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JP2007042904A (ja) | 2007-02-15 |
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