JP4734282B2 - 半導体チップおよび半導体装置 - Google Patents
半導体チップおよび半導体装置 Download PDFInfo
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- JP4734282B2 JP4734282B2 JP2007112574A JP2007112574A JP4734282B2 JP 4734282 B2 JP4734282 B2 JP 4734282B2 JP 2007112574 A JP2007112574 A JP 2007112574A JP 2007112574 A JP2007112574 A JP 2007112574A JP 4734282 B2 JP4734282 B2 JP 4734282B2
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- electrodes
- power supply
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- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
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- H01L2924/3025—Electromagnetic shielding
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/903—FET configuration adapted for use as static memory cell
- Y10S257/904—FET configuration adapted for use as static memory cell with passive components,, e.g. polysilicon resistors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/924—Active solid-state devices, e.g. transistors, solid-state diodes with passive device, e.g. capacitor, or battery, as integral part of housing or housing element, e.g. cap
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
V=L(dI/dt) (数1)
となる。
L=φ/I (数2)
(数2)のように電流(I)と空間に蓄えられる磁束(φ)の比例係数として定義される。
L01〜L02<L1〜L2<L7〜L8 (数3)
(数3)のような関係を持つこととなる。
C01<C02<C04 (数4)
(数4)の大小関係を持つ。
共振周波数[ラジアン](ω0)=1/√(L・C) (数5)
時間遅れ[秒]Td=√(L・C)=1/ω0 (数6)
の関係がある。
Q=(ω0・L)/R (数7)
(数7)のようになる。
本発明の第1の実施の形態を、図1〜図6を用いて説明する。
本発明の第2の実施の形態を、図7を用いて説明する。
本発明の第3の実施の形態を、図8を用いて説明する。
本発明の第4の実施の形態を、図9〜図11を用いて説明する。
ω280<ω211<ω203<ω204 (数8)
の条件が望ましく、それぞれ1桁以上の周波数がずれているのが望ましい。これにより、半導体チップ20の負荷変動に対してどの周波数帯においてもノイズ最小となるようにバランスの取れた給電系を実現できる。このためにも、各電流ループでのインダクタンス、抵抗値の設計が重要であり、特にボンディングワイヤ81,82では長さを変えることで調整が簡単であり、設計が容易である。
本発明の第5の実施の形態を、図12〜図15を用いて説明する。
本発明の第6の実施の形態を、図16を用いて説明する。
300…情報処理システム、310…記憶装置、320…アンテナ、340…表示デバイス、350…入力デバイス、360…電源回路。
Claims (4)
- 情報処理機能を構成する回路と電極とを有する半導体チップであって、
前記半導体チップの表面に前記回路の多層の配線パターンが形成され、
前記半導体チップの表面の前記回路の所定の層に複数の電極である第一の複数の電極が形成され、
前記半導体チップの裏面に複数の電極である第二の複数の電極が形成され、
前記第一の複数の電極の各々と、前記第二の複数の電極の各々とは、前記半導体チップの内部に設けられた複数のビアホールのうちいずれか一のビアホールを介して電気的に接続され、
前記第二の複数の電極上に高誘電体絶縁層を有する複数のコンデンサが接続され、前記複数のコンデンサの各コンデンサの端子に異種の電源電圧が印加されるように、前記各コンデンサに対して前記第二の複数の電極のうちの任意の2つの電極がそれぞれ接続され、
前記第二の複数の電極は電源用電極とグランド用電極とがあり、前記複数のコンデンサに印加される電源電圧が異種となるように前記電源用電極と前記グランド用電極とが交互に配置されており、
前記複数のビアホールは前記電源用電極と接続される電源用ビアホールと前記グランド用電極と接続されるグランド用ビアホールとがあり、前記複数のコンデンサのうち隣接するコンデンサを流れる電流が逆向きになるように、前記電源用電極と前記グランド用電極とが交互に配置されており、
前記第二の複数の電極は4個以上の偶数個設けられており、
前記回路は電源種の異なる複数の機能ブロックを持ち、
前記半導体チップの表面の第1の領域である第1の機能ブロックには、前記第1の機能ブロックの領域に対応する前記半導体チップの裏面の領域に配置された前記第二の複数の電極と電気的に接続された第1の電源電極が形成され、
前記半導体チップの表面の第2の領域である第2の機能ブロックには、前記第2の機能ブロックの領域に対応する前記半導体チップの裏面の領域に配置された前記第二の複数の電極と電気的に接続された第2の電源電極が形成され、
前記第1の電源電極と前記第二の複数の電極とは前記複数のビアホールのうちいずれか一のビアホールを経由して電気的に接続され、
前記第2の電源電極と前記第二の複数の電極とは前記複数のビアホールのうちいずれか一のビアホールを経由して電気的に接続され、
前記第二の複数の電極のうち、前記第1の電源電極に接続された電極と、前記第2の電源電極に接続された電極とが、前記半導体チップの裏面では電気的に絶縁されるように配線されていることを特徴とする半導体チップ。 - 請求項1記載の半導体チップにおいて、
前記第二の複数の電極のグランド用電極のうち、前記第1の機能ブロックの領域に配置された前記第1の電源電極と電気的に接続されるグランド用電極と、前記第2の機能ブロックの領域に配置された前記第2の電源電極と電気的に接続されるグランド用電極とが、電気的に短絡されるように配線されていることを特徴とする半導体チップ。 - 請求項1記載の半導体チップにおいて、
前記第二の複数の電極に接続された電源用電極に、高誘電体絶縁層を有するコンデンサと抵抗器が接続されてローパスフィルタが構成されていることを特徴とする半導体チップ。 - 請求項1〜3のいずれか1項記載の半導体チップと、前記半導体チップを搭載する半導体インターポーザを有する半導体装置であって、
前記半導体チップの表面に設けられた信号電極は、前記半導体インターポーザに形成された信号電極に半田で接続され、
前記第一の複数の電極は、前記半導体インターポーザに形成された電源電極に半田で接続されていることを特徴とする半導体装置。
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JP2007112574A JP4734282B2 (ja) | 2007-04-23 | 2007-04-23 | 半導体チップおよび半導体装置 |
US12/107,758 US8049303B2 (en) | 2007-04-23 | 2008-04-22 | Semiconductor device with power noise suppression |
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