JP4731794B2 - メモリ効果を有するスイッチ素子及び該素子をスイッチングさせる方法 - Google Patents
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Description
Claims (30)
- 第1及び第2電極と、
前記第1及び第2電極の間に設けられて前記第1及び第2電極を電気的に接続可能であり、Naイオン及びClイオンを含む複数のイオン錯体が内部に分布する分子系を備え、オン状態とオフ状態とを選択的に取り得るように構成される活性領域と、
前記活性領域に印加されて前記活性領域を前記オン状態と前記オフ状態とで切り替える電界を制御するために所定の電圧が印加される制御電極と、を備えており、
前記活性領域は、前記オフ状態と前記オン状態との間で切り替えを行うために前記制御電極に印加されるしきい値電圧が相対的に高い第1動作モード及び前記しきい値電圧が相対的に低い第2動作モードを提供するように構成されており、前記第1動作モードにおけるオン状態とオフ状態との間の切り替え時間は、前記第2動作モードにおけるオン状態とオフ状態との間の切り替え時間よりも長い、
スイッチ素子。 - 前記活性領域は、前記制御電極と前記第1及び第2電極との間に第1極性を持つ電圧が印加されると、前記オフ状態から前記オン状態に切り替わるように構成される
請求項1記載のスイッチ素子。 - 前記活性領域は、前記制御電極と前記第1及び第2電極との間に、前記第1極性とは逆の極性の第2極性を持つ電圧が印加されると、前記オン状態から前記オフ状態に切り替わるように構成される
請求項2記載のスイッチ素子。 - 前記活性領域は、前記オン状態において前記第1及び第2電極の間に導電チャネルが形成される
請求項1記載のスイッチ素子。 - 前記活性領域は、前記第1動作モードにおけるオン状態のインピーダンスが前記第2動作モードにおけるオン状態のインピーダンスよりも低くなるように構成される
請求項1記載のスイッチ素子。 - 前記第1動作モードにおいて前記活性領域を切り替えるために要する電界強度が、前記第2動作モードにおけるそれよりも高い
請求項1記載のスイッチ素子。 - 前記分子系は、準一次元分子マトリクスを含んで構成される
請求項1記載のスイッチ素子。 - 前記分子系は、構造的及び電気的に異方性の分子マトリクスを含んで構成される
請求項1記載のスイッチ素子。 - 前記分子系は、重共役化合物を含んで構成される
請求項1記載のスイッチ素子。 - 前記分子系は、芳香族分子を含んで構成される
請求項1記載のスイッチ素子。 - 前記分子系は、複素環分子を含んで構成される
請求項1記載のスイッチ素子。 - 前記分子系は、ポルフィリンを含んで構成される
請求項1記載のスイッチ素子。 - 前記分子系は、フタロシアニンを含んで構成される
請求項1記載のスイッチ素子。 - 前記分子系は、準一次元構造を持つ無機化合物を含んで構成される
請求項1記載のスイッチ素子。 - 前記制御電極に隣接して絶縁層をさらに備える
請求項1記載のスイッチ素子。 - 前記絶縁層は、前記制御電極と前記活性領域との間に挟まれて形成される
請求項15記載のスイッチ素子。 - 基板をさらに含んで構成される
請求項16記載のスイッチ素子。 - 前記第1及び第2電極は、前記基板に設けられる
請求項17記載のスイッチ素子。 - 前記活性領域は、前記第1及び第2電極に電気的に接触されるように、前記基板上に形成される
請求項18記載のスイッチ素子。 - 前記絶縁層は、前記制御電極と前記第1電極との間に挟まれて形成される
請求項15記載のスイッチ素子。 - 前記活性領域は、前記第1電極と前記第2電極との間に挟まれて形成される
請求項20記載のスイッチ素子。 - ゲート端子と、
少なくとも2つの信号端子と、
前記ゲート端子と一方の信号端子との間に設けられる絶縁体と、
前記2つの信号端子にその表面及び裏面がそれぞれ電気的に接続されており、前記ゲート端子と他方の信号端子に印加される電圧信号によりその内部に印加される電界に応答してオン状態とオフ状態とが切り替わり、内部にNaイオン及びClイオンを含む複数のイオン錯体を有する分子系を備える能動素子と、により構成されており、
前記オフ状態と前記オン状態との間で切り替えを行うために前記ゲート端子に印加されるしきい値電圧が相対的に高い第1切替モード及び前記しきい値電圧が相対的に低い第2切替モードを有し、前記第1切替モードで前記能動素子に印加されて前記メモリスイッチを切り替える電界強度は、前記第2切替モードにおけるそれよりも高く、前記第1切替モードにおける切り替え時間が、前記第2切替モードにおけるそれよりも長い、
メモリスイッチ。 - 前記能動素子は、オン状態のときのインピーダンスがオフ状態のときのインピーダンスよりも低くなるように構成される、
請求項22記載のメモリスイッチ。 - 前記能動素子は、印加される電界の強度がしきい値を超えると、前記オン状態と前記オフ状態とが切り替わるように構成される
請求項23記載のメモリスイッチ。 - 前記能動素子は、電界が第1極性をもつときに、前記オフ状態から前記オン状態に切り替わるように構成される
請求項24記載のメモリスイッチ。 - 前記能動素子は、電界が前記第1極性とは逆の極性の第2極性を持つときに、前記オン状態から前記オフ状態に切り替わるように構成される
請求項25記載のメモリスイッチ。 - 前記能動素子に印加される電界は、前記メモリスイッチのアドレス指定を行う
請求項22記載のメモリスイッチ。 - 前記能動素子は、前記一対の信号端子間に設けられる
請求項22記載のメモリスイッチ。 - 前記第1切替モードにおけるデータ書き込み時間が、前記第2切替モードにおけるそれよりも長い
請求項22記載のメモリスイッチ。 - 制御端子と、一対の信号端子と、前記一対の信号端子間に電気的に接続され、前記制御端子に印加される電圧信号によりその内部に印加される電界に応答してオン状態とオフ状態とが切り替わり、Naイオン及びClイオンを含む複数のイオン錯体が内部に分布する分子系を備える能動素子と、を有し、前記オフ状態と前記オン状態との間で切り替えを行うために前記制御端子に印加されるしきい値電圧が相対的に高い第1切替モード及び前記しきい値電圧が相対的に低い第2切替モードを有し、前記第1切替モードで前記能動素子に印加されて前記メモリスイッチを切り替える電界強度は、前記第2切替モードにおけるそれよりも高く、前記第1切替モードにおける切り替え時間が、前記第2切替モードにおけるそれよりも長い素子をスイッチングさせる方法であって、
前記制御端子に、前記信号端子に関する第1の極性の電圧信号を印加して、前記素子を前記オフ状態から前記オン状態に切り替え、前記能動素子のオン状態におけるインピーダンスがオフ状態におけるインピーダンスよりも低くなる段階と、
前記制御端子に、前記信号端子に関する前記第1極性とは逆の第2の極性を持つ電圧信号を印加して、前記素子を前記オン状態から前記オフ状態に切り替える段階と、を含む、
方法。
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US28905701P | 2001-05-07 | 2001-05-07 | |
US60/289,057 | 2001-05-07 | ||
PCT/US2002/014239 WO2002091494A1 (en) | 2001-05-07 | 2002-05-07 | Switch element having memeory effect |
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US6855977B2 (en) * | 2001-05-07 | 2005-02-15 | Advanced Micro Devices, Inc. | Memory device with a self-assembled polymer film and method of making the same |
US6844608B2 (en) | 2001-05-07 | 2005-01-18 | Advanced Micro Devices, Inc. | Reversible field-programmable electric interconnects |
WO2002091385A1 (en) * | 2001-05-07 | 2002-11-14 | Advanced Micro Devices, Inc. | Molecular memory cell |
JP4731794B2 (ja) * | 2001-05-07 | 2011-07-27 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | メモリ効果を有するスイッチ素子及び該素子をスイッチングさせる方法 |
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- 2002-05-07 KR KR1020037014468A patent/KR100895901B1/ko not_active IP Right Cessation
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CN100367528C (zh) | 2008-02-06 |
KR100895901B1 (ko) | 2009-05-04 |
US6809955B2 (en) | 2004-10-26 |
US7145793B1 (en) | 2006-12-05 |
US20020163829A1 (en) | 2002-11-07 |
CN1515039A (zh) | 2004-07-21 |
KR20040062446A (ko) | 2004-07-07 |
JP2005524967A (ja) | 2005-08-18 |
WO2002091494A1 (en) | 2002-11-14 |
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