JP4716836B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP4716836B2
JP4716836B2 JP2005291824A JP2005291824A JP4716836B2 JP 4716836 B2 JP4716836 B2 JP 4716836B2 JP 2005291824 A JP2005291824 A JP 2005291824A JP 2005291824 A JP2005291824 A JP 2005291824A JP 4716836 B2 JP4716836 B2 JP 4716836B2
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chip
upper chip
semiconductor device
recess
wiring board
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JP2007103680A (en
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篤人 水谷
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of further stabilizing ultrasonic-wave transmission even when a bonding pad of an upper chip and a terminal on a wiring board are connected by a thin metal wire. <P>SOLUTION: A lower chip 2 is mounted on the wiring board 1. The bonding pad of the lower chip 2 and the terminal on the wiring board 1 are connected by the thin metal wire 3. The upper chip 4 is mounted on the wiring board 1 so that the lower chip 2 is contained by a recess 6 provided to the lower face side of the upper chip 4. The bonding pad of the upper chip 4 and the terminal on the wiring board 1 are connected by the thin metal wire 3. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

本発明は、配線基板上でチップを積層するマルチチップスタックパッケージ構造の半導体装置に関するものである。   The present invention relates to a semiconductor device having a multi-chip stack package structure in which chips are stacked on a wiring board.

近年、電子機器の小型化、高機能化及び多機能化への要求がますます強くなってきている。半導体パッケージにおいて、このような要求に対応できる技術のひとつとして、複数のチップを同一パッケージにするマルチチップパッケージング技術がある。これは、それぞれのチップを個別にパッケージするものと比較して、複数のチップを積層して１つのパッケージにすることで、実装面積や重さを小さくすることが可能となる。   In recent years, there has been an increasing demand for downsizing, higher functionality, and multi-functionality of electronic devices. In a semiconductor package, as one of the technologies that can meet such a requirement, there is a multi-chip packaging technology that makes a plurality of chips the same package. This is because the mounting area and weight can be reduced by stacking a plurality of chips into one package as compared with the case where each chip is individually packaged.

例えば、２つのチップを積層する場合において、ワイヤボンドの接合領域を確保するためには、下側チップのサイズより上側チップのサイズを小さくするか、あるいは下側チップより小さいサイズのスペーサを下側チップと上側チップの間に挿入することにより、下側チップのボンディングパッドが上側チップによって遮蔽されないようにする必要がある。   For example, when two chips are stacked, in order to secure a wire bond bonding region, the size of the upper chip is made smaller than the size of the lower chip, or a spacer having a size smaller than the lower chip is placed on the lower side. It is necessary to prevent the bonding pads of the lower chip from being shielded by the upper chip by inserting between the chip and the upper chip.

そこで、従来（例えば、特許文献１を参照）は、図９に示すように、配線基板１上に接合された下側チップ２から離隔した位置に上側チップ４を保持するスペーサ１１を、下側チップ２の側面に沿って配線基板１に接着剤１０で接着して複数個配置するか、または対向する側辺に各１つずつ、合計２つのスペーサ１１を配置することによって、上側チップ４のサイズを下側チップ２のサイズより大きいものを積層するように構成する等の方法があった。
特開２００２−２２２８８９号公報 Therefore, conventionally (see, for example, Patent Document 1), as shown in FIG. 9, a spacer 11 that holds the upper chip 4 at a position separated from the lower chip 2 joined on the wiring board 1 is provided on the lower side. A plurality of spacers 11 are disposed along the side surface of the chip 2 by being bonded to the wiring board 1 with an adhesive 10 or two spacers 11 are disposed on the opposite sides. There has been a method in which a size larger than that of the lower chip 2 is stacked.
JP 2002-2222889 A

しかしながら上記のような従来の半導体装置では、複数個のスペーサを配置するため上側チップとスペーサ上面の平行度が出にくく、スペーサと上側チップとの接合性が不十分になる危険性があり、上側チップをワイヤボンドする際に、上側チップの撓みを減少させて超音波の伝達を安定させるためには、上側チップと保持するスペーサの接着力を強固にさせる必要があるという問題点を有していた。   However, in the conventional semiconductor device as described above, since a plurality of spacers are arranged, the parallelism between the upper chip and the upper surface of the spacer is difficult to occur, and there is a risk that the bonding property between the spacer and the upper chip becomes insufficient. When wire bonding the chip, in order to reduce the deflection of the upper chip and stabilize the transmission of ultrasonic waves, there is a problem that the adhesive force between the upper chip and the holding spacer needs to be strengthened. It was.

本発明は、上記従来の問題点を解決するもので、上側チップのボンディングパッドと配線基板上の端子を金属細線で接続する際にも、超音波の伝達をより安定させることができる半導体装置を提供する。   The present invention solves the above-described conventional problems, and a semiconductor device that can further stabilize the transmission of ultrasonic waves when the bonding pads of the upper chip and the terminals on the wiring board are connected by a thin metal wire. provide.

上記の課題を解決するために、本発明の請求項１記載の半導体装置は、配線基板と、前記配線基板上に実装された下側チップと、前記配線基板上に実装された上側チップとを備え、前記上側チップは、回路素子形成面とは反対面に、四角台形状の凹部と、前記凹部のコーナごとに前記凹部のコーナから前記上側チップの外側コーナにわたって形成した複数のＶ溝とを有し、前記下側チップが前記上側チップより小さく、前記上側チップが有する前記凹部に、前記下側チップを内包することを特徴とする。 In order to solve the above problem, a semiconductor device according to a first aspect of the present invention includes a wiring substrate, and a lower chip mounted on the wiring board, an upper chip mounted on the wiring substrate The upper chip includes a rectangular trapezoidal concave portion on a surface opposite to the circuit element forming surface, and a plurality of V grooves formed from the corner of the concave portion to the outer corner of the upper chip for each corner of the concave portion. And the lower chip is smaller than the upper chip, and the lower chip is included in the recess of the upper chip.

また、本発明の請求項２記載の半導体装置は、請求項１に記載の半導体装置であって、前記上側チップは前記凹部を一つ有し、前記上側チップが有する前記一つの凹部に、前記下側チップを一つ内包することを特徴とする。   A semiconductor device according to claim 2 of the present invention is the semiconductor device according to claim 1, wherein the upper chip has one of the recesses, and the one recess of the upper chip has the One lower chip is included.

また、本発明の請求項３記載の半導体装置は、請求項１に記載の半導体装置であって、前記上側チップは前記凹部を一つ有し、前記上側チップが有する前記一つの凹部に、前記下側チップを複数内包することを特徴とする。 The semiconductor device according to claim 3 of the present invention is the semiconductor device according to claim 1, wherein the upper chip has one of the recesses, and the one recess of the upper chip has the A plurality of lower chips are included.

また、本発明の請求項４記載の半導体装置は、回路素子形成面とは反対面に四角台形状ないし四角柱形状の一つの凹部を有し、その凹部に請求項２又は請求項３に記載の上側チップおよび下側チップを内包した状態で、前記配線基板上に実装されたチップを備えたことを特徴とする。 According to a fourth aspect of the present invention, there is provided the semiconductor device according to the second or third aspect of the present invention, wherein one concave portion having a quadrangular trapezoidal shape or a quadrangular prism shape is provided on the surface opposite to the circuit element forming surface. And a chip mounted on the wiring board in a state of including the upper chip and the lower chip.

以上のように本発明によれば、配線基板上に、上側チップをスペーサを用いることなく実装して、上側チップで下側チップを内包することにより、上側チップの撓みをなくすとともに、上側チップで複数個の下側チップを内包する際にも平行度を維持することができる。   As described above, according to the present invention, the upper chip is mounted on the wiring board without using a spacer, and the lower chip is included in the upper chip, so that the upper chip is not bent and the upper chip is used. Parallelism can be maintained even when a plurality of lower chips are included.

以上により、上側チップのボンディングパッドと配線基板上の端子を金属細線で接続する際にも、超音波の伝達をより安定させることができる。
また、上側チップの下面側の凹部から外側へ繋ぐように設けられた凹部により、封止樹脂を注入してパッケージングする際にも、樹脂の流れを妨害することなく成型することができる。 As described above, even when the bonding pads of the upper chip and the terminals on the wiring board are connected by the fine metal wires, the transmission of ultrasonic waves can be further stabilized.
Moreover, when the sealing resin is injected and packaged by the recess provided so as to be connected to the outside from the recess on the lower surface side of the upper chip, it can be molded without obstructing the flow of the resin.

また、上側チップの下面側の凹部から外側へ繋ぐように設けられた凹部により、下側チップと接続する配線基板上の端子が上側チップより外側に存在する場合でも、接続することができる。   Further, the concave portion provided so as to be connected to the outside from the concave portion on the lower surface side of the upper chip can be connected even when the terminal on the wiring board connected to the lower chip exists outside the upper chip.

以下、本発明の実施の形態を示す半導体装置について、図面を参照しながら具体的に説明する。
（実施の形態１）
本発明の実施の形態１の半導体装置を説明する。 Hereinafter, a semiconductor device showing an embodiment of the present invention will be specifically described with reference to the drawings.
(Embodiment 1)
A semiconductor device according to the first embodiment of the present invention will be described.

図１は本実施の形態１の半導体装置を示す構造図であり、図１（ａ）は本実施の形態１の半導体装置の断面図、図１（ｂ）は本実施の形態１の半導体装置の上側チップ下面から見た平面図を示す。   FIG. 1 is a structural diagram showing a semiconductor device according to the first embodiment, FIG. 1A is a cross-sectional view of the semiconductor device according to the first embodiment, and FIG. 1B is a semiconductor device according to the first embodiment. The top view seen from the upper chip | tip lower surface of this is shown.

図１において、１は配線基板、２は配線基板１上に実装された下側チップ、３は金属細線、４は配線基板１上に実装された上側チップ、５は半田ボール、６は上側チップ４の下面側に形成した上側チップ下面凹部（以下、単に「凹部」と記す）である。そして、凹部６は、上側チップ４の回路素子形成面とは反対面にあたる下面側に、四角台形状ないし四角柱形状に形成されている。   In FIG. 1, 1 is a wiring board, 2 is a lower chip mounted on the wiring board 1, 3 is a thin metal wire, 4 is an upper chip mounted on the wiring board 1, 5 is a solder ball, and 6 is an upper chip. 4 is an upper chip lower surface concave portion (hereinafter simply referred to as “concave portion”) formed on the lower surface side of 4. The recess 6 is formed in a quadrangular trapezoidal shape or a quadrangular prism shape on the lower surface side corresponding to the surface opposite to the circuit element formation surface of the upper chip 4.

本実施の形態１の半導体装置では、図１に示すように、下側チップ２が上側チップ４より小さく、下側チップ２のボンディングパッドと配線基板１上の端子とが金属細線３により接続されている。そして、この下側チップ２を上側チップ４が有する凹部６に内包するように、上側チップ４が実装されており、上側チップ４のボンディングパッドと配線基板１上の端子とが金属細線３により接続されている。また、配線基板１の下面側には、２次実装用の半田ボール５が形成されている。   In the semiconductor device of the first embodiment, as shown in FIG. 1, the lower chip 2 is smaller than the upper chip 4, and the bonding pads of the lower chip 2 and the terminals on the wiring substrate 1 are connected by the fine metal wires 3. ing. The upper chip 4 is mounted so that the lower chip 2 is enclosed in the recess 6 of the upper chip 4, and the bonding pads of the upper chip 4 and the terminals on the wiring substrate 1 are connected by the thin metal wires 3. Has been. A solder ball 5 for secondary mounting is formed on the lower surface side of the wiring board 1.

これらの構成により、上側チップ４が配線基板１とスペーサなどを介さずに直接接着できるため、上側チップ４にボンディングを行う際に、配線基板１に対する上側チップの平行度が維持でき、超音波の伝達を損なうことなく安定したボンディングが可能となる。
（実施の形態２）
本発明の実施の形態２の半導体装置を説明する。 With these configurations, since the upper chip 4 can be directly bonded to the wiring substrate 1 without using a spacer or the like, the parallelism of the upper chip with respect to the wiring substrate 1 can be maintained when bonding to the upper chip 4, and ultrasonic waves can be maintained. Stable bonding is possible without impairing transmission.
(Embodiment 2)
A semiconductor device according to a second embodiment of the present invention will be described.

図２は本実施の形態２の半導体装置を示す構造図であり、図２（ａ）は本実施の形態２の半導体装置の断面図、図２（ｂ）は本実施の形態２の半導体装置の上側チップ下面から見た平面図を示す。   FIG. 2 is a structural diagram showing the semiconductor device according to the second embodiment. FIG. 2A is a sectional view of the semiconductor device according to the second embodiment, and FIG. 2B is a semiconductor device according to the second embodiment. The top view seen from the upper chip | tip lower surface of this is shown.

本実施の形態２の半導体装置では、図２に示すように、実施の形態１で示した上側チップ４が有する凹部６を２つ設け、それぞれの凹部６に、下側チップ２を一つずつ内包した例である。   In the semiconductor device according to the second embodiment, as shown in FIG. 2, two recesses 6 included in the upper chip 4 shown in the first embodiment are provided, and one lower chip 2 is provided in each recess 6. This is an example of inclusion.

この構成により、実施の形態１と同様に、上側チップ４にボンディングを行う際に、配線基板１に対する上側チップの平行度が維持できるため、超音波の伝達を損なうことなく安定したボンディングが可能になる。また、全体として複数個（ここでは、２個の例を示す）の下側チップ２を上側チップ４に内包することが可能となる。
（実施の形態３）
本発明の実施の形態３の半導体装置を説明する。 With this configuration, as in the first embodiment, when bonding is performed on the upper chip 4, the parallelism of the upper chip with respect to the wiring substrate 1 can be maintained, so that stable bonding is possible without impairing the transmission of ultrasonic waves. Become. In addition, a plurality of (here, two examples) lower chips 2 can be included in the upper chip 4 as a whole.
(Embodiment 3)
A semiconductor device according to a third embodiment of the present invention will be described.

図３は本実施の形態３の半導体装置を示す構造図であり、図３（ａ）は本実施の形態３の半導体装置の断面図、図３（ｂ）は本実施の形態３の半導体装置の上側チップ下面から見た平面図を示す。   FIG. 3 is a structural diagram showing the semiconductor device according to the third embodiment. FIG. 3A is a sectional view of the semiconductor device according to the third embodiment, and FIG. 3B is a semiconductor device according to the third embodiment. The top view seen from the upper chip | tip lower surface of this is shown.

本実施の形態３の半導体装置では、図３に示すように、実施の形態１で示した上側チップ４が有する凹部６に、下側チップ２を複数個（ここでは、２個の例を示す）内包した例である。   In the semiconductor device according to the third embodiment, as shown in FIG. 3, a plurality of lower chips 2 (two examples are shown here) in the recess 6 of the upper chip 4 shown in the first embodiment. This is an example of inclusion.

この構成により、実施の形態２と同様に、上側チップ４にボンディングを行う際に、配線基板１に対する上側チップの平行度が維持できるため、超音波の伝達を損なうことなく安定したボンディングが可能となり、全体として複数個（ここでは、２個の例を示す）の下側チップ２を上側チップ４に内包することができる。
（実施の形態４）
本発明の実施の形態４の半導体装置を説明する。 With this configuration, as in the second embodiment, when bonding is performed on the upper chip 4, the parallelism of the upper chip with respect to the wiring board 1 can be maintained, so that stable bonding is possible without impairing the transmission of ultrasonic waves. As a whole, a plurality of lower chips 2 (here, two examples are shown) can be included in the upper chip 4.
(Embodiment 4)
A semiconductor device according to a fourth embodiment of the present invention will be described.

図４は本実施の形態４の半導体装置を示す構造図であり、図４（ａ）は本実施の形態４の半導体装置の断面図、図４（ｂ）は本実施の形態４の半導体装置の上側チップ下面から見た平面図を示す。図４において、７は上側チップ４が下面側に有する凹部６と上側チップ４の外側コーナとを繋ぐ凹部である。   FIG. 4 is a structural diagram showing the semiconductor device according to the fourth embodiment. FIG. 4A is a sectional view of the semiconductor device according to the fourth embodiment, and FIG. 4B is a semiconductor device according to the fourth embodiment. The top view seen from the upper chip | tip lower surface of this is shown. In FIG. 4, reference numeral 7 denotes a recess that connects the recess 6 that the upper chip 4 has on the lower surface side and the outer corner of the upper chip 4.

本実施の形態４の半導体装置は、図４に示すように、実施の形態１で示した上側チップ４が有する凹部６の各コーナから、それぞれ上側チップ４の外側コーナにわたって、凹部６と上側チップ４の外側とを繋ぐように凹部７を設けた例である。   As shown in FIG. 4, the semiconductor device according to the fourth embodiment has a recess 6 and an upper chip extending from each corner of the recess 6 included in the upper chip 4 shown in the first embodiment to the outer corner of the upper chip 4. 4 is an example in which a concave portion 7 is provided so as to connect the outer side of 4.

この構成により、実施の形態１と同様に、上側チップ４にボンディングを行う際に、配線基板１に対する上側チップの平行度が維持できるため、超音波の伝達を損なうことなく安定したボンディングが可能になる。   With this configuration, as in the first embodiment, when bonding is performed on the upper chip 4, the parallelism of the upper chip with respect to the wiring substrate 1 can be maintained, so that stable bonding is possible without impairing the transmission of ultrasonic waves. Become.

さらに、上側チップ４の凹部６と上側チップ４の外側コーナを繋ぐ凹部７を設けることで、樹脂封止をおこなうパッケージに対しても、上側チップの凹部６の内部にも樹脂を充填することができるため、装置の信頼性を向上することが可能となる。   Furthermore, by providing the recess 7 that connects the recess 6 of the upper chip 4 and the outer corner of the upper chip 4, it is possible to fill the resin into the recess 6 of the upper chip even for a package that performs resin sealing. Therefore, the reliability of the apparatus can be improved.

なお、上側チップ４の凹部６と外側コーナを繋ぐ凹部７は、Ｖ溝あるいは四角柱形状である。
（実施の形態５）
本発明の実施の形態５の半導体装置を説明する。 In addition, the recessed part 7 which connects the recessed part 6 and the outer corner of the upper chip 4 has a V-shaped groove or a quadrangular prism shape.
(Embodiment 5)
A semiconductor device according to a fifth embodiment of the present invention will be described.

図５は本実施の形態５の半導体装置を示す構造図であり、図５（ａ）は本実施の形態５の半導体装置の断面図、図５（ｂ）は本実施の形態５の半導体装置の上側チップ下面から見た平面図を示す。   FIG. 5 is a structural diagram showing the semiconductor device according to the fifth embodiment. FIG. 5A is a sectional view of the semiconductor device according to the fifth embodiment, and FIG. 5B is a semiconductor device according to the fifth embodiment. The top view seen from the upper chip | tip lower surface of this is shown.

本実施の形態５の半導体装置は、図５に示すように、実施の形態４で示した上側チップ４が有する凹部６の各コーナから、それぞれ上側チップ４の外側コーナにわたって、凹部６と上側チップ４の外側とを繋ぐように凹部７を設け、上側チップ４が有する凹部６に複数個（ここでは、２個の例を示す）の下側チップ２を内包した例である。   As shown in FIG. 5, the semiconductor device according to the fifth embodiment has a recess 6 and an upper chip extending from each corner of the recess 6 included in the upper chip 4 shown in the fourth embodiment to the outer corner of the upper chip 4. This is an example in which a recess 7 is provided so as to connect the outer side of 4, and a plurality of (two examples are shown) lower chips 2 are included in the recess 6 of the upper chip 4.

この構成により、実施の形態４と同様の効果が得ることが可能になり、さらに上側チップ４が有する凹部６に、全体として複数個（ここでは、２個の例を示す）の下側チップ２を内包することができる。
（実施の形態６）
本発明の実施の形態６の半導体装置を説明する。 With this configuration, it is possible to obtain the same effect as that of the fourth embodiment, and a plurality of lower chips 2 (here, two examples are shown) as a whole in the recesses 6 of the upper chip 4. Can be included.
(Embodiment 6)
A semiconductor device according to a sixth embodiment of the present invention will be described.

図６は本実施の形態６の半導体装置を示す構造図であり、図６（ａ）は本実施の形態６の半導体装置の断面図、図６（ｂ）は本実施の形態６の半導体装置の上側チップ下面から見た平面図を示す。図６において、８は上側チップ４が有する凹部６と上側チップ４の外側の各辺とを繋ぐ凹部である。   6 is a structural diagram showing the semiconductor device of the sixth embodiment, FIG. 6A is a cross-sectional view of the semiconductor device of the sixth embodiment, and FIG. 6B is a semiconductor device of the sixth embodiment. The top view seen from the upper chip | tip lower surface of this is shown. In FIG. 6, reference numeral 8 denotes a recess that connects the recess 6 included in the upper chip 4 and each side outside the upper chip 4.

本実施の形態６の半導体装置は、図６に示すように、実施の形態１で示した上側チップ４が有する一つの凹部６の各辺から、それぞれ上側チップ４の外側辺にわたって、凹部６と上側チップ４の外側とを繋ぐように凹部８を設けた例である。   As shown in FIG. 6, the semiconductor device of the sixth embodiment includes a recess 6 and a recess 6 extending from each side of one recess 6 of the upper chip 4 shown in the first embodiment to the outer side of the upper chip 4. This is an example in which a recess 8 is provided so as to connect the outside of the upper chip 4.

この構成により、実施の形態１と同様に、上側チップ４にボンディングを行う際に、配線基板１に対する上側チップの平行度が維持できるため、超音波の伝達を損なうことなく安定したボンディングができる。   With this configuration, as in the first embodiment, when bonding is performed on the upper chip 4, the parallelism of the upper chip with respect to the wiring substrate 1 can be maintained, so that stable bonding can be performed without impairing the transmission of ultrasonic waves.

また、実施の形態４と同様に、上側チップ４に上側チップ下面凹部６と上側チップ４の各辺を繋ぐ凹部８を設けることで、樹脂封止をおこなうパッケージに対しても、上側チップ下面凹部６内部にも樹脂を充填することができるため、信頼性をより向上することが可能となる。   Similarly to the fourth embodiment, the upper chip lower surface recess 6 is provided in the upper chip 4 by providing the upper chip lower surface recess 6 and the recess 8 that connects each side of the upper chip 4 with respect to the package for resin sealing. Since the resin can be filled in the interior of the battery 6, the reliability can be further improved.

さらに、上側チップ下面凹部６と上側チップ４の各辺を繋ぐ凹部８を設けることで、封止樹脂の流動性の向上ができるとともに、配線基板１と下側チップ２を金属細線３で繋ぐ２ｎｄボンディング部が、配線基板１上の上側チップ４より外側に存在する場合でも、ボンディングを可能にすることができる。
（実施の形態７）
本発明の実施の形態７の半導体装置を説明する。 Furthermore, by providing the recesses 8 that connect the sides of the upper chip lower surface recess 6 and the upper chip 4, the fluidity of the sealing resin can be improved, and the wiring substrate 1 and the lower chip 2 are connected by the thin metal wires 2nd. Even when the bonding portion exists outside the upper chip 4 on the wiring substrate 1, bonding can be made possible.
(Embodiment 7)
A semiconductor device according to a seventh embodiment of the present invention will be described.

図７は本実施の形態７の半導体装置を示す構造図であり、図７（ａ）は本実施の形態７の半導体装置の断面図、図７（ｂ）は本実施の形態７の半導体装置の上側チップ下面から見た平面図を示す。   FIG. 7 is a structural diagram showing the semiconductor device according to the seventh embodiment. FIG. 7A is a sectional view of the semiconductor device according to the seventh embodiment, and FIG. 7B is a semiconductor device according to the seventh embodiment. The top view seen from the upper chip | tip lower surface of this is shown.

本実施の形態７の半導体装置は、図７に示すように、実施の形態６で示した上側チップ４が有する一つの凹部６の各辺から、それぞれ上側チップ４の外側辺にわたって、凹部６と上側チップ４の外側とを繋ぐように凹部８を設け、上側チップ４が有する凹部６に複数個（ここでは、２個の例を示す）の下側チップ２を内包した例である。   As shown in FIG. 7, the semiconductor device according to the seventh embodiment includes a recess 6 and a recess 6 extending from each side of one recess 6 included in the upper chip 4 shown in the sixth embodiment to the outer side of the upper chip 4. This is an example in which a recess 8 is provided so as to connect the outside of the upper chip 4, and a plurality of (two examples are shown) lower chips 2 are included in the recess 6 of the upper chip 4.

この構成により、実施の形態６と同様の効果が得ることが可能になり、さらに、上側チップ４が有する凹部６に、全体として複数個（ここでは、２個の例を示す）の下側チップ２を内包することができる。
（実施の形態８）
本発明の実施の形態８の半導体装置を説明する。 With this configuration, it is possible to obtain the same effect as that of the sixth embodiment. Furthermore, a plurality of lower chips (here, two examples are shown) as a whole in the recesses 6 of the upper chip 4. 2 can be included.
(Embodiment 8)
A semiconductor device according to an eighth embodiment of the present invention will be described.

図８は本実施の形態８の半導体装置の構造を示す断面図である。図８において、９は上側チップ４および下側チップ２を内包するチップである。
本実施の形態８の半導体装置は、図８に示すように、チップ９が、回路素子形成面とは反対面に四角台形状ないし四角柱形状の一つの凹部を有し、その凹部に、実施の形態３で示した半導体装置における上側チップ４および下側チップ２を内包するように構成した例である。なお、これまでに記載した各実施の形態の半導体装置における上側チップ４および下側チップ２を内包するように構成してもよい。 FIG. 8 is a sectional view showing the structure of the semiconductor device according to the eighth embodiment. In FIG. 8, reference numeral 9 denotes a chip including the upper chip 4 and the lower chip 2.
In the semiconductor device according to the eighth embodiment, as shown in FIG. 8, the chip 9 has one concave portion of a square trapezoidal shape or a rectangular column shape on the surface opposite to the circuit element forming surface. This is an example in which the upper chip 4 and the lower chip 2 in the semiconductor device shown in the third embodiment are included. In addition, you may comprise so that the upper chip | tip 4 and the lower chip | tip 2 in the semiconductor device of each embodiment described so far may be included.

この構成により、これまで同様の効果が得られるとともに、さらに、より複数のチップを内包することが可能になる。
なお、以上に記載した全ての実施の形態において、配線基板１と下側チップ２ないし配線基板１と上側チップ４との接着には、絶縁性ペーストあるいは絶縁性ダイアタッチフィルムなどを適用することが可能である。 With this configuration, the same effect as before can be obtained, and more than one chip can be included.
In all the embodiments described above, an insulating paste or an insulating die attach film may be applied to the wiring substrate 1 and the lower chip 2 or the bonding between the wiring substrate 1 and the upper chip 4. Is possible.

本発明の半導体装置は、マルチチップスタックパッケージ技術によりパッケージサイズや重さ及び実装面積を小さくできることから、特に小型軽量化が要求される携帯用電話機器などの情報通信機器に搭載する半導体装置として有用である。   The semiconductor device of the present invention is useful as a semiconductor device to be mounted on information communication equipment such as portable telephone equipment that is particularly required to be reduced in size and weight because the package size, weight, and mounting area can be reduced by the multi-chip stack package technology. It is.

本発明の実施の形態１の半導体装置を示す構造図Structural diagram showing a semiconductor device according to the first embodiment of the present invention. 本発明の実施の形態２の半導体装置を示す構造図Structural diagram showing a semiconductor device according to a second embodiment of the present invention. 本発明の実施の形態３の半導体装置を示す構造図Structural diagram showing a semiconductor device according to a third embodiment of the present invention. 本発明の実施の形態４の半導体装置を示す構造図Structural diagram showing a semiconductor device according to a fourth embodiment of the present invention. 本発明の実施の形態５の半導体装置を示す構造図Structural diagram showing a semiconductor device according to a fifth embodiment of the present invention. 本発明の実施の形態６の半導体装置を示す構造図Structural diagram showing a semiconductor device according to a sixth embodiment of the present invention. 本発明の実施の形態７の半導体装置を示す構造図Structural diagram showing a semiconductor device according to a seventh embodiment of the present invention. 本発明の実施の形態８の半導体装置を示す構造図Structural diagram showing a semiconductor device according to an eighth embodiment of the present invention. 従来の半導体装置を示す構造図Structure diagram showing a conventional semiconductor device

符号の説明Explanation of symbols

１ 配線基板
２ 下側チップ
３ 金属細線
４ 上側チップ
５ 半田ボール
６ 上側チップ下面凹部
７ （上側チップの下面凹部と上側チップのコーナを繋ぐ）凹部
８ （上側チップの下面凹部と上側チップの各辺を繋ぐ）凹部
９ （上側チップを内包する）チップ
１０ 接着剤
１１ スペーサ DESCRIPTION OF SYMBOLS 1 Wiring board 2 Lower chip | tip 3 Metal thin wire 4 Upper chip 5 Solder ball 6 Upper chip lower surface recessed part 7 (Connecting the lower surface recessed part of an upper chip, and the corner of an upper chip) Recessed 8 (Lower surface recessed part of an upper chip, and each side of an upper chip Recessed part 9 (Inside the upper chip included) Chip 10 Adhesive 11 Spacer

Claims (4)

配線基板と、
前記配線基板上に実装された下側チップと、
前記配線基板上に実装された上側チップとを備え、
前記上側チップは、回路素子形成面とは反対面に、四角台形状の凹部と、前記凹部のコーナごとに前記凹部のコーナから前記上側チップの外側コーナにわたって形成した複数のＶ溝とを有し、
前記下側チップが前記上側チップより小さく、前記上側チップが有する前記凹部に、前記下側チップを内包することを特徴とする半導体装置。 A wiring board;
A lower chip mounted on the wiring board;
And a upper chip mounted on the wiring board,
The upper chip has a rectangular trapezoidal concave portion on a surface opposite to the circuit element forming surface, and a plurality of V grooves formed from the corner of the concave portion to the outer corner of the upper chip for each corner of the concave portion. ,
The lower chip is smaller than the upper chip, and the lower chip is included in the recess of the upper chip. 前記上側チップは前記凹部を一つ有し、
前記上側チップが有する前記一つの凹部に、前記下側チップを一つ内包する
ことを特徴とする請求項１に記載の半導体装置。 The upper tip has one recess,
The semiconductor device according to claim 1, wherein one lower chip is included in the one recess of the upper chip. 前記上側チップは前記凹部を一つ有し、
前記上側チップが有する前記一つの凹部に、前記下側チップを複数内包する
ことを特徴とする請求項１に記載の半導体装置。 The upper tip has one recess,
The semiconductor device according to claim 1, wherein a plurality of the lower chips are included in the one concave portion of the upper chip. 回路素子形成面とは反対面に四角台形状の一つの凹部を有し、
その凹部に請求項２又は請求項３に記載の上側チップおよび下側チップを内包した状態で、前記配線基板上に実装されたチップを備えた
ことを特徴とする半導体装置。 It has one concave part with a square trapezoidal shape on the surface opposite to the circuit element forming surface
A semiconductor device comprising a chip mounted on the wiring board in a state in which the upper chip and the lower chip according to claim 2 or 3 are included in the recess.
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JP2004128356A (en) * 2002-10-04 2004-04-22 Fujitsu Ltd Semiconductor device
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JP2005203776A (en) * 2004-01-13 2005-07-28 Samsung Electronics Co Ltd Multichip package, semiconductor device used for the same, and manufacturing method thereof
JP2005251898A (en) * 2004-03-03 2005-09-15 Mitsubishi Electric Corp Wafer level package structure and its manufacturing method, and element divided from its wafer level package structure

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
JP2004128356A (en) * 2002-10-04 2004-04-22 Fujitsu Ltd Semiconductor device
JP2004311785A (en) * 2003-04-08 2004-11-04 Olympus Corp Semiconductor device
JP2005203776A (en) * 2004-01-13 2005-07-28 Samsung Electronics Co Ltd Multichip package, semiconductor device used for the same, and manufacturing method thereof
JP2005251898A (en) * 2004-03-03 2005-09-15 Mitsubishi Electric Corp Wafer level package structure and its manufacturing method, and element divided from its wafer level package structure

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